KR100216255B1 - Interface circuit for multiprocessor system - Google Patents

Abstract

The present invention provides an interface of a multiprocessor system to interconnect two P6 buses and a system memory bus and control their operation in order to solve the limitation of the number of processors for one P6 bus of the Intel Pentium processor. In the dual-ported memory architecture, two P6 buses and a memory bus are connected to each other via an address ASIC to control the organic interface between the buses. The address ASIC is an arbitration logic (1) that performs arbitration for I / O requests on the P6 bus, and a master (2) (3), IOQ (4) (5), snoop (6) (7), and memory. It consists of a controller 8, a data ASIC 9, an SDRAM 10, an address decoder 11, 12, an operation decoder 13, 14, and the like.

Description

Interface Processing Circuit of Multiprocessor System

TECHNICAL FIELD The present invention relates to a multiprocessor system, and in particular, to solve the numerical limitation of a processor for one P6 bus of an Intel Pentium processor, it is possible to interconnect two P6 buses and a system memory bus and control their operation. To an interface processing circuit of a multiprocessor system.

Previously, Intel's Pentium Pro system can only support up to four Pentium Pro processors on a single P6 bus due to its electrical characteristics.

Many applications, however, require more than four processors, and their inherent Intel specifications can't satisfy them.

The present invention has been made to solve such a conventional problem, the interface of a multiprocessor system that can control the organic interface between the bus by connecting two P6 bus and the memory bus in a dual-ported memory structure to each other The purpose is to provide a processing circuit.

The present invention for achieving the above object is characterized by comprising an address ASIC between the two P6 bus and the memory bus.

A structural feature of the present invention is that the address ASIC is connected to an arbitration logic, which performs arbitration for I / O requests on the P6 bus, and a master, which is connected to the arbitration logic to perform operations on two P6 buses. IOQ to store the request requested in order to perform sequential memory operations, snoop used to maintain cache coupling between the first address bus and the second address bus, and connected to IOQ to transfer operations to the memory and control them. A memory controller, a data ASIC that performs data control by a control signal of a memory controller, an SDRAM that stores data from a data ASIC or supplies data to a data ASIC, and checks whether or not IOQ is waiting for an address occurring on each bus. Address decoder, offers for cycles on each bus It consists of an operation decoder that checks for a conversion type.

1 is a block diagram of an interface processing circuit of the invention multiprocessor system.

* Explanation of symbols for main parts of the drawings

1: arbitration logic 2, 3: master

4, 5: IOQ 6, 7: Snoop

8: memory controller 9: data ASIC

10: SDRAMP 11, 12: Address decoder

13, 14: operation decoder 20: address ASIC

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the present invention, which is an arbitration logic (1) that performs arbitration for I / O requests on a P6 bus and a reflection of operations occurring on two P6 buses connected to the arbitration logic (1). A master (2) (3), an In-Order-Queue (IO) (4) (5) for storing sequential memory operations to be performed on the P6 bus and performing a sequential memory operation, and the first address bus ( Data by the control signal of the snoop (6) (7) and the IOQ (4) (5) and the connected memory controller (8) used to maintain the cache coupling between the B1) and the second address bus (B2). The data ASIC 9 which performs control, the SDRAM 10 which stores data from the data ASIC 9 or supplies data to the data ASIC 9, and the IOQ 4 for the address occurring on each bus. Address decoder 11 (12) which checks whether or not Queuing It consists of an operation decoder 13 (14) for checking the operation type for the cycle, and in the figure, reference numerals D1 and D2 refer to data addresses, and 1 to 14 except for 9 and 10 are one. To form the address ASIC 20.

According to the present invention, the address ASIC 20 located between the address bus B1 and the system memory bus controls the operation of each bus and the interface between three buses separated from each other.

At this time, the address ASIC 20 transmits bus signals to the memory bus so that operations occurring in two address buses B1 and B2 are transmitted to the memory bus and controls the data ASIC 20 for data pet path.

The address ASIC 20 also performs arbitration of controllers connected on the bus.

If operations on one address bus (e.g. B1) are likely to cause coupling problems for processors on another address bus (e.g. B2), then operations on B1 will be reflected to the B2 bus. Control so that

Looking specifically at the operation of the present invention, when an I / O request is received from B1 (on P6 address bus A), arbitration is performed by arbitration logic 1 in the address ASIC 20.

That is, the address decoder 11 and the operation decoder 13 on the B1 side determine what kind of operation and what time is required with the address and type information transmitted to the arbitration logic 1.

Then, the result of the arbitration logic 1 is transmitted to the IOQ 4.

If the required operation needs to be reflected on the B2 side, the IOQ 4 transmits the necessary information to the master block 3, and the master block 3 transmits this information to B2 (on the P6 bus B).

In addition, the snooping result by the information transmitted to the B2 side is returned to the IOQ 4 on the B1 side through the snoop 7.

When the required operation needs to be reflected on the B2 side, the IOQ 4 transmits the necessary information to the master block 3 on the B2 side, and the master block 3 transmits the information on the B2 address. It has all the information about the ASIC 20 and sends this information to the data ASIC 9.

The actual data is transmitted from the memory controller 8, and the control signal necessary for this is continuously transmitted to the data ASIC 9.

If an I / O request comes in from B2, the operation proceeds as described above.

The present invention as described above can reduce the cost by simplifying the circuit configuration, and in particular, in the computer system (for example, Hiserver UX 9000) has the effect that can be extended to eight processors.

Claims (1)

An arbitration logic (1) that conducts arbitration for I / O requests on the P6 bus, and a master (2) (3) connected to the arbitration logic (1) to perform operations on two P6 buses; And maintaining the cache coupling between the first address bus B1 and the second address bus B2 so as to store the requests requested in the P6 bus so that a sequential memory operation may be performed. A memory controller 8 connected to the snoop 6 and 7 and an IOQ 4 and 5 for transmitting and controlling the operation toward the memory, and control of the memory controller 8. A data ASIC 9 that performs data control by a signal, an SDRAM 10 that stores data from the data ASIC 9 or supplies data to the data ASIC 9, and an address generated on each bus. To check whether or not to wait for IOQ (4) (5) Coders 11 and 12 and, the interface of the multiprocessor system, characterized in that the processing circuit is configured to include the operation decoder (13, 14) for checking the operation taip on a cycle takes place at each bus.

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