KR100195206B1 - Semiconductor isolation method using trench - Google Patents

Abstract

In the method of separating a semiconductor device, a method of separating a semiconductor device using a trench in which an impurity layer is formed only in the trench shoulder portion is described. This method includes sequentially depositing a pad insulating film and an etch stop layer on the entire surface of the substrate, forming an etch stop layer pattern and a pad insulating film pattern to expose an inactive region of the substrate by patterning the etch stop layer and the pad insulating film, and etching the etch stop layer pattern. Forming a trench by etching the exposed substrate using an insulating film, forming an insulating film on the trench sidewalls and the bottom surface, and forming an insulating material layer by depositing an insulating material on the entire surface of the resultant substrate to fill the trench; Etching the insulating material layer to expose the etch stop layer pattern, removing the etch stop layer pattern, etching the insulating material layer so that the surface of the etched insulating material layer is lower than the surface of the substrate, and the insulating material layer is planted. Impurities by ion implantation of impurities into the front surface of each resulting substrate A method of separating a semiconductor device using a trench, the method comprising forming a layer and etching a substrate in an active region so that an impurity layer remains only in the shoulder portion of the trench. As a result, an impurity layer may be formed only on the trench shoulders so as to improve separation characteristics of the semiconductor device.

Description

Semiconductor Device Separation Method Using Trench

1 through 4 are cross-sectional views sequentially illustrating a method of separating a semiconductor device using a conventional trench.

5 and 6 are cross-sectional views illustrating a conventional method for solving the problem of the device isolation method using a conventional trench.

7 to 13 are cross-sectional views sequentially shown to explain an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device isolation method using a trench that realizes device separation between semiconductor devices by forming an impurity layer in the trench shoulder.

In manufacturing a conventional semiconductor device, the electrical separation method between the devices formed on the same substrate is roughly divided into a device isolation method using a local oxidation (LoCal Oxidation of Silicon, LOCOS) method and a device separation method using a trench can do. In the early stages of fabrication of semiconductor devices with low integration of semiconductor devices, separation of semiconductor devices was realized mainly by the former method, that is, the LOCOS method, due to the simplicity of self-process.

However, in the device isolation method using the LOCOS method, as the degree of integration of semiconductor devices increases, it is difficult to realize a fine line width of the device isolation region, and when thermal oxidation occurs during the formation of the device isolation region, Due to the occurrence of bird's beak at the boundary and the necessity of forming the field oxide film in a thin film, the current method of separating the device is no longer effective in the fabrication of highly integrated semiconductor devices. It could not be.

Therefore, at present, electrical separation between semiconductor elements is realized by forming a trench in the latter method, that is, in the device isolation region of the substrate, rather than the former method. The method of separating a semiconductor device using the trench can overcome some of the above-described problems of the former method, that is, the device separation method by the LOCOS method, in particular, the effective device separation length for the same device separation width. In view of the fact that the (Effective Isolation Length) can be realized at a long time, it has been generalized as a method for separating semiconductor devices.

However, the semiconductor device isolation method using the trench also has another problem in the manufacture of the actual semiconductor device, which is as follows.

First, in the device isolation method using trenches, since the sidewalls of the trenches are formed almost perpendicular to the surface of the device active region at the trench shoulders bordering the trenches, the gate electric field in the MOS transistor is concentrated at the trench shoulders. This is a problem in which the Humph characteristic that is twice turned on is generated.

Second, as the width of the device active region of the substrate decreases, an inverse narrow width effect occurs in which the threshold voltage V _th of the transistor decreases.

Therefore, in order to solve the above-mentioned two problems, the current isolation method using trenches may first form a trench in the device isolation region of the substrate, and then form a slow loop of the trench shoulder portion or a trench shoulder portion by a subsequent process. A method of doping impurities is used.

However, of the above two device characteristic improvement methods, the latter method, that is, the method of doping the impurities in the trench shoulder portion, is used when doping impurities, for example, the method of doping the impurities by the ion implantation method is a region other than the trench shoulder portion, That is, impurities may be doped in the active region of the same substrate where the device is directly formed. Fortunately, when doping of such impurities is required separately, other problems may arise if doping of impurities is not necessary. That is, in the case where doping of impurity dopants in the active region of the semiconductor substrate occurs, the first problem may cause an increase in parasitic junction capacitance in the MOS transistor formed in the region, and impurity ion implantation for doping the impurity The second problem is that the ion implant having high energy impinges on the surface of the substrate while colliding with the surface of the substrate, thereby degrading the refresh characteristics of the device by increasing the junction leakage current, and the insulating material filling the trench. A subsequent high temperature heat treatment process is carried out for densification of the device, whereby impurity having a conductivity type opposite to the impurity in the device active region is redistributed by thermal diffusion of impurity counter-doped by a subsequent process. The third problem is that it becomes difficult to control.

Hereinafter, a general separation method of a semiconductor device using a conventional trench will be described with reference to the accompanying drawings, and the problem thereof will be described in detail.

1 through 6 are cross-sectional views sequentially illustrating a method of separating a semiconductor device using a conventional trench.

FIG. 1 is a cross-sectional view illustrating the formation of a pad insulating film pattern 15 and an etch stop layer pattern 20 having an opening 25 exposing a predetermined portion on a substrate 10, which is a pad insulating film on a substrate 10. And the pad insulating layer pattern 15 and the etch stop layer pattern having a first process of sequentially stacking an etch stop layer and an opening 25 to expose a predetermined portion of the substrate 10 by patterning the pad insulating layer and the etch stop layer. It proceeds to the 2nd process of forming 20).

FIG. 2 is a cross-sectional view illustrating the formation of the trench 30 in the substrate 10 exposed by the pad insulating film pattern 15 and the etch stop layer pattern 20 and the thin film insulating film 35 formed on the sidewall thereof. As an etching mask, the first process of forming the trench 30 by etching the exposed portion of the substrate 10 using the etch stop layer pattern 20 as an etch mask and on the sidewalls and the bottom surface of the trench 30 is performed. The thermal process proceeds to the second step of forming the insulating film 35 of the thin film.

FIG. 3 is a cross-sectional view illustrating the formation of an insulating material layer 40 deposited on the entire surface of the substrate 10 to completely fill the trench 30, which completely fills the trench 30 while the etching is performed. The process of forming the insulating material layer 40 thickly by chemical vapor deposition (CVD) on the prevention layer pattern 20 is performed.

4 is a cross-sectional view illustrating a planarized insulating material layer pattern 40a formed in an isolation region of the substrate 10, which is a first process of planarizing to a display part of FIG. 3 and a display part of FIG. 3. The second process of removing the material layers 20 and 15 stacked on the substrate 10 and the resultant are planarized to form the insulating material layer pattern 40a.

The implementation of the semiconductor device isolation method using the above-described trenches must be a useful method in the fabrication of semiconductor devices in the integration trend as compared to the device isolation method using the conventional LOCOS method. However, the method using the simple trench described above also has two problems as described above, and the following improvement efforts have been made.

5 and 6 are cross-sectional views illustrating a conventional improvement method for solving a problem of a device isolation method using a conventional trench.

FIG. 5 is a cross-sectional view illustrating the formation of an impurity layer 37 along the inner wall of the trench 30 by ion implantation of impurities 36 over the entire surface of the resultant substrate of FIG. 2. The impurity layer 37 is formed by thinly injecting the etch stop layer pattern 20 and the pad insulating layer pattern 15 as an ion implantation mask through the insulating layer 35 on the trench 30.

However, the improvement method described in FIG. 5 improves the parasitic capacitance of the MOS transistor by forming an impurity doped layer 37 which is not doped with impurities only in the shoulder of the trench 30 and is doped with impurities throughout the inner wall of the trench 30. In addition to the increase, as well as impurity implantation, the substrate surface is damaged to increase the junction leakage current.

FIG. 6 is a cross-sectional view showing that the impurity layer 42 of the shoulder portion of the trench 30 is formed and the top surface thereof is flattened, which is a front surface of the resultant substrate after the first process in the description of FIG. 4. The impurity layer 41 is ion implanted using the planarized etch stop layer pattern 20a as an ion implantation mask to form the impurity layer 42 at the shoulder portion of the trench 30.

This may somewhat solve the problem of the improvement method described with reference to FIG. 5. However, since the planarized etch stop layer pattern 20a exists during the ion implantation, the impurity layer 42 as shown in FIG. The adjustment for the formation of can not proceed easily in the actual process. That is, it is very difficult to form the impurity layer 42 shown in FIG. 6 by the above method in the actual process.

Accordingly, an object of the present invention is to provide a method of separating a semiconductor device using a trench that effectively forms an impurity layer only in a trench shoulder portion so as to improve a problem of the conventional method of separating a semiconductor device using a trench.

In order to achieve the object of the present invention,

Sequentially stacking a pad insulating film and an etch stop layer on the entire surface of the substrate;

Patterning the etch stop layer and the pad insulating film to form an etch stop layer pattern and a pad insulating film pattern exposing an inactive region of the substrate;

Forming a trench by etching the exposed substrate using the etch stop layer pattern as an etch mask;

Forming an insulating film on the trench sidewalls and a bottom surface;

A fifth step of forming an insulating material layer by depositing an insulating material on the entire surface of the resultant substrate so as to fill the inside of the trench;

Etching the insulating material layer to expose the etch stop layer pattern;

A sixth step of removing the etch stop layer pattern;

Etching the insulating material layer so that the surface of the etched insulating material layer is lower than the surface of the substrate;

An eighth step of forming an impurity layer by ion implanting impurities into the entire surface of the resultant substrate from which the insulating material layer is re-etched; And

And a ninth step of etching the substrate in the active region so that an impurity layer remains only in the shoulder portion of the trench.

The object of the present invention can be preferably achieved by the following various. The pad insulating layer of the first step may be formed using an oxide, and the etch stop layer may be formed using silicon nitride (SiN). Meanwhile, the etch stop layer is formed to have a thickness of 1000 kPa to 4000 kPa, the trench of the second step is formed to have a depth of 3000 kPa to 5000 kPa, and the insulating film of the fourth step uses a thermal oxide film having a thickness of about 1000 kPa. It is preferable to form.

The insulating material layer of the fifth step is formed using a chemical vapor deposition (CVD) oxide film, and the planarization of the sixth step is preferably performed using a chemical mechanical polishing (CMP) method. The etch stop layer pattern of the sixth step is removed using a phosphoric acid solution, and the etch of the seventh step uses a wet etching method, wherein the exposed pad insulating layer pattern and the protruding insulating material layer It is preferable to use an etchant having an etching selectivity of 1:10 or less, and a representative example thereof may include BOE (Buffered Oxide Isolation) solution.

The recessed insulating material layer of the seventh step is formed to a depth of about 500 Å with respect to the exposed substrate, and the etching of the tenth step is to use a chemical dry etching method, wherein It is preferable to form the insulating material layer so as to protrude about 500 kPa from the surface of the substrate by etching in 10 steps.

Particularly, after the first step, the method may further include forming an oxide layer on the pad insulating layer and the etch stop layer and forming an oxide layer pattern used to etch the etch stop layer and the pad insulating layer by patterning the oxide layer. Can be.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

7 to 13 are cross-sectional views sequentially shown to explain an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating the formation of a pad insulating film pattern 115 and an etch stop layer pattern 120 having an opening that exposes a predetermined portion on the substrate 100, which is a pad insulating film and an etch stop layer on the substrate 110. The first step of sequentially stacking the photoresist to the pad insulating layer and the etch stop layer, and the pad insulating layer pattern 115 and the etch stop layer pattern having the opening 125 to expose a predetermined portion of the substrate 110. Proceeds to the second step of forming 120). In this case, the pad insulating film is formed of a thin film to improve the profile of the surface of the substrate 110.

FIG. 8 is a cross-sectional view illustrating the formation of the trench 130 in the substrate exposed by the pad insulating layer pattern 115 and the etch stop layer pattern 120 and the thin film insulating layer 135 formed on the sidewall thereof. A first process of forming the trench 130 by etching the exposed portion of the substrate 110 using the etch stop layer pattern 120 as an etch mask with respect to the resultant substrate of FIG. 7 and sidewalls of the trench 130. And a second process of forming the insulating film 135 of the thin film on the bottom surface by a thermal oxidation method. At this time, the trench 130 is formed to have a depth of 3000 ~ 5000Å. Meanwhile, after the pad insulating film and the etch stop layer of FIG. 1 are formed, an oxide film (not shown) is further laminated thereon, and an oxide film pattern (not shown) defining an element isolation region is formed on the oxide film. Thereafter, the trench may be formed by etching the etch stop layer, the pad insulating layer, and the substrate exposed by the oxide layer pattern using the etching mask. On the other hand, the insulating film 135 of the thin film formed by the second process is formed to have a thickness of less than 1000Å. This is formed for the purpose of adjusting the profile of the inner surface of the trench 130 and the boundary of the device active region, and is usually formed by a thermal oxidation process.

FIG. 9 is a cross-sectional view illustrating the formation of an insulating material layer 140 deposited on the entire surface of the substrate so as to completely fill the inside of the trench, which completely fills the inside of the trench (130 of FIG. 8) and the etch stop layer pattern 120. ) To form a thick insulating material layer 140 by chemical vapor deposition (CVD) method. The insulating material layer 140 may be formed using an oxide. In this case, the oxide is also referred to as CVD oxide (Oxide).

FIG. 10 is a cross-sectional view illustrating a planarized and protruding insulating material layer pattern 140a formed in an isolation region of a substrate, which is a first process of planarizing the multi-display portion of FIG. 9 with respect to the resultant of FIG. The planarized insulating material layer pattern 140a protrudes from the exposed surface of the pad insulating layer pattern 115 by peeling the planarized etch stop layer pattern 120 stacked on the substrate 110 to the display portion of FIG. 9. The process proceeds to the second step of forming. In this case, the planarization of the first process may be performed by a chemical mechanical polishing (CMP) method, and the etch stop layer pattern 120 of the second process may be removed using a phosphoric acid solution.

FIG. 11 is a cross-sectional view illustrating implantation of impurities into the entire surface of the substrate on which the insulating material layer pattern 140a is formed as compared to the exposed substrate surface, which is the exposed pad insulating layer pattern of the resultant substrate of FIG. 10. A first etching method in which the insulating material layer pattern 140a is recessed compared to the exposed surface of the substrate using a material having a larger ratio of etching the protruding insulating material layer pattern 140a as an etchant compared to (115 of FIG. 10). Process and Result It proceeds to the 2nd process which forms the impurity layer 142 which has predetermined thickness on the board | substrate by ion implanting the impurity 141 to the whole surface of a board | substrate. In this case, the upper sidewall of the trench 130 is partially exposed by the recessed insulating material layer pattern 140a, so that the impurity layer 142 is formed deeper at the shoulder of the trench 130 by ion implantation. do. In this case, the etching of the first process using a wet etching method, wherein the etching selectivity of the exposed pad insulating film pattern (115 in FIG. 10) and the protruding insulating material layer 140a is 1:10. It is preferable to use the following etchant, and a representative example thereof may include BOE (Buffered Oxide Isolation) solution. On the other hand, the recessed insulating material layer 140a is preferably formed to a depth of about 500Å with respect to the exposed substrate 110.

FIG. 12 is a cross-sectional view illustrating that the impurity layer 142a remains only in the shoulder portion of the trench 130. The etching of the recessed insulating material layer pattern 140a is etched with respect to the resultant substrate on which the impurity layer of FIG. 11 is formed. The impurity layer is removed from the surface of the substrate 110 exposed by etching the resultant substrate by using an etchant having a small ratio, and the impurity layer 142a is formed only in the shoulder portion of the trench 130. The process of forming the insulating material layer pattern 140a to protrude from the surface of the substrate 110 is performed. In this case, the etching may be performed using a chemical dry etching method, and the insulating material layer pattern 140a may be formed to protrude about 500Å relative to the surface of the substrate 110.

FIG. 13 is a cross-sectional view showing that the device isolation region of FIG. 12 is planarized with respect to the completed substrate surface, which may be arbitrarily selected according to a subsequent desired process. In this case, reference numeral 140b indicates an insulating material layer pattern in which planarization is performed.

It is apparent that the present invention discussed above can solve the problems of the conventional method for separating semiconductor devices. That is, the parasitic junction capacitance caused by the formation of the impurity layer in the trench shoulder portion by the conventional method increases the junction leakage current, thereby degrading the refresh characteristics of the device and filling the trench. The following high temperature heat treatment process for densification can solve the problem of difficulty in controlling device characteristics by counter-doped impurity in the device active region with impurity counter-doped impurity and redistribution by thermal diffusion. have. As a result, an effective realization of device isolation can be achieved, resulting in a more reliable manufacture of semiconductor devices.

The present invention is not limited to the above-described embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (2)

A semiconductor device isolation method using a trench, comprising: a first step of sequentially stacking a pad insulating film and an etch stop layer on a front surface of a substrate; Patterning the etch stop layer and the pad insulating film to form an etch stop layer pattern and a pad insulating film pattern exposing an inactive region of the substrate; Forming a trench by etching the exposed substrate using the etch stop layer pattern as an etch mask; Forming an insulating film on the trench sidewalls and a bottom surface; A fifth step of forming an insulating material layer by depositing an insulating material on the entire surface of the resultant substrate so as to fill the inside of the trench; Etching the insulating material layer to expose the etch stop layer pattern; A sixth step of removing the etch stop layer pattern; Etching the insulating material layer so that the surface of the etched insulating material layer is lower than the surface of the substrate; An eighth step of forming an impurity layer by ion implanting impurities into the entire surface of the resultant substrate from which the insulating material layer is re-etched; And a ninth step of etching the substrate in the active region so that an impurity layer remains only in the shoulder portion of the trench. The method of claim 1, further comprising, after the first step, forming an oxide film on the pad insulating film and the etch stop layer, and forming an oxide pattern used to etch the etch stop layer and the pad insulating film by patterning the oxide film. Separation method of a semiconductor device using a trench, further comprising.