KR0184937B1 - Method of manufacturing semiconductor device transistor - Google Patents
Method of manufacturing semiconductor device transistor Download PDFInfo
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- KR0184937B1 KR0184937B1 KR1019950048752A KR19950048752A KR0184937B1 KR 0184937 B1 KR0184937 B1 KR 0184937B1 KR 1019950048752 A KR1019950048752 A KR 1019950048752A KR 19950048752 A KR19950048752 A KR 19950048752A KR 0184937 B1 KR0184937 B1 KR 0184937B1
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- Prior art keywords
- ion implantation
- silicon substrate
- oxide film
- photoresist
- photoresist film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims description 73
- 229920002120 photoresistant polymer Polymers 0.000 claims description 57
- 238000005468 ion implantation Methods 0.000 claims description 49
- 239000012535 impurity Substances 0.000 claims description 27
- 238000000059 patterning Methods 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract description 2
- 239000000243 solution Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
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- Ceramic Engineering (AREA)
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Abstract
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 게이트 전극의 폭을 최소화시키기 위해 접합 영역의 실리콘 기판에서 산화막의 성장 속도가 빠른 특성을 이용하여 상기 접합 영역의 실리콘 기판상에 두꺼운 열산화막을 형성한다. 그리고 상기 두꺼운 열산화막에 의해 게이트 전극의 폭이 사진 장비의 임계 치수 이하가 되도록 하므로써 소자의 집적도 및 전기적 특성이 향상될 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.The present invention relates to a transistor manufacturing method of a semiconductor device, in order to minimize the width of the gate electrode to form a thick thermal oxide film on the silicon substrate of the junction region using the characteristic of the rapid growth rate of the oxide film in the silicon substrate of the junction region. do. In addition, the present invention relates to a method of fabricating a transistor of a semiconductor device in which the thickness of the gate electrode is less than or equal to the critical dimension of the photographic equipment by the thick thermal oxide film so that the integration and electrical characteristics of the device can be improved.
Description
제1a 내지 제1c도는 종래 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a transistor manufacturing method of a conventional semiconductor device.
제2a 내지 제2e도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of elements for explaining the first embodiment of the present invention.
제3a 및 제3b도는 본 발명의 제2실시예를 설명하기 위한 소자의 단면도.3A and 3B are sectional views of elements for explaining the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 실리콘 기판 2,18,31 : 게이트 산화막1,11 silicon substrate 2,18,31 gate oxide film
3,19,32 : 도프 폴리실리콘층 4 : 감광막3,19,32: dope polysilicon layer 4: photosensitive film
5,15,33 : 게이트 전극 6,14 : LDD 영역5,15,33: gate electrode 6,14: LDD region
7 : 산화막 스페이서 8,16 : 접합 영역7 oxide film spacer 8,16 junction region
12 : 패드 산화막 13 : 제1감광막12 pad oxide film 13 first photosensitive film
15 : 제2감광막 17,17A : 열 산화막15: second photosensitive film 17,17A: thermal oxide film
29 : 제3감광막 30 : 채널 이온주입 영역29: third photosensitive film 30: channel ion implantation region
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 게이트 전극의 폭을 최소화시킬 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly to a method of manufacturing a transistor of a semiconductor device to minimize the width of the gate electrode.
일반적으로 반도체 소자가 고집적화됨에 따라 트랜지서트의 크기도 감소된다. 그러나 현재의 사진(Lithography) 공정으로는 패턴의 폭을 임계 치수(Critical Dimension) 이하로 감소시키기가 어려운 실정이기 때문에 새로운 방법의 개발이 요구된다. 그러면 종래 반도체 소자의 트랜지스터 제조 방법을 제1a 내지 제1c도를 통해 설명하면 다음과 같다.In general, as semiconductor devices are highly integrated, the size of the transistor is also reduced. However, the current lithography process is difficult to reduce the width of the pattern to less than the critical dimension (critical dimension), so the development of a new method is required. The transistor manufacturing method of the conventional semiconductor device will now be described with reference to FIGS. 1A to 1C.
종래에는 제1a도에 도시된 바와 같이 실리콘 기판(1)상에 게이트 산화막(2), 도프 폴리실리콘층(3) 및 감광막(4)을 순차적으로 형성한 후 게이트 전극용 마스크(Mask)를 이용하여 상기 감광막(4)을 패터닝한다. 상기 패터닝된 감광막(4)을 마스크로 이용한 식각 공정으로 상기 도프 폴리실리콘층(3) 및 게이트 산화막(2)을 순차적으로 패터닝하여 게이트 전극(5)을 형성한 후 잔류된 상기 감광막(4)을 제거하고, 제1b도에 도시된 바와 같이 전체 상부면에 저농도의 불순물 이온을 주입하여 상기 게이트 전극(5) 양측부의 실리콘 기판(1)에 LDD(Lightly Doped Drain) 영역(6)을 형성한다. 그리고 상기 게이트 전극(5)의 양측벽에 산화막 스페이서(7)를 형성한 후 전체 상부면에 고농도의 불순물 이온을 주입하여 상기 게이트 전극(5) 양측부의 실리콘 기판(1)에 접합 영역(8)을 형성한다. 그런데 상기 게이트 전극(5)의 폭은 상기 패터닝된 감광막(4)의 폭에 의해 결정되고, 상기 감광막(4)의 폭은 사전 장비의 임계 치수에 의해 결정되기 때문에 초고집적 반도체 소자의 제조 공정에서는 이와 같은 방법으로 트랜지스터를 제조하기가 어려워진다.Conventionally, as shown in FIG. 1A, a gate oxide film 2, a dope polysilicon layer 3, and a photoresist film 4 are sequentially formed on a silicon substrate 1, and then a mask for a gate electrode is used. The photosensitive film 4 is patterned. The dope polysilicon layer 3 and the gate oxide layer 2 are sequentially patterned in an etching process using the patterned photosensitive film 4 as a mask to form a gate electrode 5, and then the remaining photosensitive film 4 is used. As shown in FIG. 1B, lightly doped drain (LDD) regions 6 are formed in the silicon substrate 1 at both sides of the gate electrode 5 by implanting low concentrations of impurity ions into the entire upper surface. After forming oxide spacers 7 on both sidewalls of the gate electrode 5, a high concentration of impurity ions are implanted into the entire upper surface of the gate electrode 5 to bond regions 8 to silicon substrates 1 on both sides of the gate electrode 5. To form. However, the width of the gate electrode 5 is determined by the width of the patterned photosensitive film 4, and the width of the photosensitive film 4 is determined by the critical dimension of the pre-equipment. It becomes difficult to manufacture transistors in this way.
따라서 본 발명은 게이트 전극의 폭을 사진 장비의 임계 치수 이하가 되도록 함으로써 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a transistor of a semiconductor device that can solve the above disadvantages by making the width of the gate electrode less than or equal to the critical dimension of photographic equipment.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 실리콘 기판상에 패드 산화막 및 제1감광막을 순차적으로 형성하고, 제1마스크를 이용하여 상기 제1감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 제1감광막을 경화시킨 후 상기 패터닝된 제1감광막을 이온 주입 마스크로 이용한 저농도 불순물 이온 주입 공정으로 노출된 상기 실리콘 기판에 LDD 영역을 형성하는 단계와, 상기 단계로부터 전체 상부면에 제2감광막을 도포한 후 제2마스크를 이용하여 상기 제2감광막을 패터닝하고, 상기 패터닝된 제2감광막을 이온 주입 마스크로 이용한 고농도 불순물 이온 주입 공정으로 노출된 실리콘 기판에 접합 영역을 형성하는 단계와, 상기 단계로부터 상기 제2 및 제1감광막을 제거한 후 열산화 공정을 실시하여 상기 실리콘 기판상에 열산화막을 형성하는 단계와, 상기 단계로부터 상기 불순물 이온이 주입되지 않은 실리콘 기판상에 형성된 열산화막을 제거한 후 전체 상부면에 게이트 산화막 및 도프 폴리실리콘층을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 제1마스크를 이용한 사진 및 식각 공정으로 상기 도프 폴리실리콘층 및 게이트 산화막을 순차적으로 패터닝하여 게이트 전극을 형성하는 단계로 이루어지는 것을 특징으로 하며, 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 실리콘 기판상에 패드 산화막 및 제1감광막을 순차적으로 형성하고, 제1마스크를 이용하여 상기 제1감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 제1감광막을 경화시킨 후 상기 패터닝된 제1감광막을 이온 주입 마스크로 이용한 저농도 불순물 이온 주입 공정으로 노출된 상기 실리콘 기판에 LDD 영역을 형성하는 단계와, 상기 단계로부터 전체 상부면에 제2감광막을 도포한 후 제2마스크를 이용하여 상기 제2감광막을 패터닝하고, 상기 패터닝된 제2감광막을 이온 주입 마스크로 이용한 고농도 불순물 이온 주입 공정으로 노출된 실리콘 기판에 접합 영역을 형성하는 단계와, 상기 단계로부터 상기 제2 및 제1감광막을 제거한 후 열산화 공정을 실시하여 상기 실리콘 기판상에 열산화막을 형성하는 단계와, 상기 단계로부터 전체 상부면에 제3감광막을 도포하고, 상기 불순물 이온이 주입되지 않은 실리콘 기판상에 형성된 열산화막이 노출되도록 상기 제3감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 제3감광막을 이온 주입 마스크로 이용한 채널 이온주입 공정으로 상기 실리콘 기판에 채널 이온주입 영역을 형성하는 단계와, 상기 단계로부터 잔류된 상기 제3감광막 및 상기 불순물 이온이 주입되지 않은 실리콘 기판상에 형성된 열산화막을 제거한 후 전체 상부면에 게이트 산화막 및 도프 폴리실리콘층을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 제1마스크를 이용한 사진 및 식각 공정으로 상기 도프 폴리실리콘층 및 게이트 산화막을 순차적으로 패터닝하여 게이트 전극을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a transistor of a semiconductor device, the method including sequentially forming a pad oxide film and a first photoresist film on a silicon substrate, and patterning the first photoresist film using a first mask; Forming an LDD region on the silicon substrate exposed by a low concentration impurity ion implantation process using the patterned first photoresist layer as an ion implantation mask after curing the patterned first photoresist layer from the step; After coating the second photoresist film on the surface, patterning the second photoresist film using a second mask, and forming a junction region on the exposed silicon substrate by a high concentration impurity ion implantation process using the patterned second photoresist film as an ion implantation mask And removing the second and first photoresist films from the step, and performing a thermal oxidation process. Forming a thermal oxide film on the silicon substrate, and removing the thermal oxide film formed on the silicon substrate to which the impurity ions are not implanted, and sequentially forming a gate oxide film and a dope polysilicon layer on the entire upper surface thereof. And forming a gate electrode by sequentially patterning the dope polysilicon layer and the gate oxide layer by a photolithography and an etching process using the first mask from the above step, wherein the transistor of the semiconductor device according to the present invention is formed. The manufacturing method includes sequentially forming a pad oxide film and a first photoresist film on a silicon substrate, patterning the first photoresist film using a first mask, and curing the patterned first photoresist film from the step, followed by the patterning. Concentration impurities using the first photosensitive film as an ion implantation mask Forming an LDD region on the silicon substrate exposed by an on-injection process, applying a second photoresist film to the entire upper surface from the step, and then patterning the second photoresist film using a second mask, and forming the patterned material. Forming a junction region on the silicon substrate exposed by the high concentration impurity ion implantation process using the photoresist film as an ion implantation mask; and removing the second and first photoresist films from the step, and performing a thermal oxidation process on the silicon substrate. Forming a thermal oxide film on the substrate, applying a third photosensitive film to the entire upper surface from the step, and patterning the third photosensitive film to expose the thermal oxide film formed on the silicon substrate to which the impurity ions are not implanted; In the channel ion implantation process using the patterned third photosensitive film as an ion implantation mask from the step, the silicon group Forming a channel ion implantation region in the substrate; and removing the thermal oxide film formed on the silicon substrate to which the third photoresist film and the impurity ions are not remaining, and the gate oxide film and the dope polysilicon layer And forming a gate electrode by sequentially patterning the dope polysilicon layer and the gate oxide layer in a sequential manner and in a photo and etching process using the first mask.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 내지 제2e도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도로서, 제2a도는 실리콘 기판(11)상에 패드 산화막(12) 및 제1감광막(13)을 순차적으로 형성하고, 제1마스크(도시않됨)를 이용하여 상기 제1감광막(13)을 패터닝한 상태의 단면도로써, 이때 상기 패터닝된 제1감광막(13)의 폭(d)은 공정에 이용되는 사진 장비의 임계 치수와 동일하도록 한다. 또한 상기 패스 산화막(12)은 200 내지 300Å의 두께로 형성된다.2A to 2E are cross-sectional views of the device for explaining the first embodiment of the present invention. FIG. 2A is a view illustrating sequentially forming the pad oxide film 12 and the first photosensitive film 13 on the silicon substrate 11, A cross-sectional view of the first photoresist layer 13 patterned using a first mask (not shown), wherein the width d of the patterned first photoresist layer 13 is a critical dimension of the photographic equipment used in the process. To be the same as In addition, the pass oxide film 12 is formed to a thickness of 200 to 300 kPa.
제2b도는 110 내지 130℃의 온도에서 20 내지 40분동안 상기 패터닝된 제1감광막(13)을 경화시킨 후 상기 패터닝된 제1감광막(13)을 이온 주입 마스크로 이용한 저농도 불순물 이온 주입 공정으로 노출된 상기 실리콘 기판(11)에 LDD 영역(14)을 형성한 상태의 단면도로서, 이때 이온 주입량은 1×1012내지 1×1015원자/㎤이며, 이온 주입 에너지는 30 내지 80KeV가 되도록 한다.2b is a low concentration impurity ion implantation process using the patterned first photoresist layer 13 as an ion implantation mask after curing the patterned first photoresist layer 13 at a temperature of 110 to 130 ° C. for 20 to 40 minutes. A cross-sectional view of the state in which the LDD region 14 is formed on the silicon substrate 11, wherein the ion implantation amount is 1 × 10 12 to 1 × 10 15 atoms / cm 3, and the ion implantation energy is 30 to 80 KeV.
제2c도는 전체 상부면에 제2감광막(15)을 도포한 후 제2마스크(도시않됨)를 이용하여 상기 제2감광막(15)을 패터닝하고, 상기 패터닝된 제2감광막(15)을 이온 주입 마스크로 이용한 고농도 불순물 이온 주입 공정으로 노출된 실리콘 기판(11)에 접합 영역(16)을 형성한 상태의 단면도로서, 이때 상기 패터닝된 제2감광막(15)의 폭(d+a)은 상기 패터닝된 제1감광막(13)의 폭(d)보다 a만큼 크다. 또한 상기 이온 주입량은 1×1014내지 1×1017원자/㎤이며, 이온 주입 에너지는 30 내지 60KeV가 되도록 한다.In FIG. 2C, after applying the second photoresist film 15 to the entire upper surface, the second photoresist film 15 is patterned using a second mask (not shown), and the patterned second photoresist film 15 is ion implanted. A cross-sectional view of a state in which a junction region 16 is formed in a silicon substrate 11 exposed by a high concentration impurity ion implantation process used as a mask, wherein the width d + a of the patterned second photosensitive film 15 is the patterning. It is larger than a width d of the first photosensitive film 13 thus obtained. In addition, the ion implantation amount is 1 × 10 14 to 1 × 10 17 atoms / cm 3, and the ion implantation energy is 30 to 60 KeV.
제2d도는 상기 제2 및 제1감광막(15 및 13)을 제거한 후 열산화 공정을 실시하여 상기 실리콘 기판(11)상에 열산화막(17 및 17A)을 형성한 상태의 단면도로서, 이때 상기 불순물 이온이 주입된 접합 영역(16)의 실리콘 기판(11)상에는 1000 내지 3000Å 정도의 두꺼운 열산화막(17)이 성장되며, 상기 주입된 불순물 이온이 내부로 확산된다. 그리고 상기 불순물 이온이 주입되지 않은 실리콘 기판(11)상에는 얇은 열산화막(17A)이 성장된다. 또한 상기 제1 및 제2감광막(13 및 15)은 산소 플라즈마를 아용한 건식 식각 및 황산과 과산화수소수가 혼합된 용액을 이용한 습식 식각으로 제거한다.FIG. 2D is a cross-sectional view of thermal oxidation processes 17 and 17A formed on the silicon substrate 11 by performing a thermal oxidation process after removing the second and first photoresist films 15 and 13. On the silicon substrate 11 of the implanted region 16 into which ions are implanted, a thick thermal oxide film 17 of about 1000 to 3000 kPa is grown, and the implanted impurity ions diffuse into the inside. A thin thermal oxide film 17A is grown on the silicon substrate 11 to which the impurity ions are not implanted. In addition, the first and second photoresist layers 13 and 15 may be removed by dry etching using oxygen plasma and wet etching using a solution containing sulfuric acid and hydrogen peroxide.
제2e도는 HF 용액을 이용한 습식 식각 공정으로 상기 불순물 이온이 주입되지 않은 실리콘 기판(11)상에 형성된 얇은 열산화막(17A)을 제거한 후 전체 상부면에 100 내지 150Å 두께의 게이트 산화막(18) 및 1500 내지 3000Å 두께의 도프 폴리실리콘층(19)을 순차적으로 형성하고, 상기 제1마스크를 이용한 사진 및 식각 공정으로 상기 도프 폴리실리콘층(19) 및 게이트 산화막(18)을 순차적으로 패터닝하여 게이트 전극(15)을 형성한 상태의 단면도로서, 이때 형성된 상기 게이트 전극(15)의 폭(W)은 상기 접합 영역(16)의 실리콘 기판(11)상에 형성된 상기 열산화막(17)에 의해 상기 패터닝된 제1감광막(13)의 폭(d)보다 작게 형성된다.2e is a gate oxide film 18 having a thickness of 100 to 150 Å on the entire upper surface after removing the thin thermal oxide film 17A formed on the silicon substrate 11 to which the impurity ions are not implanted by a wet etching process using an HF solution. A dope polysilicon layer 19 having a thickness of 1500 to 3000 Å is sequentially formed, and the dope polysilicon layer 19 and the gate oxide layer 18 are sequentially patterned by a photolithography and an etching process using the first mask to form a gate electrode. A cross-sectional view of a state in which 15 is formed, wherein the width W of the gate electrode 15 formed at this time is patterned by the thermal oxide film 17 formed on the silicon substrate 11 of the junction region 16. It is formed smaller than the width d of the first photosensitive film 13.
제3a 및 제3b도는 본 발명의 제2실시예를 설명하기 위한 소자의 단면도로서, 본 발명의 제2실시예는 상기 제1실시예의 제2d도에 설명된 상기 열산화막(17 및 17A) 형성 공정을 마친 후 후속 공정을 다음과 같이 진행하므로써 얻을 수 있다.3A and 3B are cross-sectional views of elements for explaining the second embodiment of the present invention, wherein the second embodiment of the present invention forms the thermal oxide films 17 and 17A described in the second embodiment of the first embodiment. After finishing the process, the following process can be obtained by proceeding as follows.
제3a도는 상기 제1실시예의 제2d도에 설명된 상기 열산화막(17 및 17A)을 형성한 후 전체 상부면에 제3감광막(29)을 도포하고, 상기 불순물 이온이 주입되지 않은 실리콘 기판(11)상에 형성된 열산화막(17A)이 노출되도록 상기 제3감광막(29)을 패터닝한다. 그리고 상기 패터닝된 제3감광막(29)을 이온 주입 마스크로 이용한 채널 이온주입 공정으로 상기 실리콘 기판(11)에 채널 이온주입 영역(30)을 형성한 상태의 단면도로서, 이때 이온 주입량은 1×1011내지 1×1017원자/㎤이며, 이온 주입 에너지는 30 내지 70KeV가 되도록 한다.FIG. 3A shows a silicon substrate on which the third photosensitive film 29 is coated on the entire upper surface after forming the thermal oxide films 17 and 17A described in FIG. 2D of the first embodiment, and the impurity ions are not implanted. The third photosensitive film 29 is patterned to expose the thermal oxide film 17A formed on the substrate 11. A cross-sectional view of a channel ion implantation region 30 formed on the silicon substrate 11 by a channel ion implantation process using the patterned third photoresist layer 29 as an ion implantation mask, wherein the ion implantation amount is 1 × 10. 11 to 1 × 10 17 atoms / cm 3 and ion implantation energy of 30 to 70 KeV.
제3b도는 잔류된 상기 제3감광막(29) 및 상기 불순물 이온이 주입되지 않은 실리콘 기판(11)상에 형성된 열산화막(17A)을 제거한 후 전체 상부면에 100 내지 150Å 두께의 게이트 산화막(31) 및 1500 내지 3000Å 두께의 도프 폴리실리콘층(32)을 순차적으로 형성하고, 상기 제1마스크를 이용한 사진 및 식각 공정으로 상기 도프 폴리실리콘층(32) 및 게이트 산화막(31)을 순차적으로 패터닝하여 게이트 전극(33)을 형성한 상태의 단면도로서, 상기 열산화막(17A)은 HF 용액을 이용한 습식 식각 공정으로 제거하며, 이때 형성된 상기 게이트 전극(33)의 폭(W)은 상기 접합 영역(16)의 실리콘 기판(11)상에 형성된 상기 열산화막(17)에 의해 상기 패터닝된 제1감광막(13)의 폭(d)보다 작게 형성된다.FIG. 3B illustrates the removal of the thermally oxidized film 17A formed on the remaining third photosensitive film 29 and the silicon substrate 11 into which the impurity ions are not implanted, and then a gate oxide film 31 having a thickness of 100 to 150 Å on the entire upper surface thereof. And a dope polysilicon layer 32 having a thickness of 1500 to 3000 Å in sequence, and sequentially patterning the dope polysilicon layer 32 and the gate oxide layer 31 by a photolithography and etching process using the first mask. The thermal oxide film 17A is removed by a wet etching process using an HF solution, and the width W of the gate electrode 33 formed at this time is the junction region 16. The thermal oxide film 17 formed on the silicon substrate 11 is smaller than the width d of the patterned first photosensitive film 13.
상술한 바와 같이 본 발명에 의하면 접합 영역의 실리콘 기판에서 산화막의 성장 속도가 빠른 특성을 이용하여 상기 접합 영역의 실리콘 기판상에 두꺼운 열산화막을 형성한다. 그리고 상기 두꺼운 열산화막에 의해 게이트 전극의 폭이 사진 장비의 임계 치수 이하기 되도록 하므로써 소자의 집적도 및 전기적 특성이 향상될 수 있도록 하는 탁월한 효과가 있다.As described above, according to the present invention, a thick thermal oxide film is formed on the silicon substrate in the junction region by using the characteristic of the rapid growth rate of the oxide film in the silicon substrate in the junction region. In addition, the thickness of the gate electrode may be less than or equal to the critical dimension of the photographic equipment by the thick thermal oxide film, so that the integration and electrical characteristics of the device may be improved.
Claims (25)
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