KR0179832B1 - Ccd package manufacturing method - Google Patents
Ccd package manufacturing method Download PDFInfo
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- KR0179832B1 KR0179832B1 KR1019950022835A KR19950022835A KR0179832B1 KR 0179832 B1 KR0179832 B1 KR 0179832B1 KR 1019950022835 A KR1019950022835 A KR 1019950022835A KR 19950022835 A KR19950022835 A KR 19950022835A KR 0179832 B1 KR0179832 B1 KR 0179832B1
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- South Korea
- Prior art keywords
- package
- semiconductor chip
- leads
- solder
- stacked
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 239000011521 glass Substances 0.000 claims description 12
- 238000000465 moulding Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- VYQRBKCKQCRYEE-UHFFFAOYSA-N ctk1a7239 Chemical compound C12=CC=CC=C2N2CC=CC3=NC=CC1=C32 VYQRBKCKQCRYEE-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
본 발명은 적층형 시시디(CCD:CHARGE COUPLED DEVICE)패키지 및 그 제조방법에 관한 것으로, 일반적인 시시디 패키지는 응용분야의 다양화에 따라 요구되는 패키지의 박형화와 집적도 향상을 이루는데 한계가 있는 문제점이 있었던 바, 본 발명의 적층형 시시디 패키지는 와이어 본딩을 배제하고 솔더(14)를 이용하여 반도체 칩(11)의 본드 패드(도시되어 있지 않음)와 리드(15)를 연결하여 외부로의 전기적인 연결단자가 되도록 함으로써 패키지를 박형화 시키고, 접착부재(10)의 상,하에 제1 및 제2 반도체 칩(11)(11')을 적층형으로 부착하여 하나의 패키지로 사용할 수 있도록 함으로써 패키지의 집적도 향상에 기여하는 효과가 있는 것이다.The present invention relates to a stacked type CDC (CHADGE COUPLED DEVICE) package and a method of manufacturing the same. A general CD package has a problem in that the thickness and integration of a package required according to the diversification of applications are limited. As described above, the stacked CD package of the present invention excludes wire bonding and connects the bond pads (not shown) of the semiconductor chip 11 and the leads 15 using the solder 14 to be electrically connected to the outside. The package is made thinner by connecting terminals, and the first and second semiconductor chips 11 and 11 'are stacked and attached to the upper and lower adhesive members 10 so that the package can be used as a single package, thereby improving package integration. To contribute to.
Description
제1도는 일반적인 시시디 패키지의 구성을 보인 종단면도.1 is a vertical cross-sectional view showing the configuration of a typical cd package.
제2도는 본 발명 적층형 시시디 패키지의 구성을 보인 종단면도.Figure 2 is a longitudinal cross-sectional view showing the configuration of the stacked-type CD package of the present invention.
제3도는 본 발명 적층형 시시디 패키지의 제조공정을 설명하기 위한 도면으로,3 is a view for explaining a manufacturing process of the present invention, the stacked CD package,
(a)는 반도체 칩의 상면에 솔더와 피아이큐가 설치된 상태를 보인 종단면도.(a) is a longitudinal cross-sectional view which shows the state in which the solder and the PICQ were installed in the upper surface of the semiconductor chip.
(b)는 솔더에 리드를 부착하는 상태를 보인 종단면도.(b) is a longitudinal cross-sectional view which shows the state which attaches a lead to solder.
(c)는 반도체 칩의 상부에 글래스 리드를 설치하는 상태를 보인 종단면도.(c) is a longitudinal cross-sectional view which shows that the glass lead is provided in the upper part of a semiconductor chip.
(d)는 접착부재의 상,하부에 제1 및 제2 반도체 칩을 적층하는 상태를 보인 종단면도.(d) is a longitudinal sectional view which shows the state which laminated | stacked the 1st and 2nd semiconductor chip on the upper part and the lower part of an adhesive member.
(e)는 제1 및 제2 반도체 칩을 몰딩하는 상태를 보인 종단면도.(e) is a longitudinal cross-sectional view which shows the state which molded the 1st and 2nd semiconductor chip.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 접착부재 11,11' : 제1 및 제2 반도체 칩10: adhesive member 11,11 ': first and second semiconductor chip
11a,11a' : 수광 영역부 12,12' : 글래스 리드11a, 11a ': light receiving area portion 12, 12': glass lead
13,13' : 피아이큐(PIQ) 14,14' : 솔더13,13 ': PIQ 14,14': Solder
15,15' : 리드 16 : 몰딩부15,15 ': Lead 16: Molding part
17,17' : 절연 테이프17,17 ': Insulation Tape
본 발명은 적층형 시시디(CHARGE COUPLED DEVICE) 패키지에 관한 것으로, 특히 접착부재의 상,하부에 제1 및 제2 반도체 칩을 설치하여 패키지의 집적도 향상 및 경박 단소화에 기여하도록 한 적층형 시시디 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked COUPLED DEVICE package, and more particularly, to install first and second semiconductor chips on the upper and lower portions of the adhesive member, thereby contributing to the improvement of package density and the reduction of light weight and compactness. It is about.
일반적으로 디램 디바이스나 에스램 디바이스와 달리 글래스 리드를 통하여 반도체 칩의 수광 영역부로 수광되는 빛을 화상처리하는 디바이스로 시시디 패키지를 사용하는 바, 이러한 시시디 패키지는 이미지 센서, 감시용 카메라, 모니터, 캠코더 등의 상당히 많은 부분에 응용이 되고 있는 실정이다.In general, unlike a DRAM device or an SRAM device, a CD package is used as a device for processing light received through a glass lead to a light receiving area of a semiconductor chip. The CD package includes an image sensor, a surveillance camera, and a monitor. It is being applied to quite a lot of parts such as a camcorder.
제1도는 이와 같은 일반적인 시시디 패키지의 구성을 보인 종단면도로서, 이에 도시된 바와 같이, 일반적인 시시디 패키지는 수개의 리드(1)가 내설되어 있는 몸체(2)와, 상기 몸체(2)의 중앙에 형성되어 있는 캐비티(2A)에 접착제(3)로 부착되어 있는 반도체 칩(4)과, 그 반도체 칩(4)과 상기 리드(1)를 전기적으로 접속하는 와이어(5) 및 상기 반도체 칩(4)이 탑재되어 있는 몸체(2)의 상부를 실런트(6)로 부착하여 복개하는 글래스 리드(7)으로 구성되어 있다.FIG. 1 is a longitudinal cross-sectional view showing the configuration of such a general CD package. As shown in the drawing, a general CD package includes a body 2 having several leads 1 embedded therein, and The semiconductor chip 4 attached to the cavity 2A formed in the center with the adhesive agent 3, the wire 5 which electrically connects the semiconductor chip 4, and the said lead 1, and the said semiconductor chip It consists of the glass lid 7 which attaches and covers the upper part of the body 2 on which the 4 is mounted with the sealant 6, and covers it.
도면중 미설명 부호 4A는 수광 영역부이다.In the figure, reference numeral 4A denotes a light receiving area portion.
상기와 같이 구성되어 있는 종래의 일반적인 시시디 패키지는 패키지 몸체(2)에 형성되어 있는 캐비티(2A)에 반도체 칩(4)을 부착하는 단계와, 상기 반도체 칩(4)과 리드(1)를 와이어(5)로 연결하는 와이어 본딩 단계와, 상기 반도체 칩(4)이 부착되어 있는 캐비티(2a)의 상부를 글래스 리드(7)로 복개하는 단계의 순서로 제조되는 것이다.In the conventional general CD package having the above structure, the semiconductor chip 4 is attached to the cavity 2A formed in the package body 2, and the semiconductor chip 4 and the lid 1 are attached to each other. The wire bonding step of connecting the wires 5 and the upper part of the cavity 2a to which the semiconductor chip 4 is attached are covered with the glass lead 7.
그러나, 상기와 같은 일반적인 시시디 패키지는 와이어 본딩을 필수적으로 수행하여야 하므로 패키지의 박형화에 한계가 있으며, 또한, 패키지 적용분야의 발전에 따라 하나의 패키지로 다기능이 요구되어 패키지의 집적도 향상을 필요로 하는데, 이러한 집적도 향상에 한계가 있는 문제점이 있었다.However, the general CD package as described above has a limitation in thinning the package because wire bonding is essential. In addition, as the package application field is developed, multifunctionality is required as a single package, and thus the package density needs to be improved. However, there was a problem that there is a limit in improving the integration.
본 발명의 목적은 와이어 본딩을 배제하고 솔더를 이용하여 반도체 칩과 리드의 전기적인 연결을 함으로써 패키지를 박형화시킬 수 있는 적층형 반도체 패키지 및 그 제조방법을 제공함에 있다.Disclosure of Invention An object of the present invention is to provide a laminated semiconductor package and a method for manufacturing the same, which can thin a package by eliminating wire bonding and electrically connecting a semiconductor chip and a lead using solder.
본 발명의 다른 목적은 절연부재의 상,하부에 제1 및 제2 반도체 칩을 적층함으로써 패키지의 집적도 향상에 기여하는 적층형 반도체 패키지 및 그 제조방법을 제공함에 있다.Another object of the present invention is to provide a stacked semiconductor package and a method of manufacturing the same, which contribute to improving the integration degree of the package by stacking the first and second semiconductor chips on and under the insulating member.
상기와 같은 본 발명의 목적을 달성하기 위하여 절연부재의 상,하부에 부착되어 있는 제1/제2 반도체 칩과, 그 제1 및 제2 반도체 칩의 상,하부에 피아이큐로 부착되어 있는 상,하부 글래스 리드와, 상기 제1/제2 반도체 칩의 본드 패드에 솔더로 연결되어 외부로의 전기적인 연결단자가 되는 수개의 상,하부 리드와, 그 상,하부 리드 사이에 설치되는 상,하부 절연 테이프 및 상기 제1/제2 반도체 칩, 상,하부 리드의 일정부분을 감싸도록 몰딩한 몰딩부로 구성되는 적층형 시시디 패키지가 제공된다.In order to achieve the object of the present invention as described above, the first and second semiconductor chips attached to the upper and lower portions of the insulating member and the upper and lower images of the first and second semiconductor chips attached to the upper and lower portions of the first and second semiconductor chips. A lower glass lead and a plurality of upper and lower leads connected to solder pads of the first and second semiconductor chips to be electrically connected to the outside, and an upper and lower leads installed between the upper and lower leads. Provided is a stacked CD package including a lower insulating tape, a molding part molded to cover a portion of the first and second semiconductor chips, and upper and lower leads.
또한, 상기와 같은 본 발명의 제조방법에 있어서는 웨이퍼 상태의 반도체 칩에 형성되어 있는 본드 패드에 솔더를 형성하고, 그 반도체 칩의 수광 영역부 주변에 피아이큐로 코팅하는 단계와, 상기 웨이퍼 상태의 반도체 칩을 개개의 반도체 칩으로 분리한 후, 그 반도체 칩의 상부에 형성된 솔더에 리드를 연결하여 전기적인 접속을 실시하는 단계와, 상기 반도체 칩에 형성된 수광 영역부 상부에 글래스 리드를 부착 하고, 그와 같이 제작된 다른 반도체 칩을 절연부재의 상,하부에 부착하는 단계와, 이와 같이 부착된 제1 및 제2 반도체 칩과 리드를 포함하여 에폭시로 인캡슐레이션시키는 몰딩단계의 순서로 진행하는 적층형 시시디 패키지의 제조방법이 제공된다.In the manufacturing method of the present invention as described above, a solder is formed on a bond pad formed on a semiconductor chip in a wafer state, and coated with a PICQ around the light-receiving area portion of the semiconductor chip; Separating the semiconductor chip into individual semiconductor chips, and then connecting the leads to solder formed on the semiconductor chip to perform electrical connection, and attaching a glass lead to the upper portion of the light receiving region formed on the semiconductor chip, Attaching the other semiconductor chips thus manufactured to the upper and lower portions of the insulating member, and the molding step of encapsulating with epoxy including the attached first and second semiconductor chips and leads. A method of making a stacked CD package is provided.
이하, 상기와 같은 본 발명의 실시례를 첨부된 도면에 의거하여 보다 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention as described above will be described in detail with reference to the accompanying drawings.
제2도는 본 발명 적층형 시시디 패키지의 구성을 보인 종단면도이고, 제3도의 (a)(b)(c)(d)(e)는 본 발명 적층형 시시디 패키지의 제조공정을 설명하기 위한 종단면도이다.2 is a longitudinal cross-sectional view showing the configuration of the laminated CD package of the present invention, Figure 3 (a) (b) (c) (d) (e) is a longitudinal section for explaining the manufacturing process of the laminated CD package of the present invention It is also.
도시된 바와 같이, 본 발명의 적층형 시시디 패키지는 절연부재(10)의 상,하부에 수광 영역부(11a)(11a')가 형성되어 있는 제1 및 제2 반도체 칩(11)(11')이 부착되어 있고, 그 제1 및 제2 반도체 칩(11)(11')에 형성된 수광 영역부(11a)(11a')의 상,하부 글래스 리드(12)(12')가 피아이큐(13)(13')로 부착되어 있으며, 상기 제1 및 제2 반도체 칩(11)(11')의 본드 패드(도시되어 있지 않음)에 솔더(14)(14')로 각각의 상,하부 리드(15)(15')가 접착되어 있는 것이다. 그리고, 상기 제1 및 제2 반도체 칩(11)(11')과 리드(15)(15')를 에폭시로 인캡슐레이션시킨 몰딩부(16)로 구성되어 있는 것이다.As shown, the stacked CD package of the present invention includes first and second semiconductor chips 11 and 11 'having light receiving regions 11a and 11a' formed on upper and lower portions of the insulating member 10. ) And upper and lower glass leads 12 and 12 'of the light-receiving region portions 11a and 11a' formed on the first and second semiconductor chips 11 and 11 '. 13 and 13 ', each of the upper and lower solder pads 14 and 14' to the bond pads (not shown) of the first and second semiconductor chips 11 and 11 '. Leads 15 and 15 'are bonded to each other. The first and second semiconductor chips 11 and 11 'and the leads 15 and 15' are formed of a molding part 16 encapsulated with epoxy.
상기 상,하부 리드(15)(15')사이에는 각각의 리드(15)(15')를 지지하며 댐바의 역할을 하는 상,하부 절연 테이프(17)(17')가 설치되어 있다.Upper and lower insulating tapes 17 and 17 'are provided between the upper and lower leads 15 and 15' to support the leads 15 and 15 'and serve as a dam bar.
상기와 같이 구성되어 있는 본 발명의 시시디 패키지의 제조공정을 제3도를 참고로 하여 살펴보면 다음과 같다.Looking at the manufacturing process of the cd package of the present invention configured as described above with reference to Figure 3 as follows.
먼저, 웨이퍼 상태의 반도체 칩(11)에 형성되어 있는 본드 패드(도시되어 있지 않음)에 솔더(혹은 범프)(14)를 형성하고, 그 반도체 칩(11)의 수광 영역부(11a) 주변에 피아이큐(13)로 코팅하는 단계와, 상기 웨이퍼 상태의 반도체 칩(11)을 개개의 반도체 칩(11)으로 분리한 후, 그 반도체 칩(11)의 상부에 형성된 솔더(14)에 리드(15)를 연결하여 전기적인 접속을 실시하는 단계와, 상기 반도체 칩(11)에 형성된 수광 영역부(11a)상부에 글래스 리드(12)를 부착하고, 그와 같이 제작된 다른 반도체 칩(11')를 절연부재(10)의 상,하부에 부착하는 단계와, 이와 같이 부착된 제1 및 제2 반도체 칩(11)(11')과 리드(12)(12')를 포함하여 에폭시로 인캡슐레이션시키는 몰딩단계의 순서로 진행하는 것이다.First, a solder (or bump) 14 is formed on a bond pad (not shown) formed in the semiconductor chip 11 in a wafer state, and then around the light receiving region 11a of the semiconductor chip 11. Coating the PICQ 13, separating the semiconductor chip 11 in the wafer state into individual semiconductor chips 11, and then attaching a lead to the solder 14 formed on the semiconductor chip 11. 15 to connect electrical connections, and attach the glass lead 12 over the light-receiving region 11a formed in the semiconductor chip 11, and the other semiconductor chip 11 'manufactured as described above. ) Is attached to the upper and lower portions of the insulating member 10, and the first and second semiconductor chips 11, 11 ′ and the leads 12, 12 ′ attached as described above are phosphorus-doped with epoxy. It proceeds in the order of molding step to encapsulate.
상기 몰딩단계의 진행시는 글래스 리드(12)의 표면과 몰딩부(16)의 표면이 일치하도록 하는 것이 바람직하며, 이와 같이 몰딩단계가 끝난 후에는 각각의 리드(12)(12')를 분리하기 위하여 댐바 컷팅을 하는 트림공정을 진행하고, 기판에 실장을 하기 위한 솔더링을 실시함으로써 최종 패키지가 완성되는 것이다.During the molding step, it is preferable that the surface of the glass lead 12 and the surface of the molding part 16 coincide with each other. After the molding step is finished, the respective leads 12 and 12 'are separated. The final package is completed by proceeding a trimming process for dam bar cutting and soldering for mounting on a substrate.
상기 실시례에서는 패키지의 상부에 설치되는 제1 반도체 칩(11)을 먼저 제조하는 것을 설명하였으나, 그 순서는 패키지의 하부에 설치되는 제2 반도체 칩(11')을 먼저 제조하여도 무방하다.In the above embodiment, the manufacturing of the first semiconductor chip 11 installed on the upper portion of the package has been described first, but the order may be to manufacture the second semiconductor chip 11 'installed on the lower portion of the package first.
또한, 상기 반도체 칩(11)에 형성된 본드 패드(도시되어 있지 않음)에 솔더(14)를 형성하는 방법은 시브이디(CVD),피브이디(PVD),일랙트로플래팅(ELECTRO-PLATING)등의 방법이 사용될 수 있다.In addition, a method of forming the solder 14 on the bond pads (not shown) formed on the semiconductor chip 11 may include CD, PVD, and ELECTRO-PLATING. And the like can be used.
상기와 같은 적층형 시시디 패키지의 제조를 위하여 별도의 몰딩장비는 필요없고, 기존의 에폭시를 이용하여 트랜스퍼 몰딩방식으로 패키지를 제조하면 되는 것이다.In order to manufacture the stacked CD package, there is no need for a separate molding apparatus, and the package may be manufactured by a transfer molding method using an existing epoxy.
이상에서 상세히 설명한 바와 같이 본 발명의 적층형 시시디 패키지는 와이어 본딩을 배제하고 솔더를 이용하여 반도체 칩의 본드 패드와 리드를 연결하여 외부로의 전기적인 연결단자가 되도록 함으로써 패키지를 박형화 시키고, 접착부재의 상,하에 제1 및 제2 반도체 칩을 적층형으로 부착하여 하나의 패키지로 사용할 수 있도록 함으로써 패키지의 집적도 향상에 기여하는 효과가 있는 것이다.As described in detail above, the laminated CD package of the present invention excludes wire bonding and connects the bond pad and the lead of the semiconductor chip to the outside by connecting the pads and leads of the semiconductor chip, thereby making the package thinner, and the adhesive member. By attaching the first and the second semiconductor chip in a stacked type above and below, it can be used as a package, thereby contributing to the improvement of package density.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950022835A KR0179832B1 (en) | 1995-07-28 | 1995-07-28 | Ccd package manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950022835A KR0179832B1 (en) | 1995-07-28 | 1995-07-28 | Ccd package manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970008634A KR970008634A (en) | 1997-02-24 |
| KR0179832B1 true KR0179832B1 (en) | 1999-03-20 |
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ID=19422001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950022835A KR0179832B1 (en) | 1995-07-28 | 1995-07-28 | Ccd package manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0179832B1 (en) |
-
1995
- 1995-07-28 KR KR1019950022835A patent/KR0179832B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970008634A (en) | 1997-02-24 |
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