KR0174338B1 - Random access memory with a simple test arrangement - Google Patents

Abstract

Quick test input / output (I / O) random access memory (RAM) is disclosed. The RAM array can be divided into individual units. Each unit is further divided into subarray blocks. Each subarray or segment can be configured as one and include an extra word line, including one spare column. If the block is accessed, only half of the segments are accessed. Even if a segment is accessed, the extra column of that segment is not accessed. Data from the columns in the half accessed and data from the extra columns in the half not accessed are transferred to the local data lines [Local Data Lines (LDLs)], and again from the LDL to the Master Data Lines (MDLs). Is passed to]. Valid data from the accessed column lines and selected spare lines is provided to the second sense amplifiers on the MDL. The defective columns are replaced with spares after passing through second stage amplifiers. Complementary outputs from several second sense amplifiers are wire AND'ed to each other and EXOR'ed during the compression mode test. The wire ANDed second sense amplifiers are then enabled at the same time. After the compression mode test, if one of the complementary wire ANDed outputs is high and the other is low, the EXOR output will go high indicating that no error has been detected. Otherwise, the RAM failed at the self-test.

Description

Random access memory with simple test configuration

1 schematically illustrates a prior art redundancy scheme for wide I / O RAM.

FIG. 2A illustrates a floor plan of a wide I / O 256 Mb DRAM chip constructed in accordance with a preferred embodiment of the present invention. FIG.

FIG. 2b schematically illustrates a 16Mb unit of the 256Mb DRAM chip of FIG. 2a.

FIG. 2C schematically illustrates a segment of the 16 MB unit of FIG. 2B.

3 is a schematic cross-sectional view of a 16 Mb unit constructed in accordance with a preferred embodiment of the present invention.

4A is a schematic cross-sectional view of a transistor level showing a segment constructed in accordance with a preferred embodiment of the present invention.

4b is a timing diagram for FIG. 4a.

4c schematically illustrates a column connection between a sense amplifier and a second sense amplifier.

5A schematically illustrates a programmable fuse latch circuit.

5b schematically illustrates a programmable address selection circuit.

5c schematically illustrates a CRDN circuit.

Figure 6a is a schematic cross sectional view of a unit through an IOSW circuit.

6b schematically illustrates an IOSU circuit.

7 schematically illustrates a compression mode test configuration.

* Explanation of symbols for main parts of the drawings

122: array block 126: subarray block

128: word lines 130: segment

132 bit lines

134: spare column line

124: IO switch (IOSW)

136: local data line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor memories, and more particularly to tests of semiconductor memories.

There are many causes for memory cell defects and memory array defects, and there are various signatures that result. Although defects in a single separate cell can spread throughout the array, it often results in multiple cells at the same location around the cell. If a defect occurs in a large number of cells, this fault may be a word line fault (i.e. defective cells with the same word line address), a bit (or column) line fault (i.e. a fault with the same bit line address). Cells), or both. The causes of these many cell defects vary. In particular, bit line defects may be caused by open bit lines, shorted bit lines, lack of field oxide, excessive oxide, intercell leakage, or various other causes. Can occur. Thus, memory cells are extensively tested to identify defective cells.

It is very often possible to repair chips with defective cells. Once identified, the defective cells can be replaced by electrical means if the spare cells of the array are included. Providing on-chip spare cells to repair cell defects is known in the art as on-chip redundancy. State-of-the-art redundancy configurations typically have one or more redundant rows (low redundancy) and / or one or more redundant columns (column redundancy). These redundant rows / columns have fuse programmable decoders that can be programmed to respond to the address of the defective row / column while at the same time preventing the selection of the defective cell. Electrically, a repaired chip is indistinguishable from a chip that is completely flawless.

Testing memory chips to identify defective cells is complex and requires special test patterns designed to identify each kind of defect. Because each of several test patterns must be written to and read from the array at least once. Testing memory chips can be time consuming. For example, on a 16Mb RAM chip with one data input / data output (DI / DO) and 70ns access time, testing a test pattern over 16 million cells can take several seconds. . Because testing requires many different and different test patterns, testing across an array can take several minutes. If there are hundreds of chips on one semiconductor wafer, it can take several hours to inspect one wafer. Moreover, this testing is performed at least once for each step between the initial wafer screen and the final shipment of wafer functionality.

In addition, as the chip density increases, for example, to 64 Mb or 256 Mb, the test time also increases. For each chip generation, the density increases four times. Typically, a four-fold increase results in a four-fold increase in addressable location. However, the performance improvement of each generation is usually less than twice. Thus, the test time is longer in each generation, and therefore more problematic.

For a variety of reasons, including reduced array test time, these ultra dense RAMs are configured to have 2 bits (X32) or wider data paths of 32 bits (x32) or wider. . Having such a wide input / output (I / O) organization significantly reduces array test time as more cells are accessed during each cycle. Accessing a larger number of cells per cycle results in fewer read / write cycles for each test pattern. For example, one test pattern on a 64Mb chip of 1 would require more than 64 million write cycles to load into the array, and then 6400 to verify that the array contains the stored test pattern. Ten thousand read cycles are required. On the other hand, in a wide I / O configuration of 512k × 128b, since one read / write cycle is for each 128 bit, only 512000 write cycles and 512000 read cycles are needed. Thus, wide I / O configurations require only a fraction of the number of test cycles, which can significantly reduce test time.

In addition to the reduced test time, it also provides the motivation for modern system requirements to have wide I / O configurations. State-of-the-art microprocessors typically employ 32-bit or 64-bit data words. Computers configured to fit into either of these microprocessors typically require 4-8 MB (MBytes) of DRAM. In such a system, 8MB of memory consisting of 2M × 32 can be made quite simple from four 16Mb (2M × 8) chips. For example, a 2M × 32 Single In-line Memory Module (SIMM) will use four chips of 2M × 8 in parallel. However, a 64Mb chip consisting of 8M × 8 cannot be simply reconfigured. Rather, the X32 SIMM configuration from 8Mx8 requires additional complex logic, with significant loss in performance. However, the external I / O configuration, whether comprised of 2M × 32, 1M × 64 or 512k × 128, provides an optimal 64Mb chip for use in systems based on typical microprocessors of the state of the art. In fact, the 512k × 128 configuration allows access to four 32-bit words simultaneously. New chip word architectures, such as Very Long Instruction Words (VLIWs) with wide data paths of 256 bits or more, are emerging as chip densities increase to 256 Mb and beyond.

Another reason for having a highly integrated chip-dry wide I / O DRAM configuration is the requirement for the performance of DRAMs used with high performance microprocessors. Typical prior art DRAMs cannot meet this requirement for performance. Prefetch is known as one of the state-of-the-art methods for increasing the throughput of synchronous DRAM (SDRAM). An SDRAM with a prefetch structure has a wider on-chip data path than on-chip I / O, for example 64-bit on-chip data paths versus 32-bit off-chip I / Os. chip data path). Off-chip transfer consists of two 32-bit transfers in sequence, while all array (on-chip) operations occur simultaneously (ie, 64-bit array read and write), and off chip transfer ) Consists of two 32-bit transfers sequentially. Therefore, RAM with wide I / O is needed because RAM with wide I / O reduces test time, simplifies memory system design and improves RAM performance.

Unfortunately, the prior art redundancy technology is insufficient for wide I / O RAM. There have been several prior art attempts to provide column redundancy in RAM chips. In one prior art approach the extra columns are isolated in a small (extra) array. If the column address points to a defective column, one of the pre-programmed spare columns is selected instead from the spare array. See, for example, US Pat. No. 4,727,516, entitled Semiconductor Memory Device Having Redundancy Means, issued by Yoshida et al., Which is incorporated herein by reference. But Yoshida's attempt is slow and requires a significant amount of additional logic. Additional logic is needed to determine whether the column address points to a defective column and, if so, to bypass the defective column and select a preprogrammed spare column. Redundancy detect logic determines whether the column address points to a defective column and if so, delays the cell access time to select the correct spare column instead. Need to be added. This redundancy approach has been acceptable for narrow I / O chips (8 I / O), but is too slow, flexible, and inadequate for use in wide I / O structures.

Another method of redundancy is used when a RAM array is hierarchically organized into groups of smaller subarrays, such as in highly integrated arrays, for example when the array is divided into four. In this second prior art redundancy method, extra columns are included with each subarray and used for that subarray. Each time a defective column is addressed, as in the first method, an extra column line in the subarray is selected instead of replacing it with data from a separate subarray.

FIG. 1 is a schematic illustration of a second prior art redundancy scheme for a wide I / O 16Mb DRAM chip. Chip 100 is composed of two extra bit lines (RBL) 102, 104 which provide two extra columns in each subarray 106. Each subarray 106 contains 2 ⁿ bit lines [(BL, 108), where n is 5 to 8 and redundant bit lines (two in this example). Each subarray 106 is part of a subarray block 110. All subarray blocks 110 come together to form the entire RAM array. Thus, for example, a 16Mb RAM has 16 blocks 110 that are each 1Mb. The block size, subarray size, and number of subarrays 106 are dependent on each other and are selected according to performance and logic purposes.

This second prior art redundancy method is not as slow as the first method but is not as flexible as the first method. In the first prior art method, any defective column can be replaced by any spare column in the block of spare columns. In the second prior art method, defective columns can only be replaced by spare columns in the same subarray. Therefore, for each chip, there must be at least one extra column for each subarray. This second approach allows the replacement of two or more defective columns in different subarrays, but guarantees that two defective columns per chip can be repaired even if there are two extra columns per subarray 106. It is only. If there are three defective columns in the same subarray 106, they cannot be repaired.

Moreover, this second method is inflexible and does not control the time delay caused by redundancy. The subarray 106 is accessed when one word line 112 is selected and goes high. Data from the accessed cells is provided simultaneously to the bit lines 108 and the redundant bit lines 102. 104. One bit line 108 or extra bit lines 102 and 104 after each predetermined minimum delay is sufficient for the redundancy decoder to determine whether the extra column is addressed, each subarray 106. Is selected. The selected bit lines 108 or redundant bit lines 102 and 104 in each subarray are coupled to a local data line (Local Data Line (LDL), 114). LDL 114 is coupled to Master Data Lines (MDL) 116. MDL 116 couples the corresponding subarrays 106 in each subarray block 110. Data is transferred between the subarray 106 and the chip I / Os on the MDL 116.

In normal cases, the bit select logic is faster than the redundancy decode logic. However, even though both circuits are equally fast, this second method requires delayed bit line selection to avoid timing conflicts, known as race conditions. When race conditions occur, the redundant bit lines 102 or 104 and the defective bit lines are both simultaneously connected to the LDL and shorted together for a short time. Problems arising from race conditions can range from slowing down data (i.e. detecting whether it is stored as 1 or 0) to incorrectly switching the data stored in the array or causing incorrect data to be read or written. To avoid race conditions, there must be a slight delay in chip timing before bit line selection. The delay is significantly smaller than required when using the first prior art method, but due to this slight delay it is still necessary to deliberately slow the chip access time to include redundancy. Slow chip access is an obstacle to improving performance for most RAM.

In addition to being inflexible and slowing chip access, this second prior art redundancy method is inefficient. In the 16 Mb chip of the above example, there are two redundant bit lines 102 and 104 for each of the ₂₅ = 32 bit lines 108. At least 6.25% of the array area is provided for redundant cells (this ratio is higher if low redundancy is included). However, if there are three defective columns in the same subarray 106, even if the spare columns 102 and 104 remain unused in each other subarray 106, they cannot be repaired. Thus, if there are three defective columns in the same subarray, the usable chip becomes unrepairable and unusable. Prior art redundancy schemes for wide I / O array chips are somewhat extensions of the prior art schemes. Prior art redundancy schemes, which had limited advantages over narrow I / O RAM, are insufficient for use in wide I / O RAM or prefetch type SDRAM. As can be seen from the above description, wide I / O chip configurations are further needed in ultra high density RAM. Thus, there is a need for a wide I / O RAM structure with flexible redundancy and improved test performance.

An object of the present invention is to reduce the test time of a semiconductor memory.

Another object of the present invention is to simplify semiconductor memory testing.

Yet another object of the present invention is to reduce the time required to identify defective semiconductor memory chips.

It is another object of the present invention to simplify initial semiconductor memory chip test screening.

The present invention relates to a structure of a wide I / O random access memory (RAM) and a self-test circuit thereof. If the RAM is large, it is divided into several units. For each unit or small amount of RAM, the memory is further divided into several blocks. Blocks are further divided into memory segments. Each segment consists of rows and columns. The selection of rows and columns is made in response to the memory address and is common for all segments in the block. Data from each column is sensed by first amplifying by a second sense amplifier in the unit, secondly in the sense amplifier of the column. The second sense amplifier provides a means for self-testing several columns at the same time. In a preferred embodiment the second sense amplifier has a complementary open collector output. The second sense amplifier outputs are ANDed together and the complementary result is EXOR. The EXOR output will provide a self-test result of pass / fail.

2A illustrates a layout design of a wide I / O 256 Mb DRAM chip 120 that may be tested in accordance with a preferred embodiment of the present invention. This 256 Mb array is divided into 16 identical 16 Mb units or array blocks 122.

2B is a diagram schematically showing one 16Mb unit 122. As in the prior art 16Mb RAM chip of FIG. 1, each 16Mb unit 122 is divided into a plurality of blocks 126. As shown in FIG. The plurality of word lines 128 lie horizontally through each subarray block 126. Each block 126 is further divided into a plurality of subarrays or segments 130. 2C is a diagram schematically illustrating the segment 130. Each segment 130 includes 2 ⁿ bit lines 132 and one redundant column line 134. The terms column and bit line are used interchangeably with one another in the present specification and in the related art, and refer to a plurality of subarray cells having a common bit address according to the common meaning used in the related art. It should be noted that in this embodiment the bit line actually refers to four complementary pairs of lines. For each complementary line pair, half of the cells are connected to one line and the other half to the other line.

In this embodiment, there are two segments 130 for every four units DI / DO, so that there are a total of sixteen segments 130 for each block 126. Only half (8) of segments 130 are accessed during block access. Data from the accessed segment 130 is passed to the I / O switch (IOSW) 124. IOSW 124 redrives the data and passes four bits from each accessed segment 130 to the I / O bus. Thus, a 256Mb DRAM with 16 32-bit units 122 in Figure 2a can be configured for 512k x 512 for testing and can be configured in the same manner for normal operation if desired.

Continuing with the description of FIG. 2C, the bit lines 132 and the extra column 134 in each segment 130 are local data lines (LDL) 136, which are also complementary line pairs. The LDL 136 from each subarray block 126 is coupled to an MDL 138, which is also a complementary line pair, and the MDL in each unit 122 is associated with the corresponding IOSW ( 124. In the redundancy configuration of the preferred embodiment, each block 126 is further divided into a right axis half 140 and a left half 142. As can be seen from the above description, half of the segments of the block during array access, i.e. Only right-half half 140 or left half 142 is accessed, half of the blocks with accessed segments are half accessed, and the remaining (unaccessed) half of blocks is designated as an extra half. Are the other half blocks 140 and 142, respectively. Refers to extra columns 134 in one half block 140, 142 that can be used to replace defective bit lines in a segment 130. Thus, as in the second prior art method, a 1: 1 extra All eight extra bit lines 134 (from the extra half block) as well as one spare bit line 134 that do not have a large segment correspondence, that can be used to replace a defective bit line in segment 130. Optionally, each unit 122 may include a redundant word line block 45 to replace defective word lines.

FIG. 3 is an example of a unit constructed in accordance with a preferred embodiment of the present invention, and is shown at approximately the same level of detail as the prior art 16M chip of FIG. In the example of FIG. 3, the bit lines 132 of each segment 130 in the accessed right-half half 140 are accessed, and at the same time the extra bit lines of the segment 130 in the spare left half 142 ( 134 is accessed. Data is transferred to the LDL 136 from the bit lines 132 (including the defective bit line 146) in the accessed half 140 and the redundant bit lines 134 in the redundant half 142. . Data on LD 136 is passed to corresponding MDL 138. IOSW circuit 124 selectively transfers data from MDL 138 to I / O lines 148, 150, 152, and 156. Only valid data from each accessed half 140 is passed to I / O line 148. At the same time IOSW 124 blocks error data from defective bit line 146 and instead replaces valid data from pre-programmed redundant column 154 in redundant (left) half 142 with I / O lines. Forward to 152. IOSW 124 also prevents data from being passed to the remaining I / O lines 156.

In the example of FIG. 3, one defective bit line 146 in the accessed half 140 is electrically replaced by an extra bit line 134 from the extra half block 142. However, each of the eight defective bit lines can be repaired within either half block 140, 142. Thus, it is possible to replace several defective columns with one redundant bit line 134 per segment 130 instead of several defective columns with a common bit address. It may also replace several defective columns in the same segment 130.

Bit, LDL 136 and MDL 138 selections can be better understood through a schematic cross-sectional view of the transistor level of the array block of FIG. 3 as provided in FIG. As can be seen from the above description, in the preferred embodiment of the present invention, each bit line 132 is actually represented by one line pair in FIG. 4A, but in practice there are four complementary pairs of line pairs. Cells 162 and 164 connected to adjacent word lines 127 and 128 are connected to opposite lines 166 and 168 of each pair. Thus, half 128 of the word line (eg, word lines with even addresses) selects cells 162 on one 166 of the bit line pair. On the other hand, the other half 127 of the word line selects the cells 164 on the remaining line 168 of the bit line pair (word lines with odd addresses). 1 is stored in the array such that the array sets the sense amplifier to the selected 1 condition. Thus, if 1 is defined as having 166 high and 168 low, charging 1 of the cell's storage capacitor 178 will cause the 1 to be stored in cell 162 (and 168). Stored in all remaining cells connected to the. Conversely, by completely discharging the storage capacitor 192 of the cell, 1 is stored in cell 164 (and in all remaining cells connected to reference 168).

The operation of the circuit of FIG. 4A follows the timing diagram of FIG. 4B. Prior to selecting cell 162 or 164, the array is in a steady-state standby condition. The voltages of the bit line pairs 166 and 168 are equalized to V _dd / 2 and the gate 170 of the equalization transistor 172 remains high. Word lines WL, 127 and 128 and column select (CSL) lines 174 remain low during the wait. When the word line 128 or 127 is driven high, the cell transistor 176 in each cell 162 on the word line 128 is turned on, bringing the storage capacitor 178 of the corresponding cell into a line of complementary pairs. Couple to (166). The voltage on line 166 rises slightly if charge is stored in storage capacitor 178 and drops slightly if charge is not stored (ie, capacitor is discharged). The second line 168 of the complementary pair remains precharged to V _dd / 2 and serves as a reference voltage of the sense amplifier 180. The sense amplifier 180 is set after a delay sufficient to sense 1 or 0 on line 166. The sense amplifier is set by bringing the sense amplifier enable (SAE) line 182 high and driving its inverse 184 low. After setting up the sense amplifiers, the data passed to the bit line pairs 166 and 168 is amplified and reconstructed on the bit line pairs 166 and 168 by bringing them high / low or low / high according to the data stored in the cell 162. Driven. Once all of the bit lines 166 and 168 are re-driven by the sense amplifier, the segment select signal (SEGi) is raised to select one column in each accessed segment 130. Drive) high. When the CSL 174 goes high, the selected restart bit line pairs 166, 168 are connected to the LDLs 188, 190 through pass gates 194, 196. The CSl timing is nearly identical to SEGi but slightly delayed.

At the same time as driving the CSL in the redundant half 142, if a defective column is addressed, the Spare Column Select Enable (SCSLEj) signal is raised to spare Column Select Enable (SCSL). The signal is driven high [reference 174 in the extra column], and data from the redundant column 134 is passed to the LDL pair 188, 190 via pass gates 194, 196. When the SCSL goes high, it drives the Column Select Disable (CSLD) signal high, which alternately pulls the simultaneously driven CSL 174 low to isolate the defective columns from the LDL 134. SCSL timing is nearly identical to SCSLEj but slightly delayed therefrom.

Finally, in FIG. 4C, the LDL pairs 188 and 190 are connected to the master data line by the master data select line (MSL) 208 through the pass gates 202 and 204. 198, 200. The data on the MDL pairs 198, 200 are sensed again and re-driven through the second sense amplifier 206. As will be described later, each of the second sense amplifiers 206 is described. The output is optionally coupled to a Global Data Line (GDL) 210 coupled to chip I / O.

Programming the redundant column decoder can be better understood with reference to FIG. 5A, which schematically illustrates a programmable fuse latch 210. This programmable fuse latch 210 includes a fuse 212 connected between ground and the drain of a P-type FET (PFET) 214. This fuse provides a low resistance for clamping the input of the inverter 216 low. When the input is clamped low, inverter 216 transfers high to inverters 218 and 220. Inverters 216 and 218 form a latch. Inverter 220 inverts the level from inverter 216 again. Outputs from the programmable fuse latch are from inverters 216 and 220. Initializing the latch by removing the fuse (primarily by laser programming) and supplying a pulse to the gate 222 of the PFET 214 causes the output of the inverter 220 to go high and the inverter 216 to go low. Each segment has one programmable fuse latch to enable redundant column lines and three programmable fuse latches to identify the segment that has a defective column line that the enabled spare column line will replace. . The redundant column line enable level (FMAC) is the reinverted output of the inverter 220. Three segment identification latches provide both true and complement outputs from inverters 220 and 216 labeled FSm and FSm, respectively, where m = 0, 1 or 2 The use of the output will be described below in more detail below.

The programmable address selection circuit of FIG. 5B includes the programmable fuse latch 210 of FIG. 5A. The state of the fuse 212 selects the state of the 2: 1 multiplexer (mux) formed by pairs of complementary transistors (222, 224 and 226, 228). In the state where the fuse 212 is present, the latch output 230 is high and the output of the buffer 220 is low. Complementary pairs 222 and 224 are on, and complementary pairs 226 and 228 are off. The 2: 1 multiplexer passes ADD (an inverted address signal) to its outputs 232 and An and a block bADD (Completion of ADD). On the contrary, when the fuse 212 is removed, the latch output 230 Low and the buffer output 220 is high, the complementary pairs 226, 228 are on and the complementary pairs 222, 224 are off, in this state the multiplexer passes bADD to its output 232 and adds ADD. To prevent.

5c schematically illustrates a CRDN circuit according to a preferred embodiment of the present invention. NAND gates 240, 242, and 244 coupled with NOR gate 246 decode the fuse programmed address by logically ANDing the programmable address select output Ao-An (n = 9) with the programmable latch output FMAC. The FMAC, which is the output of the programmable fuse latch 210, is high when the fuse 212 is blown to enable the CRDN. The decoder output of the NOR gate 246 is a Segment Column Select Enable (SCSLj) signal for segment j (j is between 0 and 7). SCSLEj goes high only when FMAC is high, that is, when CRDN is enabled, and Ao-An goes high when the programmed address is accessed. Ao-An goes high depending on the state and column address of the fuse 212 in each programmable address selection circuit. Thus, the extra column selection is programmed by removing the fuse (breaking) to bring FMAC high and to provide Ao-An as high once the defective column is addressed. SCSLEj goes high when a programmed address (in the defective column) is accessed. Each segment has a CRDN circuit. Thus, access to redundant columns is faster than prior art methods and array bit line accesses occur concurrently with redundant column accesses.

Thus, if SCSLE goes high, an extra column is enabled to replace one defective column in the accessed half 140. The segment containing the defective column to be replaced is identified by FSEG ₁ . FSEG ₁ is the output of NOR gate 254. Input 256 to NOR gate 254 (representing eight NOR gates) is FS _m or FS _m . NOR. Gate 254 causes three inputs to be 1/8 decoded, resulting in one FSEG _0-7 being high. High FSEG _0-7 indicates that you have fuse programmed extra columns to replace each defective column in segments 0-7. NAND gates 248, 250 and 252 represent eight NAND gates (one for each accessed segment). When SCSLE goes high, extra columns are accessed. One bfCHIT ₁ go down indicates that there is a HIT on a fuse column for segment ₁ is identified FSEG (match).

6A is a schematic cross-sectional view of the unit 122 through the IOSW circuit 124. Logic for replacing defective column 136 with redundant column 134. In the cross-sectional view of FIG. 6A a decode logic is included for both the redundant half 256 and the accessed half 262. The CRDN circuit of FIG. 5C is represented by logic block 262. By addressing the extra column selected as a fuse to bring bfCHIT _0-7 in the extra half 256 low, the I / O DISable (IODIS1) signal is generated by the NAND gate 264. Driven high. IODIS ₁ is the segment output from the segment containing the selected spare column and input to the IOSW logic 266 for the defective column segment. When IODIS ₁ goes high, the output of the second sense amplifier 270 in the defective accessed segment is disabled by bringing the IOSW ₁ signal, ie, the output of the NOR gate 268 low. When IOSW ₁ is enabled, the content of second sense amplifier 270 is selectively connected to I / O complementary pairs 272 and 274. IOSW ₁ is also controlled via the NOR gate 276 by timing signal IOSET and by SEG1 and SCSELEj.

Data on MDL 138 is provided to complementary pair 194 to second sense amplifier 270 as described above. Once the second sense amplifier 270 is set up, the second sense amplifier sends the driven data back to the complementary pairs 280 and 282 to turn on one of the FETs 284 and 286. I / O complementary pairs 272 and 274 are previously charged high. Highing IOSW ₁ turns on FETs 288 and 290 to couple FETs 284 and 286 to complementary lines 272 and 274, respectively. One of lines 272 or 274 is pulled low through 284.288 or 286 and 290, respectively, depending on the state of the second sense amplifier. The data transferred from the array to the I / O line pairs 272 and 274 leaves the chip.

As shown in FIG. 7, in a RAM chip constructed in accordance with a preferred embodiment of the present invention, each unit 122 has eight second sense amplifiers 270 outputs (0-7) from an extra half. have. The output of each extra half of the second sense amplifier 270 is dotted, dot AND'ed, and exits to the output of the sense amplifier 270 on the side accessed from the io complementary pairs 272 and 274. A pulse is applied to the gates of the PFETs 292 and 294 to pull the IO complementary pairs 272 and 274 high. This configuration allows for quick and simple testing. This test, then referred to as a data compression mode test, provides a convenient initial screen for determining whether all cells in a segment are operating properly. Data compression mode testing first begins by filling the array with a predetermined pattern, for example all 1s or all 0s. It then passes through word and column addresses to access each cell being tested. At each address all IOSWs are set high to couple the outputs of all second sense amplifiers 270 together to I / O lines 272 and 274. If one line remains high and the other line goes low in each I / O pair 272 and 274, no error is detected. However, if both lines go low, at least one defective cell has been detected. In addition, the EXOR (Exclusive OR) gate 296, which accepts I / O lines 272 and 274, provides sufficient Go and No Go test logic. If there is 1 in the EXOR output, it is Go. If there is 0, it is No Go. Data compression mode testing does not detect all defective cells, but significantly accelerates RAM testing. Thus, the RAM configuration of the present invention is significantly easier to test than the prior art configuration.

While the invention has been described in terms of preferred embodiments, it will be understood by those skilled in the art that various changes and modifications can be made therein without departing from the scope of the invention as set forth below. The claims are intended to cover modifications and variations that fall within the scope of the invention.

Claims (18)

A plurality of memory segments each comprising a plurality of memory cells arranged in rows and columns, the at least two of the segments in accordance with a row address; Column selection means for selecting each column from each of said columns in each said segment according to a row address and column address for simultaneously selecting each row of memory cells random access memory (RAM) comprising means for testing a plurality of cells simultaneously in a plurality of rows. 2. The apparatus of claim 1, wherein the means for testing the plurality of cells simultaneously comprises a plurality of second sense amplifiers each having a dottable output, wherein each of the dot outputs comprises: And coupled to an output of at least another one of said dotable outputs. 3. The apparatus of claim 2, wherein two or more dottable outputs within the means for simultaneously testing the plurality of cells are dotted together to form a global data line, each of And an active precharge load connected to the global data line. 2. The random access of claim 1, wherein each column is one or more complementary pairs of lines and one memory cell in each row is connected to each complementary line pair. Memory. 5. The random access memory of claim 4 wherein the one or more complementary line pairs are four pairs. 5. The method of claim 4 wherein half of said memory cells in each said row are connected to one line of said complementary line pair and the other half to another line of said complementary line pair. Random access memory. 4. The random access memory of claim 3 wherein the memory array further comprises a plurality of subarray blocks each comprising a plurality of memory segments. 8. The method of claim 7, wherein the row selection means selects one subarray block of the plurality of subarray blocks and one row in the selected subarray block, wherein the selected row is all the memory segments of the selected subarray block. Random access memory, characterized in that common to. 10. The random access memory of claim 8, further comprising a plurality of array blocks each including at least two subarray blocks of the plurality of subarray blocks. A plurality of array units, each comprising a plurality of subarray blocks, each of the plurality of subarray blocks comprising a plurality of segments, each of the plurality of segments being two-dimensional A plurality of array units comprising a two-dimensional addressable array of rows and columns and comprising at least one spare column: at a row address. Row selection means for selecting each of said rows in response: column selection means for selecting each column of every segment in a subarray block: and a plurality of in said plurality of units Random Access Memory (RAM), comprising means for testing cells simultaneously. 11. The apparatus of claim 10, wherein the means for testing the plurality of cells simultaneously comprises a plurality of second sense amplifiers each having a dottable output and each of the dotable outputs. Is coupled to an output of at least one of the dotnable outputs. 12. The apparatus of claim 10, wherein two or more dottable outputs within the means for testing the plurality of cells simultaneously are dotted together to form a global data line, each of the above And a random precharge load coupled to the global data line. 11. The method of claim 10, wherein each said column is one or more complementary pairs of lines, and one memory cell in each said row is connected to each complementary line pair. Random access memory. 14. The random access memory of claim 13 wherein the one or more complementary line pairs are four pairs. 11. The method of claim 10, wherein half of the memory cells in each row are connected to one line of the complementary line pair, and the other half is connected to the other line of the complementary line pair. Random access memory. 13. The system of claim 12, wherein the global data line is a complementary line pair, and further includes an exclusive OR that receives the global data complementary line pair and provides a pass / no / go signal. Random access memory comprising a. A plurality of memory segments arranged in rows and columns, respectively. At least one spare column in each of the plurality of memory segments. The at least two memories in accordance with a column address and row selection means for simultaneously selecting respective rows of memory cells in at least two of the segments according to a row address Column selection means for selecting each column from the columns in each said segment in the first half of the segment, wherein the first half is half accessed and the second half is redundant (Rundand) Memory array comprising means for selecting half of columns: an extra choice for selecting at least one redundant column from the redundant half when a predetermined defective column is selected in the accessed half Redundancy selection means; Substitution means for electrically replacing the selected defective column with the selected redundant column: and for simultaneously testing a plurality of cells having a common word address. Random Access Memory (RAM), comprising means. A plurality of array units, each of which includes a plurality of subarray blocks, each of the plurality of subarray blocks comprising a plurality of segments, each of which comprises two-dimensional addressing. A plurality of array units comprising a plurality of memory cells and at least one spare column arranged in a two-dimensional array of possible rows and columns. Row selection means for selecting each of the rows in response to a row address; One half of the subarray block is selected as an accessed half or redundant half, and each said in every segment in the accessed half in response to a column address. Column selection means for selecting columns; Redundancy selection means for selecting a spare column from the spare half for each selected defective column selected in the accessed half; Substitution means for electrically replacing each of the selected defective columns with the selected spare column: and Random access memory (RAM), comprising means for simultaneously testing a plurality of cells having a common word address.