KR0120568B1 - Semiconductor device connection apparatus and manufacture of the same - Google Patents

Semiconductor device connection apparatus and manufacture of the same

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Publication number
KR0120568B1
KR0120568B1 KR1019940009310A KR19940009310A KR0120568B1 KR 0120568 B1 KR0120568 B1 KR 0120568B1 KR 1019940009310 A KR1019940009310 A KR 1019940009310A KR 19940009310 A KR19940009310 A KR 19940009310A KR 0120568 B1 KR0120568 B1 KR 0120568B1
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South Korea
Prior art keywords
film
contact hole
semiconductor substrate
forming
polysilicon
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KR1019940009310A
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Korean (ko)
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KR950030314A (en
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김대영
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김주용
현대전자산업주식회사
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Priority to KR1019940009310A priority Critical patent/KR0120568B1/en
Publication of KR950030314A publication Critical patent/KR950030314A/en
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Publication of KR0120568B1 publication Critical patent/KR0120568B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The method is for enhancing the reliability and the productivity of a semiconductor device by preventing the damage of a semiconductor substrate due to a void generated by the polycrystalline silicon film. The device is characterized by comprising: several conduction lines on top of a semiconductor substrate; a bottom insulation layer on top of the conduction lines; a contact hole revealing the semiconductor substrate; and a plug which is formed by stacking a first polycrystalline silicon film and a second polycrystalline silicon film in the contact hole.

Description

반도체 소자의 접속장치 및 그 제조방법Semiconductor device connection device and manufacturing method

제1a도 내지 제1b도는 종래기술에 의한 반도체소자의 접속장치 형성공정을 도시한 단면도.1A to 1B are cross-sectional views showing a process for forming a connection device of a semiconductor device according to the prior art.

제2a도 내지 제2f도는 본 발명의 제1실시예에 의한 반도체소자의 형성공정을 도시한 단면도.2A to 2F are cross-sectional views showing the process of forming a semiconductor device according to the first embodiment of the present invention.

제3a도 내지 제3e도는 본 발명의 제2실시예에 의한 반도체소자의 접속장치 및 형성공정을 도시한 단면도.3A to 3E are cross-sectional views showing a connection device and a forming process for a semiconductor device according to a second embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 10, 20 : 반도체 기판 2, 12, 22 : 소자분리산화막1, 10, 20: semiconductor substrate 2, 12, 22: device isolation oxide film

3, 13 : 도전배선 4, 14, 27 : 평탄화층3, 13: conductive wiring 4, 14, 27: planarization layer

5, 15, 28 : 제1다결정실리콘막 7 :보이드5, 15, 28: first polysilicon film 7: void

16 : 감광막 17 : 제1보이드16: photosensitive film 17: first void

19, 29 : 제2다결정실리콘막 21 : 게이트산화막19, 29: second polysilicon film 21: gate oxide film

23 : 워드라인용 전도층 24 : 층간절연막23: conductive layer for word line 24: interlayer insulating film

25 : 제1절연막 26 : 제2절연막25: first insulating film 26: second insulating film

27 : 제2보이드 30 : 절연막 스페이서27: second void 30: insulating film spacer

37 : 평탄화층 패턴 20, 50, 70 : 콘택홀37: planarization layer pattern 20, 50, 70: contact hole

본 발명은 반도체소자의 접속장치 및 그 제조방법에 관한 것으로, 종래기술에서 접속장치 형성시 단차피복성이 좋지 않은 다결정실리콘막을 사용함으로써 발생하는 보이드를 방지하기 위하여, 반도체기판 상부에 콘택홀을 형성한 다음, 상기 콘택홀의 내부에서 제1다결정실리콘막의 상부에 제2다결정실리콘막을 증착하되 상기 제1,2다결정실리콘막 증착공정시 발생되는 보이드는 식각공정으로 제거함으로써 반도체소자의 접속장치를 제조하여 보이드로 인한 반도체기판의 손상을 방지할 수 있어 반도체소자의 신뢰성 및 생산성을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device connection device and a method for manufacturing the same. In order to prevent voids caused by using a polycrystalline silicon film having poor step coverage in forming a connection device in the prior art, a contact hole is formed on the semiconductor substrate. Next, a second polysilicon film is deposited on the first polycrystalline silicon film inside the contact hole, and the voids generated during the first and second polysilicon film deposition processes are removed by an etching process, thereby manufacturing a semiconductor device connection device. It is a technology that can prevent damage to the semiconductor substrate due to voids and improve the reliability and productivity of the semiconductor device.

일반적인 반도체소자의 제조공정에서 자기정렬형 콘택홀을 형성한 후에 상기 콘택홀을 매립하고 다시 절연막을 증착한 다음, 상기 매립된 콘택홀에 다시 콘택홀을 형성할 때 상기 콘택홀에 다결정실리콘층으로 채우는 공정이 선행되어야 한다.In the manufacturing process of a general semiconductor device, after forming a self-aligned contact hole, the contact hole is buried, an insulating film is deposited again, and when the contact hole is formed again in the buried contact hole, a polysilicon layer is formed in the contact hole. The filling process must be preceded.

따라서, 종래기술에서 콘택홀 내에 다결정실리콘층을 증착하고 에치백 공정을 실시하는데 이때, 도핑된 다결정실리콘층은 콘택홀이 깊은 부분에서는 단차 피복성이 좋지 못하여 증착시 상기 다결정실리콘층으로 매립한 콘택홀 내부에 구멍, 즉 보이드(void)가 발생된다.Therefore, in the prior art, a polysilicon layer is deposited in the contact hole and an etch back process is performed. In this case, the doped polysilicon layer has a poor step coverage in a deep contact hole, so that the contact is filled with the polysilicon layer during deposition. Holes, or voids, are generated inside the holes.

그로 인하여, 에치백 공정을 실시하면 상기 보이드 부분이 계속 식각되어 반도체기판에 손상을 입혀 생산성을 저하시키는 원인이 된다.Therefore, when the etch back process is performed, the void portion is continuously etched, which causes damage to the semiconductor substrate, thereby lowering productivity.

이하, 첨부된 도면을 참고로 하여 종래기술을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the prior art.

제1a도 내지 제1b도는 종래기술에 의한 반도체소자의 접속장치 형성공정을 도시한 단면도이다.1A to 1B are cross-sectional views showing a process for forming a connection device of a semiconductor device according to the prior art.

제1a도는 반도체기판(1) 상부에 소자분리산화막(2), 도전배선(3)을 형성하고 전체 구조상부에 평탄화층(4)을 형성한 다음, 감광막을 이용하여 콘택마스크(도시안됨)을 형성하고 상기 콘택마스크를 이용하여 상기 평탄화층(4)의 예정된 부위에 콘택홀(20)을 형성한 다음, 상기 콘택홀(20)을 매립하여 상기 반도체기판(1)에 접속되도록 다결정실리콘막(5)을 증착한 것을 도시한 단면도로서, 상기 다결정실리콘막(5)은 도핑된 것을 사용하여 형성한 것이며 상기 다결정실리콘막(5)의 단차피복성이 좋지 않아 상기 콘택홀(20)의 중앙부에 보이드(7)가 형성된 것을 도시한다. 여기서, 상기 평탄화층(4)은 절연막을 사용하여 형성한다.In FIG. 1A, the device isolation oxide film 2 and the conductive wiring 3 are formed on the semiconductor substrate 1, the planarization layer 4 is formed on the entire structure, and then a contact mask (not shown) is formed using a photosensitive film. And forming a contact hole 20 in a predetermined portion of the planarization layer 4 using the contact mask, and then filling the contact hole 20 to connect to the semiconductor substrate 1. 5) is a cross-sectional view showing the deposition of the polysilicon film (5) is formed using a doped one, the step coverage of the polysilicon film (5) is poor, the center portion of the contact hole 20 It shows that the void 7 is formed. Here, the planarization layer 4 is formed using an insulating film.

제1b도는 에치백 공정을 실시하여 상기 다결정실리콘막(5)을 일정두께 식각하여 반도체소자의 접속장치를 형성한 것을 도시한 단면도로서, 상기 보이드(7)가 더욱 깊이 형성된 것을 도시한다. 여기서, 상기 다결정실리콘막(5)의 상부에 많은 다른 다결정실리콘막을 증착하여도 단차피복성이 좋지 못하여 같은 문제점이 발생된다.FIG. 1B is a cross-sectional view showing the connection device of the semiconductor device by etching the polysilicon film 5 by a certain thickness by performing an etch back process, showing that the voids 7 are formed deeper. Here, even if many other polysilicon films are deposited on the polysilicon film 5, the step coverage is not good and the same problem occurs.

상기한 종래기술에 의하면, 콘택홀을 통하여 반도체기판에 접속되는 다결정실리콘막에 발생되는 보이드로 인하여 반도체기판에 손상될 수 있어 반도체소자의 생산성 및 신뢰성을 저하시켜 고집적화를 어렵게 한다.According to the above-described prior art, the voids generated in the polysilicon film connected to the semiconductor substrate through the contact hole may damage the semiconductor substrate, thereby lowering the productivity and reliability of the semiconductor device, making it difficult to achieve high integration.

따라서, 본 발명은 종래기술의 문제점을 해결하기 위하여, 반도체기판 상부에 접속장치를 형성하기 위한 콘택홀을 형성한 다음, 상기 콘택홀을 매립하여 반도체기판에 접속되는 제1다결정실리콘막을 증착하고 발생되는 제1보이드를 감광막을 이용하여 매립한 다음, 상기 감광막이 매립된 보이드를 제거하고 동시에 콘택홀 내부에 형성된 제1다결정실리콘막을 평탄화시킨 다음, 제2다결정실리콘막을 상기 제1다결정실리콘막의 상부에 증착함으로써 발생되는 상기 제1보이드보다 작은 제2보이드를 제거함으로써 보이드가 없는 반도체소자의 접속장치를 제조하는데 그 목적이 있다.Accordingly, in order to solve the problems of the related art, the present invention forms a contact hole for forming a connection device on an upper surface of the semiconductor substrate, and then deposits and generates a first polycrystalline silicon film connected to the semiconductor substrate by filling the contact hole. After the first void is buried by using a photoresist film, the void having the photoresist film embedded therein is removed, and at the same time, the first polysilicon film formed inside the contact hole is planarized, and then a second polysilicon film is formed on the first polycrystalline silicon film An object of the present invention is to manufacture a void-free connection device of a semiconductor device by removing a second void smaller than the first void generated by vapor deposition.

이상의 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 도전배선(3)이 다수개 구비되고 그 상부에 하부절연층이 형성되고, 상기 반도체기판이 노출된 콘택홀이 형성되고, 상기 콘택홀에 제1다결정실리콘막과 제2다결정실리콘막이 적층된 구조로 플러그가 구비된 것이다.In order to achieve the above object, a feature of the present invention is that a plurality of conductive wirings 3 are provided on a semiconductor substrate, a lower insulating layer is formed on the semiconductor substrate, and a contact hole through which the semiconductor substrate is exposed is formed. The first polycrystalline silicon film and the second polysilicon film are laminated in the hole, and the plug is provided.

이상의 다른 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 소자분리산화막을 형성한 다음, 도전배선을 형성하고 전체구조상부에 평탄화층을 형성하는 공정과, 감광막을 이용하여 콘택마스크를 형성하고 상기 콘택마스크를 이용하여 상기 반도체기판의 예정된 부위에 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 반도체기판에 접속하는 제1다결정실리콘막을 예정된 두께로 증착하는 공정과, 감광막을 도포한 다음, 감광막 에치백하여 콘택홀 내부에만 감광막을 남겨놓는 공정과, 상기 감광막을 마스크로 하여 감광막의 저부면까지 상기 콘택홀의 내부에 매립된 제1다결정실리콘막을 식각하는 동시에 상기 감광막을 제거하는 공정과, 전체구조상부에 제2다결정실리콘막을 예정된 두께로 증착하는 공정과, 상기 제2다결정실리콘막을 상기 평탄화층이 노출될 때까지 전면 식각하여 상기 콘택홀의 내부에 보이드가 발생되지 않은 제1,2다결정실리콘막의 이중구조로 된 플러그를 형성하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is to form a device isolation oxide film on the semiconductor substrate, and then to form a conductive wiring and a planarization layer on the entire structure, and to form a contact mask using a photosensitive film And forming a contact hole in a predetermined portion of the semiconductor substrate using the contact mask, depositing a first polycrystalline silicon film connected to the semiconductor substrate through the contact hole to a predetermined thickness, and applying a photosensitive film. Next, the photoresist film is etched back so as to leave the photoresist only in the contact hole, and the first polycrystalline silicon film embedded in the contact hole is removed to the bottom surface of the photoresist using the photoresist as a mask and simultaneously removed. And depositing a second polysilicon film on the entire structure to a predetermined thickness, and the second polycrystalline silicon. And etching the entire surface until the planarization layer is exposed, thereby forming a plug having a double structure of the first and second polysilicon layers in which voids are not generated in the contact hole.

이상의 다른 목적을 달성하기 위한 본 발명의 다른 특깅은, 반도체기판 상부에 소자분리산화막과 상하부에 층간절연막과 산화막이 구비된 도전배선을 형성하는 공정과, 전체구조상부에 제1절연막과 제2절연막을 순차적으로 일정두께 증착하고 그 상부에 평탄화층을 형성하는 공정과, 콘택마스크를 이용하여 상기 평탄화층을 식각하고 상기 제1절연막을 식각장벽으로 하여 상기 제2절연막을 식각하는 공정과, 전체구조상부에 제3절연막을 일정두께 증착한 다음, 이방성 식각함으로써 상기 반도체기판을 노출시키는 콘택홀을 형성함과 동시에 상기 콘택홀의 측벽에 절연막 스페이서를 형성하는 공정과, 상기 콘택홀을 통하여 상기 반도체기판에 접속하는 제1다결정실리콘막을 예정된 두께로 증착하는 공정과, 감광막을 도포한 다음, 감광막 에치백하여 콘택홀 내부에만 감광막을 감광막을 남겨놓는 공정과, 상기 감광막을 마스크로 하여 감광막의 저부면까지 상기 콘택홀의 내부에 매립된 제1다결정실리콘막을 식각하는 동시에 상기 감광막을 제거하는 공정과, 전체구조상부에 제2다결정실리콘막을 예정된 두께로 증착하는 공정과, 상기 제2다결정실리콘막을 상기 평탄화층이 노출될 때까지 전면식각하여 자기정렬적으로 형성된 상기 콘택홀의 내부에 보이드가 발생되지 않은 제1,2다결정실리콘막의 이중구조로 된 플러그를 형성하는 공정을 포함하는데 있다.Another feature of the present invention for achieving the above object is to form a device isolation oxide film on the semiconductor substrate and a conductive wiring provided with an interlayer insulating film and an oxide film on the upper and lower portions, the first insulating film and the second insulating film on the entire structure Sequentially depositing a predetermined thickness and forming a planarization layer thereon, etching the planarization layer using a contact mask, and etching the second insulation layer using the first insulating layer as an etch barrier; Forming a contact hole for exposing the semiconductor substrate by anisotropic etching after depositing a third insulating layer to a predetermined thickness and forming an insulating film spacer on the sidewall of the contact hole; and forming a contact hole on the semiconductor substrate through the contact hole. Depositing a first polysilicon film to be connected to a predetermined thickness; applying a photosensitive film; and then etching back the photosensitive film Leaving a photoresist film on the inside of the tackhole only; etching the first polycrystalline silicon film embedded in the contact hole to the bottom surface of the photoresist film using the photoresist as a mask, and removing the photoresist film; Depositing a second polysilicon film to a predetermined thickness; and etching the second polysilicon film over the entire surface of the second polycrystalline silicon film until the planarization layer is exposed; It includes a step of forming a plug having a double structure of a silicon film.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2a도 내지 제2f도는 본 발명의 제1실시예로서 반도체소자의 접속장치 제조공정을 도시한 단면도이다.2A to 2F are sectional views showing the manufacturing process of a connection device of a semiconductor device as a first embodiment of the present invention.

제2a도는 반도체기판(10) 상부에 소자분리산화막(12) 및 도전배선(13)을 순차적으로 형성한 다음, 전체 구조상부에 평탄화층(14)을 형성한 것을 도시한 단면도이다. 여기서, 상기 평탄화층(14)은 절연막을 사용하여 형성한다.FIG. 2A is a cross-sectional view illustrating that the device isolation oxide film 12 and the conductive wiring 13 are sequentially formed on the semiconductor substrate 10 and then the planarization layer 14 is formed over the entire structure. Here, the planarization layer 14 is formed using an insulating film.

제2b도는 상기 평탄화층(14) 상부에 감광막을 이용하여 콘택마스크(도시안됨)를 형성하고 상기 콘택마스크를 사용하여 상기 반도체기판(10)을 노출시키는 콘택홀(50)을 형성한 다음, 불순물이 도핑된 제1다결정실리콘막(15)을 사용하여 상기 반도체기판(10)에 접속되도록 상기 콘택홀(50)을 매립한 것을 도시한 단면도로서, 상기 제1다결정실리콘막(15)의 나쁜 단차피복성으로 인하여 상기 콘택홀(50)의 증앙부에 제1보이드(17)가 형성된 것을 도시한 것이다. 여기서, 상기 제1다결정실리콘막(15)은 불순물이 도핑되지 않은 다결정실리콘을 사용하여 형성할 수도 있다.FIG. 2B illustrates that a contact mask (not shown) is formed on the planarization layer 14 using a photoresist film, and a contact hole 50 is formed using the contact mask to expose the semiconductor substrate 10. A cross-sectional view showing that the contact hole 50 is buried so as to be connected to the semiconductor substrate 10 by using the doped first polysilicon film 15, and a bad step of the first polysilicon film 15 is shown. It is shown that the first void 17 is formed in the central portion of the contact hole 50 due to the covering property. The first polysilicon layer 15 may be formed using polycrystalline silicon that is not doped with impurities.

제2c도는 전체구조상부에 감광막(16)을 도포한 다옴, 에치백 공정을 실시하여 상기 제1보이드(17)가 발생된 부위에만 상기 감광막(16)을 남긴 것을 도시한 단면도이다.FIG. 2C is a cross-sectional view illustrating the photoresist film 16 being applied to the entire structure and leaving the photoresist film 16 only at a portion where the first void 17 is generated by performing an etch back process.

제2d도는 상기 감광막(16)을 식각장벽으로 하여 상기 노출된 제1다결정실리콘막(15)을 상기 제1보이드(17)에 형성된 상기 감광막(16)의 밑부분까지 식각하여 상기 콘택홀(50) 내부의 상기 제1다결정실리콘막(15)을 평탄화시킴과 동시에 상기 감광막(16)으로 채워진 제1보이드(17)를 제거한 것을 도시한 단면도이다.2d illustrates that the exposed first polysilicon layer 15 is etched to the bottom of the photosensitive layer 16 formed on the first void 17 by using the photosensitive layer 16 as an etch barrier. ) Is a cross-sectional view of the planarization of the first polysilicon film 15 inside the substrate and removal of the first void 17 filled with the photosensitive film 16.

제2e도는 전체구조상부에 계2다결정실리콘막(19)을 일정두께 증착한 것을 도시한 단면도로서, 상기 콘택홀(50)은 제1다결정실리콘막(15)에 의하여 일정깊이가 채워진 상태이므로 상기 제2다결정실리콘막(19)에 의하여 발생되는 제2보이드(27)는 더 낮게 형성된다.FIG. 2E is a cross-sectional view of depositing a predetermined thickness of the second polysilicon film 19 on the entire structure. The contact hole 50 is filled with a predetermined depth by the first polycrystalline silicon film 15. The second void 27 generated by the second polysilicon film 19 is formed lower.

제2f도는 상기 제2다결정실리콘막(19)을 에치백 공정으로 식각하여 상기 제2다결정실리콘막(19)을 평탄화시킴으로써 상기 제2보이드(27)가 제거된 제1다결정실리콘막(18)과 제2다결정실리콘막(19)의 이중구조로 형성된 플러그를 구비하는 반도체소자의 접속장치를 형성한 것을 도시한 단면도이다.2f illustrates the first polysilicon film 18 from which the second void 27 is removed by etching the second polysilicon film 19 by an etch back process to planarize the second polysilicon film 19. It is sectional drawing which shows the formation of the connection device of the semiconductor element provided with the plug formed in the double structure of the 2nd polycrystalline silicon film 19. As shown in FIG.

제3a도 내지 제3E도는 본 발명의 제2실시예로서 반도체소자의 접속장치를 형성한 것을 도시한 단면도이다.3A to 3E are sectional views showing the formation of a connection device of a semiconductor element as a second embodiment of the present invention.

제3a도는 반도체기판(20) 상부에 소자분리산화막(22)과 도선배선을 형성한 것을 도시한 단면도로서, 상기 도선배선은 게이트산화막(21), 워드라인용 전도층(23) 및 층간절연막(24)을 적층되게 형성한 것을 도시한다.3A is a cross-sectional view illustrating a device isolation oxide film 22 and a conductive wiring formed on the semiconductor substrate 20. The conductive wiring includes a gate oxide film 21, a word layer conductive layer 23, and an interlayer insulating film ( 24 is formed to be stacked.

제3b도는 전체구조상부에 제1절연막(25)과 제2절연막(26)을 순차적으로 일정두께 증착하고 그 상부에 평탄화층(27)을 형성한 것을 도시한 단면도로서, 상기 제1,2절연막(25,26)은 실리콘질화막을 사용하여 형성하며 상기 평탄화층(27)은 절연막을 사용하여 형성한다.FIG. 3B is a cross-sectional view showing that the first insulating film 25 and the second insulating film 26 are sequentially deposited to a predetermined thickness on the entire structure, and the planarization layer 27 is formed thereon. 25 and 26 are formed using a silicon nitride film, and the planarization layer 27 is formed using an insulating film.

제3c도는 상기 평탄화층(27) 상부에 감광막을 이용하여 콘택마스크(도시안됨)를 형성한 다음, 상기 콘택마스크를 사용하고 상기 제1절연막(25)을 식각장벽으로 사용하여 평탄화층(27)과 제2절연막(26)을 순차적으로 식각함으로써 평탄화층 패턴(37)을 형성한 다음, 상기 콘택마스크를 제거한 것을 도시한 단면도이다.3C illustrates that a contact mask (not shown) is formed on the planarization layer 27 by using a photoresist film, and then the planarization layer 27 is formed by using the contact mask and using the first insulating layer 25 as an etch barrier. And the second insulating layer 26 are sequentially etched to form the planarization layer pattern 37, and then the contact mask is removed.

제3d도는 전체구조상부에 제3절연막을 일정두께 증착하고 이방성 식각을 실시하여 절연막 스페이서(30)을 형성함과 동시에 콘택홀(70)을 형성한 것을 도시한 단면도로서, 상기 콘택홀(70)은 상기 절연막 스페이서(30) 형성시 실시하는 이방성 식각공정에서 약간의 과식각을 실시하여 상기 제1절연막(B)을 식각함으로써 형성한 것이다.FIG. 3D is a cross-sectional view illustrating the formation of the insulating layer spacer 30 and the formation of the contact hole 70 at the same time by depositing a third insulating layer on the entire structure and performing anisotropic etching to form the contact hole 70. In the anisotropic etching process performed at the time of forming the insulating film spacer 30, the first insulating film B is etched by performing a slight overetching.

제3e도는 제3d도 공정후에 본 발명의 제1실시예에 의한 반도체소자의 접속장치 형성공정에서 콘택홀(50)을 형성한 후, 플러그 형성공정을 동일하게 실시하여 상기 콘택홀(70) 측벽에 형성된 절연막 스페이서(30) 사이에 제1다결정실리콘막(28)과 제2다결정실리콘막(29)가 적층된 구조로 형성된 플러그를 형성한 반도체소자의 접속장치를 도시한 단면도이다.3E and 3D, after the contact hole 50 is formed in the semiconductor device connection device forming process according to the first embodiment of the present invention, the plug forming process is performed in the same manner to form the sidewalls of the contact hole 70. A cross-sectional view showing a semiconductor device connecting device in which a plug formed with a structure in which a first polycrystalline silicon film 28 and a second polysilicon film 29 are stacked between insulating film spacers 30 formed thereon is formed.

상기한 본 발명에 의하면, 종래기술에서 접속장치 형성시 다결정실리콘막의 단차피복성 불량으로 보이드가 발생되는대 상기 보이드를 제거함으로써 상기 보이드로 인하여 발생되는 반도체기판의 손상을 방지할 수 있어 반도체소자의 신뢰성 및 생산성을 향상시킬 수 있다.According to the present invention described above, when voids are generated due to poor step coverage of the polysilicon film when the connection device is formed in the related art, damage to the semiconductor substrate caused by the voids can be prevented by removing the voids. It can improve the reliability and productivity.

Claims (13)

반도체소자의 접속장치에 있어서, 반도체기판 상부에 도전배선이 다수개 구비되고 그 상부에 하부절연층이 형성되고, 상기 반도체기판이 노출된 콘랙홀이 형성되고, 상기 콘택홀에 제1다결정실리콘막과 제2다결정실리콘막이 적층된 구조로 플러그가 구비된 것을 특징으로 하는 반도체소자의 접속장치.In a device for connecting a semiconductor device, a plurality of conductive wirings are provided on a semiconductor substrate, a lower insulating layer is formed on the semiconductor substrate, a contact hole is formed in which the semiconductor substrate is exposed, and a first polycrystalline silicon film is formed in the contact hole. And a plug having a structure in which a second polycrystalline silicon film is laminated. 제1항에 있어서, 상기 제1,2다결정실리콘막은 불순물이 도핑된 또는 도핑되지 않은 다결정실리콘막이 사용되는 것을 특징으로 하는 반도체소자의 접속장치.The semiconductor device connection device according to claim 1, wherein the first and second polysilicon films are made of a doped or undoped polysilicon film. 제1항에 있어서, 상기 콘택홀의 측벽과 플러그 사이에 스페이서를 형성하는 것을 특징으로 하는 반도체소자의 접속장치.The semiconductor device connection device according to claim 1, wherein a spacer is formed between the side wall of the contact hole and the plug. 반도체소자의 접속장치 제조방법에 있어서, 반도체기판 상부에 소자분리산화막을 형성한 다음, 도전배선을 형성하고 전체구조상부에 평탄화층을 형성하는 공정과, 감광막을 이용하여 콘택마스크를 형성하고 상기 콘택마스크를 이용하여 상기 반도체기판의 예정된 부위에 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 반도체기판에 접속하는 제1다결정실리콘막을 예정된 두께로 증착하는 공정과, 감광막을 도포한 다음, 감광막 에치백하여 콘택홀 내부에만 감광막을 남겨놓는 공정과, 상기 감광막을 마스크로 하여 감광막의 저부면까지 상기 콘택홀의 내부에 매립된 제1다결정실리콘막을 식각하는 동시에 상기 감광막을 제거하는 공정과, 전체구조상부에 제2다결정실리콘막을 예정된 두께로 증착하는 공정과, 상기 제2다결정실리콘막을 상기 평탄화층이 노출될 때까지 전면식각하여 상기 콘택홀의 내부에 보이드가 발생되지 않은 제1,2다결정실리콘막의 이중구조로 된 플러그를 형성하는 공정을 포함하는 반도체소자의 접속장치 제조방법.A method of manufacturing a connection device for a semiconductor device, comprising: forming a device isolation oxide film on a semiconductor substrate, forming a conductive wiring, and forming a planarization layer over the entire structure; forming a contact mask using a photosensitive film; Forming a contact hole in a predetermined portion of the semiconductor substrate using a mask; depositing a first polycrystalline silicon film connected to the semiconductor substrate to the predetermined thickness through the contact hole; applying a photosensitive film, and then applying a photosensitive film. Leaving the photoresist film only inside the contact hole by etching back, etching the first polycrystalline silicon film embedded in the contact hole to the bottom surface of the photoresist film using the photoresist as a mask and simultaneously removing the photoresist film; Depositing a second polysilicon film on a predetermined thickness thereon, and depositing the second polycrystalline silicon film on the And etching the entire surface until the planarization layer is exposed to form a plug having a double structure of the first and second polycrystalline silicon films in which voids are not generated in the contact hole. 제4항에 있어서, 상기 제1,2다결정실리콘막은 불순물이 도핑된 또는 도핑되지 않은 다결정실리콘막을 사용하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.The method of manufacturing a connection device of a semiconductor device according to claim 4, wherein said first and second polysilicon films are made of a polysilicon film doped or not doped with impurities. 제4항에 있어서, 상기 콘택홀의 측벽에 스페이서를 형성한 다음, 상기 콘택홀의 내부에 상기 제1,2다결정실리콘막의 적층된 구조의 접속장치를 형성하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.The method of claim 4, wherein a spacer is formed on a sidewall of the contact hole, and then a connection device having a stacked structure of the first and second polysilicon layers is formed inside the contact hole. . 제4항에 있어서, 상기 제2다결정실리콘막을 전면식각할 때는 등방성이나 이방성으로 식각하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.The method of manufacturing a connection device of a semiconductor device according to claim 4, wherein the second polysilicon film is etched isotropically or anisotropically when etching the entire surface. 반도체소자의 접속장치 제조방법에 있어서, 반도체기판 상부에 소자분리산화막과 상하부에 층간절연막과 산화막이 구비된 도전배선을 형성하는 공정과, 전체구조상부에 제1절연막과 제2전연막을 순차적로 일정두께 증착하고 그 상부에 평탄화층을 형성하는 공정과, 콘택마스크를 이용하여 상기 평탄화층을 식각하고 상기 제1절연막을 식각장벽으로 하여 상기 제2절연막을 식각하는 공정과, 전체구조상부에 제3절연막을 일정두께 증착한 다음, 이방성 식각함으로써 상기 반도체기판을 노출시킨는 콘택홀을 형성함과 동시에 상기 콘택홀의 측벽에 절연막 스페이서를 형성하는 공정과, 상기 콘택홀을 통하여 상기 반도체기판에 접속하는 제1다결정실리콘막을 예정된 두께로 증착하는 공정과, 감광막을 도포한 다음, 감광막 에치백하여 콘택홀 내부에만 감광막을 남겨놓는 공정과, 상기 감광막을 마스크로 하여 감광막의 저부면까지 상기 콘택홀의 내부에 매립된 제1다결정실리콘막을 식각하는 동시에 상기 감광막을 제거하는 공정과, 전체구조상부에 제2다결정실리콘막을 예정된 두께로 증착하는 공정과, 상기 제2다결정실리콘막을 상기 평탄화층이 노출될 때까지 전면식각하여 자기정렬적으로 형성된 상기 콘택홀의 내부에 보이드가 발생되지 않은 제1,2다결정실리콘막의 이중구조로 된 플러그를 형성하는 공정을 포함하는 반도체소자의 접속장치 제조방법.A method of manufacturing a connection device for a semiconductor device, comprising: forming a device isolation oxide film on a semiconductor substrate and a conductive wiring including an interlayer insulating film and an oxide film on upper and lower portions of the semiconductor substrate; and sequentially forming a first insulating film and a second electrode film on the entire structure. Depositing a thickness and forming a planarization layer thereon; etching the planarization layer using a contact mask; and etching the second insulation layer using the first insulating layer as an etch barrier; Depositing an insulating film to a predetermined thickness, and then forming an contact hole exposing the semiconductor substrate by anisotropic etching, and forming an insulating film spacer on the sidewall of the contact hole, and connecting the semiconductor substrate to the semiconductor substrate through the contact hole. Depositing a polysilicon film to a predetermined thickness, applying a photoresist film, and then etching back the photoresist film, Leaving the photo film, etching the first polycrystalline silicon film embedded in the contact hole to the bottom surface of the photoresist using the photoresist as a mask, and removing the photoresist; and a second polysilicon film over the entire structure. And a double structure of the first and second polysilicon films in which the voids are not generated in the contact holes formed by self-aligning the entire surface by etching the second polysilicon film until the planarization layer is exposed. A method of manufacturing a connection device for a semiconductor device comprising the step of forming a plug. 제8항에 있어서, 상기 평탄화층은 절연막을 사용하여 형성하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.The method of claim 8, wherein the planarization layer is formed using an insulating film. 제8항에 있어서, 상기 플러그의 폭은 상기 절연막 스페이서의 두께로 조절하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.The method of claim 8, wherein the width of the plug is adjusted by a thickness of the insulation spacer. 제8항에 있어서, 상기 제1,2절연막은 실리콘질화막을 사용하여 형성하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.10. The method of claim 8, wherein the first and second insulating films are formed using a silicon nitride film. 제8항에 있어서, 상기 콘택홀의 측벽에 스페이서를 형성하지 않음으로써 접속면적이 넓은 플러그를 형성하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.The method of claim 8, wherein a plug having a large connection area is formed by not forming a spacer on the sidewall of the contact hole. 제8항에 있어서, 상기 제2다결정실리콘막을 전면식각할 때는 등방성이나 이방성으로 식각하는 것을 특징으로 하는 반도체소자의 접속장치 제조방법.The method of claim 8, wherein the entire surface of the second polysilicon film is etched isotropically or anisotropically.
KR1019940009310A 1994-04-29 1994-04-29 Semiconductor device connection apparatus and manufacture of the same KR0120568B1 (en)

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KR100426764B1 (en) * 2000-04-13 2004-04-13 엔이씨 일렉트로닉스 코포레이션 Semiconductor device and manufacturing method therefor

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KR100400037B1 (en) * 2001-02-22 2003-09-29 삼성전자주식회사 Semiconductor device with contact plug and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426764B1 (en) * 2000-04-13 2004-04-13 엔이씨 일렉트로닉스 코포레이션 Semiconductor device and manufacturing method therefor

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