JPWO2014119434A1 - Mounting method and mounting apparatus - Google Patents

Mounting method and mounting apparatus Download PDF

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JPWO2014119434A1
JPWO2014119434A1 JP2014559639A JP2014559639A JPWO2014119434A1 JP WO2014119434 A1 JPWO2014119434 A1 JP WO2014119434A1 JP 2014559639 A JP2014559639 A JP 2014559639A JP 2014559639 A JP2014559639 A JP 2014559639A JP WO2014119434 A1 JPWO2014119434 A1 JP WO2014119434A1
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substrate
mounting
holding stage
substrate holding
chip component
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JP6291426B2 (en
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幹夫 川上
幹夫 川上
義浩 木下
義浩 木下
正弘 小川
正弘 小川
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Toray Engineering Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04Mounting of components, e.g. of leadless components
    • H05K13/046Surface mounting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/08Monitoring manufacture of assemblages
    • H05K13/089Calibration, teaching or correction of mechanical systems, e.g. of the mounting head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75753Means for optical alignment, e.g. sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/759Means for monitoring the connection process
    • H01L2224/75901Means for monitoring the connection process using a computer, e.g. fully- or semi-automatic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Operations Research (AREA)
  • Wire Bonding (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Abstract

チップ部品を基板に実装する範囲が大きくなっても、チップ部品を基板の所定の位置に高精度に実装する実装方法および実装装置を提供すること。具体的には、チップ部品のアライメントマークと基板のアライメントマークを画像認識手段で認識してチップと基板のアライメントを行った後に、チップ部品を加圧し実装する時に生じる位置ズレ量を相殺する実装オフセットを、基板を保持する基板保持ステージ面内の位置および接合時の加圧力の関数として設定することを特徴とする実装方法および実装装置を提供する。選択図 図1To provide a mounting method and a mounting apparatus for mounting a chip component at a predetermined position on a substrate with high accuracy even when the range for mounting the chip component on a substrate becomes large. Specifically, after the alignment mark of the chip component and the alignment mark of the substrate are recognized by the image recognition means and the alignment of the chip and the substrate is performed, the mounting offset that offsets the positional deviation generated when the chip component is pressed and mounted. Is provided as a function of the position in the surface of the substrate holding stage that holds the substrate and the pressure applied during bonding, and a mounting method and apparatus. Figure 1

Description

本発明は、電子部品などのチップ部品を、基板保持ステージ上に載置された、セラミックス、樹脂、ガラス等からなる基板の所定の位置に実装する実装方法及び実装装置に関する。   The present invention relates to a mounting method and a mounting apparatus for mounting a chip component such as an electronic component on a predetermined position of a substrate made of ceramics, resin, glass or the like placed on a substrate holding stage.

一般に、電子部品などのチップ部品を基板に実装する実装装置は、例えばチップ部品を真空吸着保持するボンディングヘッドと、ボンディングヘッドを上下方向に移動させる機構と、基板を吸着保持する基板保持ステージと、基板保持ステージを水平方向及び回転方向に移動させる機構と、ボンディングヘッドと基板保持ステージとの空間に進退可能に設けられ且つボンディングヘッド側と基板保持ステージ側とを同時に撮像可能な2視野カメラとを有する。この実装装置では、2視野カメラを上記空間に進入させて、ボンディングヘッドが保持したチップ部品に書かれたアライメントマークと、基板に書かれたアライメントマークを同時に読み取り、その読み取り情報に基づいてチップ部品と基板における実装位置との位置合わせを行う。そして、2視野カメラを待避させた後、ヘッドを下降させて、チップ部品を基板における実装位置に接合させる(例えば、特許文献1)。   In general, a mounting apparatus for mounting a chip component such as an electronic component on a substrate includes, for example, a bonding head that vacuum-holds the chip component, a mechanism that moves the bonding head in a vertical direction, a substrate holding stage that sucks and holds the substrate, A mechanism for moving the substrate holding stage in the horizontal direction and the rotation direction, and a two-field camera provided in a space between the bonding head and the substrate holding stage so as to be capable of moving back and forth and capable of simultaneously imaging the bonding head side and the substrate holding stage side. Have. In this mounting apparatus, a two-view camera is entered into the space, and the alignment mark written on the chip component held by the bonding head and the alignment mark written on the substrate are simultaneously read, and the chip component is based on the read information. Is aligned with the mounting position on the board. Then, after retracting the two-view camera, the head is lowered to join the chip component to the mounting position on the substrate (for example, Patent Document 1).

特開2004−22949号公報Japanese Patent Laid-Open No. 2004-22949

近年、生産効率を上げることを目的として基板のサイズが大きくなる傾向、あるいは基板保持ステージに多くの基板を載置する傾向にあるため、基板保持ステージの大型化が進んでいる。一方、基板保持ステージの大型化により、実装範囲が大きくなるにも係わらず、位置ズレの許容範囲が1μm以下のような高精度実装の要求は高まっている。   In recent years, the size of the substrate holding stage has been increasing for the purpose of increasing production efficiency, or a large number of substrates have been placed on the substrate holding stage. On the other hand, with the increase in the size of the substrate holding stage, there is an increasing demand for high-accuracy mounting such that the allowable range of positional deviation is 1 μm or less, in spite of an increase in the mounting range.

このように、実装範囲が大きくなることと関係し、新たな問題が発生している。それは、2視野カメラがボンディングヘッドと基板ステージとの間にある状態で位置ズレが1μm以下となるように位置合わせを行ったにも係わらず、実際に基板に実装された状態での位置ズレ量が数μmを超えているものが存在することである。この位置ズレ量は、基板保持ステージ面内における実装位置と実装時の加圧力が同じであれば再現することから、実際の量産工程においては、この位置ズレ量を相殺するためのオフセットを設定することにより実装精度を確保している。ただし、このオフセットは、基板、チップ、実装時の加圧力によって変化することから、実装条件毎に、試行錯誤により個別に設定している。   As described above, a new problem has arisen in connection with an increase in the mounting range. This is the amount of positional deviation when the two-view camera is actually mounted on the substrate even though the positional deviation is 1 μm or less with the two-field camera between the bonding head and the substrate stage. Exists that exceeds several μm. This positional deviation amount is reproduced if the mounting position in the substrate holding stage surface is the same as the applied pressure at the time of mounting. Therefore, in the actual mass production process, an offset for offsetting this positional deviation amount is set. This ensures mounting accuracy. However, since this offset varies depending on the substrate, the chip, and the applied pressure during mounting, it is set individually for each mounting condition by trial and error.

ここで、チップ部品に書かれたアライメントマークと基板に書かれたアライメントマークは、いずれも接合面側にあるため、実装後のアライメントマークを観察するためにX線による透視が必要になり、実装後の位置ズレ量を測定するだけでも大きな手間を要する。   Here, since the alignment mark written on the chip component and the alignment mark written on the substrate are both on the bonding surface side, X-ray fluoroscopy is necessary to observe the alignment mark after mounting. Even just measuring the amount of subsequent positional deviation requires a lot of labor.

このように、実装条件毎にオフセットを設定する方法では、時間的な無駄が生じ、条件設定するまでのチップ部品および基板も無駄になる。   As described above, in the method of setting the offset for each mounting condition, time is wasted, and chip components and substrates until the condition is set are also wasted.

本発明は、このような事情に鑑みてなされたものであって、チップ部品を実装する、基板保持ステージ面内の位置および実装時の加圧条件が決まれば、オフセットが求まる実装方法および、この実装方法を行う機能を備えた実装装置を提供することを目的とする。   The present invention has been made in view of such circumstances, and a mounting method in which an offset is obtained if a position in a substrate holding stage surface on which a chip component is mounted and a pressurizing condition at the time of mounting are determined, and this An object of the present invention is to provide a mounting apparatus having a function of performing a mounting method.

上記課題を解決するために、請求項1に記載の発明は、チップ部品のアライメントマークと基板のアライメントマークを画像認識手段で認識してチップ部品と基板のアライメントを行った後にチップ部品を加圧して基板に実装する実装方法において、アライメント後にチップ部品を加圧して実装する時に生じる位置ズレ量を相殺する実装オフセットを、基板を保持する基板保持ステージ面内の位置および接合時の加圧力の関数として設定することを特徴とする実装方法である。   In order to solve the above problem, the invention according to claim 1 is directed to pressurizing the chip component after the alignment mark of the chip component and the alignment mark of the substrate are recognized by the image recognition means and the chip component and the substrate are aligned. In the mounting method that mounts on the board, the mounting offset that offsets the amount of misalignment that occurs when the chip components are pressed and mounted after alignment is a function of the position within the surface of the board holding stage that holds the board and the pressure applied during bonding. It is the mounting method characterized by setting as.

請求項2に記載の発明は、請求項1に記載の実装方法であって、基板保持ステージ面内の複数の位置における複数条件の加圧力に対する位置ズレ量を求め、その結果を基に、基板保持ステージ面内の位置および接合時の加圧力と位置ズレ量の関係を表す関数を導出することを特徴とする実装方法である。   Invention of Claim 2 is the mounting method of Claim 1, Comprising: The position shift amount with respect to the pressurizing force of several conditions in several positions in a board | substrate holding | maintenance stage surface is calculated | required, Based on the result, a board | substrate A mounting method is characterized by deriving a function representing a relationship between a position within a holding stage surface and a pressure applied during bonding and a positional deviation amount.

請求項3に記載の発明は、請求項2に記載の実装方法であって、基板保持ステージ面内の複数の位置における複数条件の加圧力に対する位置ズレ量を求めるに際して、アライメントマークが記された、透明なチップ部品を用いることを特徴とする実装方法である。   The invention according to claim 3 is the mounting method according to claim 2, wherein an alignment mark is written when obtaining a positional shift amount with respect to a plurality of conditions of applied pressure at a plurality of positions in the substrate holding stage surface. The mounting method is characterized by using a transparent chip component.

請求項4に記載の発明は、チップ部品を吸着保持するボンディングヘッドと、ボンディングヘッドを上下方向に移動させる機構と、基板を載置保持する基板保持ステージと、ボンディングヘッドと基板保持ステージが相対的に水平方向及び回転方向に移動させる機構と、ボンディングヘッドと基板保持ステージとの空間に進退可能に設けられ且つボンディングヘッド側と基板保持ステージ側とを同時に撮像可能な2視野認識手段を有する実装装置であって、請求項1から3の何れかに記載の実装方法を行う機能を備えた実装装置である。   According to a fourth aspect of the present invention, the bonding head for sucking and holding the chip components, the mechanism for moving the bonding head in the vertical direction, the substrate holding stage for mounting and holding the substrate, and the bonding head and the substrate holding stage are relative to each other. Mounting mechanism having a mechanism for moving the bonding head and the substrate holding stage in a horizontal direction and a rotational direction, and a two-field recognition means capable of moving forward and backward in the space between the bonding head and the substrate holding stage and capable of simultaneously imaging the bonding head side and the substrate holding stage side. And it is a mounting apparatus provided with the function to perform the mounting method in any one of Claims 1-3.

本発明を用いることにより、アライメント後にチップ部品を加圧して実装する時に生じる位置ズレ量を相殺するオフセットを容易に得ることが出来、実装工程の生産性が向上する。   By using the present invention, it is possible to easily obtain an offset that offsets the amount of misalignment that occurs when a chip component is pressed and mounted after alignment, and the productivity of the mounting process is improved.

本発明の一実施形態に係る実装方法を実施するためのフリップチップ実装装置の要部正面図である。It is a principal part front view of the flip chip mounting apparatus for enforcing the mounting method which concerns on one Embodiment of this invention. 本発明が対象とする実装に用いられる基板について説明する図である。It is a figure explaining the board | substrate used for the mounting which this invention makes object. 本発明の一実施形態に用いる模擬基板と模擬チップを説明する図である。It is a figure explaining the simulation board | substrate and simulation chip | tip used for one Embodiment of this invention. 本発明の一実施形態に係る模擬基板と模擬チップの位置ズレ量評価を行う場所を示す図である。It is a figure which shows the place which performs the positional offset amount evaluation of the simulation board | substrate and simulation chip which concerns on one Embodiment of this invention. 本発明の一実施形態におけるアライメントマーク相互の位置ズレを説明する図である。It is a figure explaining the position shift of the alignment marks in one Embodiment of this invention. 本発明の一実施形態で得るデータ群を説明する図である。It is a figure explaining the data group obtained by one Embodiment of this invention. 本発明の一実施形態における装置動作および演算のフローチャートである。It is a flowchart of apparatus operation | movement and calculation in one Embodiment of this invention. 本発明の実施例1で用いた基板保持ステージの構造を説明する図である。It is a figure explaining the structure of the board | substrate holding | maintenance stage used in Example 1 of this invention. 本発明の実施例1で用いた模擬基板を説明する図である。It is a figure explaining the simulation board | substrate used in Example 1 of this invention. 本発明の実施例1で得た実測データである。It is the actual measurement data obtained in Example 1 of this invention. 本発明の実施例1に係る、近似式から得たデータである。It is the data obtained from the approximate expression based on Example 1 of this invention.

以下に、本発明の一実施形態について、図面を参照して説明する。   An embodiment of the present invention will be described below with reference to the drawings.

図1は、実装装置の基本的な機能を説明するための要部正面図である。この装置は、チップ部品2の突起電極3と基板4の電極5を接合するフリップチップ実装装置1であり、例えば図2のように、基板4の複数箇所にチップ部品2を実装するものである。この実装装置の要部は、チップ部品2を吸着保持するボンディングヘッド6と基板4を吸着保持する基板保持ステージ7と、認識手段である2視野カメラ8から構成されていおり、ボンディングヘッド6、基板保持ステージ7および2視野カメラ8は制御部12の指示に従い機能する。   FIG. 1 is a main part front view for explaining the basic functions of the mounting apparatus. This apparatus is a flip chip mounting apparatus 1 that joins the protruding electrodes 3 of the chip component 2 and the electrodes 5 of the substrate 4. For example, as shown in FIG. 2, the chip component 2 is mounted at a plurality of locations on the substrate 4. . The main part of this mounting apparatus is composed of a bonding head 6 that sucks and holds the chip component 2, a substrate holding stage 7 that sucks and holds the substrate 4, and a two-view camera 8 that is a recognition means. The holding stage 7 and the two-field camera 8 function according to instructions from the control unit 12.

ボンディングヘッド6は昇降可能になっており、基板保持ステージ7はX、Y、θ方向に移動可能になっていて、基板4を、チップ部品2を実装すべき場所をボンディングヘッド6の下に配置する。2視野カメラ8は、ボンディングヘッド6と基板ステージ7の間に挿入できるよう進退可能に構成されており、チップ部品2の突起電極形成面および基板の電極形成面にはそれぞれアライメントマークが記されており、2視野カメラ8で両アライメントマークを読み取り、ボンディングヘッド6または基板保持ステージ7のいずれかまたは両方を移動させて精密位置合わせを行う。精密位置合わせ後に、ボンディングヘッド6が下降して加圧するとともに必要に応じて加熱することのより、チップ部品2の突起電極3と基板4の電極5を接合するが、ボンディングヘッド6を下降する前に、基板保持ステージ7面内の位置および加圧力の関数として求まるオフセット分だけ、基板保持ステージ7の位置を微調整する。なお、オフセットを求める関数の導出方法に関しては後述する。   The bonding head 6 can be moved up and down, the substrate holding stage 7 is movable in the X, Y, and θ directions, and the substrate 4 is disposed below the bonding head 6 where the chip component 2 is to be mounted. To do. The two-field camera 8 is configured to be able to advance and retract so that it can be inserted between the bonding head 6 and the substrate stage 7, and alignment marks are respectively provided on the protruding electrode forming surface of the chip component 2 and the electrode forming surface of the substrate. Both alignment marks are read by the two-field camera 8, and either or both of the bonding head 6 and the substrate holding stage 7 are moved to perform precise alignment. After the precise positioning, the bonding head 6 is lowered and pressurized and heated as necessary to join the protruding electrode 3 of the chip component 2 and the electrode 5 of the substrate 4, but before the bonding head 6 is lowered. Further, the position of the substrate holding stage 7 is finely adjusted by an offset amount obtained as a function of the position in the surface of the substrate holding stage 7 and the applied pressure. A method for deriving the function for obtaining the offset will be described later.

この一連の実装作業が終了後、ボンディングヘッド6は上昇し、図示していないチップ吸着反転ツールにより、新たなチップ部品2がボンディングヘッド6に搬送されるとともに、基板保持ステージ7が移動して、次にチップ部品を実装すべき基板の場所がボンディングヘッドの下に配置される。この後は、先の説明と同様、2視野カメラを用いた位置合わせから接合に至る、一連の作業が行われる。   After this series of mounting operations is completed, the bonding head 6 is raised, and a new chip component 2 is transported to the bonding head 6 by a chip suction reversing tool (not shown), and the substrate holding stage 7 is moved, Next, the location of the substrate on which the chip component is to be mounted is placed under the bonding head. Thereafter, as in the previous description, a series of operations from alignment to joining using a two-field camera is performed.

また、基板4の、チップ部品2を実装すべき全ての場所への実装作業が完了した後は、基板保持ステージ7による吸着保持は解かれ、図示していない基板搬送ツールにより実装完了後の基板4は搬出されるとともに新たな基板4が搬入され、基板保持ステージ7により吸着保持される。   Further, after the mounting operation of the substrate 4 to all the locations where the chip components 2 are to be mounted is completed, the suction holding by the substrate holding stage 7 is released, and the substrate after the mounting is completed by a substrate transport tool (not shown). 4 is unloaded and a new substrate 4 is loaded and sucked and held by the substrate holding stage 7.

次に、オフセットを求める関数の導出方法について説明する。まず、関数を導出するための基礎となるデータを取得する方法を、例を用いて説明する。図3は、基板保持ステージ7面内の複数箇所(図4のA1、A2、・・・、D7、D8)において、加圧時に生じる位置ズレ量を把握する際に用いる、アライメントマークMCの記された模擬チップ部品20と、アライメントマークMBの記された模擬基板40である。まず、この模擬基板40を基板保持ステージ7で吸着保持した後、前記複数箇所いずれかの位置において、2視野カメラ8を用いて、模擬チップ部品20のアライメントマークMCと模擬基板40アライメントマークMBの位置合わせを行い、2視野カメラ8を待避させた後に、所定の加圧力を加え、模擬チップ部品20と模擬基板40の貼り合わせを透明な接着剤を用いて行う。その後、貼り合わさった状態での、模擬チップ部品20のアライメントマークMCと模擬基板40のアライメントマークMBの位置ズレ量を認識手段を用いて実測する。   Next, a method for deriving a function for obtaining an offset will be described. First, a method for acquiring data serving as a basis for deriving a function will be described using an example. FIG. 3 shows the alignment mark MC used to grasp the amount of positional deviation that occurs during pressurization at a plurality of locations (A1, A2,..., D7, D8 in FIG. 4) on the surface of the substrate holding stage 7. The simulated chip component 20 and the simulated substrate 40 on which the alignment mark MB is written. First, after the simulated substrate 40 is sucked and held by the substrate holding stage 7, the alignment mark MC of the simulated chip component 20 and the simulated substrate 40 alignment mark MB are used at any position of the plurality of locations using the two-view camera 8. After positioning and retracting the two-view camera 8, a predetermined pressure is applied, and the simulated chip component 20 and the simulated substrate 40 are bonded together using a transparent adhesive. Thereafter, the amount of positional deviation between the alignment mark MC of the simulated chip component 20 and the alignment mark MB of the simulated substrate 40 in the bonded state is measured using a recognition unit.

ここで、それぞれのアライメントマークを明瞭に認識するために、模擬チップ部品20が可視光に対して透明であることが望ましい。仮に、模擬チップ部品20が可視光に不透明なシリコン等であってもX線や赤外線を用いることにより、貼り合わせ後のアライメントマークを認識することは可能であるが、X線や赤外線を透視観測する必要があるため、装置が大がかりになってしまう。一方、模擬チップ部品20が可視光に透明であれば可視光カメラでも貼り合わせ後のアライメントマークを上側から認識することが可能であり、汎用のカメラでも高い分解能が得られる。また、2視野カメラ8を転用することも可能なので装置コストが抑えられる。   Here, in order to clearly recognize each alignment mark, it is desirable that the simulated chip component 20 is transparent to visible light. Even if the simulated chip component 20 is made of silicon or the like that is opaque to visible light, it is possible to recognize the alignment mark after bonding by using X-rays or infrared rays. Because it is necessary to do so, the device becomes a large scale. On the other hand, if the simulated chip component 20 is transparent to visible light, the alignment mark after bonding can be recognized from above even with a visible light camera, and high resolution can be obtained even with a general-purpose camera. Further, since the two-field camera 8 can be diverted, the apparatus cost can be suppressed.

実測するズレ量は、図5に示すようにX方向のズレ量ΔX、Y方向のズレ量Δ2方向成分として求め、それぞれを基板ステージ面上の位置(x、y)および加圧力との関係をデータとして記録する。なお、以上のデータ取得・記録を、基板保持ステージ7面内の複数箇所(図4のA1、A2、・・・、D7、D8)で行い、同じ複数箇所で加圧力を変えて同様な内容を新たな模擬基板40を用いて行うことにより、データ取得・記録を行い、図6に示すようなデータ群を得る。   As shown in FIG. 5, the actually measured deviation amount is obtained as a deviation amount ΔX in the X direction and a deviation amount Δ2 direction component in the Y direction, and the relationship between the position (x, y) on the substrate stage surface and the applied pressure, respectively. Record as data. The above data acquisition / recording is performed at a plurality of locations (A1, A2,..., D7, D8 in FIG. 4) on the surface of the substrate holding stage 7, and the same contents are obtained by changing the pressure at the same plurality of locations. Is performed using a new simulated substrate 40 to obtain and record data, and obtain a data group as shown in FIG.

このデータ群を用い、位置ズレ量を、基板保持ステージ7面内の位置および加圧力を変数とする近似式により求めることにより、基板保持ステージ7面内の任意の位置、任意の加圧力の際の位置ズレ量を予測することが出来る。したがって、オフセットはこの位置ズレ量を相殺するものであることから、基板保持ステージ7の任意の位置、任意の加圧力のオフセット量も求まる。すなわち、オフセットを基板保持ステージ7面内の位置および接合時の加圧力の関数として設定することが出来る。   By using this data group, the amount of positional deviation is obtained by an approximate expression using the position and pressure force on the surface of the substrate holding stage 7 as variables, so that at any position and arbitrary pressure force on the surface of the substrate holding stage 7. Can be predicted. Therefore, since the offset cancels out this positional shift amount, an arbitrary position of the substrate holding stage 7 and an offset amount of an arbitrary applied pressure can be obtained. That is, the offset can be set as a function of the position in the surface of the substrate holding stage 7 and the pressure applied during bonding.

以上のオフセット演算に関するフローチャートを図7に示すが、この一連の動作および演算を自動で実施するような機能を制御部12に組み込むことも可能である。   A flowchart relating to the above offset calculation is shown in FIG. 7, and it is also possible to incorporate a function for automatically performing this series of operations and calculations into the control unit 12.

なお、基板保持ステージ7面内の複数点の設定に関しては、その間隔が、対象とする実装装置が実装対象とするチップ部品のサイズと同等から3倍程度の範囲であることが望ましい。実際の実装作業の間隔がチップ部品より小さくなることはないので、チップ部品より小さい間隔とする必要性は低く、また、間隔が大きすぎると近似式の精度低下により、適切なオフセットが得られなくなるためである。   Regarding the setting of a plurality of points on the surface of the substrate holding stage 7, it is desirable that the interval be in the range of about the same as the size of the chip component to be mounted by the target mounting apparatus to about three times. Since the actual mounting work interval is never smaller than the chip component, it is less necessary to make the interval smaller than the chip component, and if the interval is too large, an appropriate offset cannot be obtained due to a decrease in the accuracy of the approximate expression. Because.

以上、基板保持ステージ面内の位置と加圧力からオフセットを求める実施の形態について記したが、更なる高精度実装の要望が高まることで実装温度等を因子とする実装段階での位置ずれが問題となる可能性がある。そのような場合においては、位置、加圧力の他に温度などの因子の影響についても調べ、その因子をオフセットを求める関数の変数とすることも可能である。   As described above, the embodiment for obtaining the offset from the position in the substrate holding stage surface and the applied pressure has been described. However, as the demand for further high-accuracy mounting increases, the position shift at the mounting stage due to the mounting temperature and the like is a problem. There is a possibility. In such a case, it is possible to examine the influence of factors such as temperature in addition to the position and the applied pressure, and use the factors as variables of the function for obtaining the offset.

(実施例1)
図8は本実施例1に用いた基板保持ステージ7の構造を示すものである。基板4を吸着保持する基板保持ステージ7は基板を加熱するためのステージヒータ9の上に配置されており、ステージヒータ9と架台11の間には倣い機構10を設けてある。基板保持ステージ7のXY方向への移動は、架台11が移動することによって成される。ここで、各要素のX方向×Y方向のサイズは、ステージヒータ9が260mm×130mm、基板保持ステージ7が250mm×120mmのサイズとなっており、倣い機構10は直径が114mmとなっている。この基板保持ステージ7を用いた実装では、Y方向での位置の違いによる位置ズレの違いはなく、ΔYは殆どゼロであるのに対して、X方向の位置によっては位置ズレΔXが生じることが判っていたものであり、量産前には試行錯誤によりX方向の位置毎に、X方向のオフセットを求めていたものである。そこで、この基板保持ステージ7のオフセットを関数化することを試みた。
Example 1
FIG. 8 shows the structure of the substrate holding stage 7 used in the first embodiment. A substrate holding stage 7 for sucking and holding the substrate 4 is disposed on a stage heater 9 for heating the substrate, and a copying mechanism 10 is provided between the stage heater 9 and the gantry 11. The movement of the substrate holding stage 7 in the XY directions is performed by moving the gantry 11. Here, the size of each element in the X direction × Y direction is 260 mm × 130 mm for the stage heater 9 and 250 mm × 120 mm for the substrate holding stage 7, and the copying mechanism 10 has a diameter of 114 mm. In the mounting using the substrate holding stage 7, there is no difference in position deviation due to the difference in position in the Y direction, and ΔY is almost zero, whereas a position deviation ΔX may occur depending on the position in the X direction. It was already known, and before mass production, an offset in the X direction was obtained for each position in the X direction by trial and error. Therefore, an attempt was made to functionalize the offset of the substrate holding stage 7.

図9は、その際に用いた模擬基板40であり、サイズは240mm×64mmであるが、基板保持ステージ7のY方向位置の違いにより位置ズレ量に変化が生じることがないことから、X方向の位置毎の位置ズレ量のみを求めるようにしている。図9において、6番の場所が基板保持ステージのX方向における中心であり、この点をゼロとして、左右各100mmの20mm毎の間隔で、模擬チップ部品20と模擬基板40の位置ズレ量の測定を行った。測定に際し、模擬チップ部品20および模擬基板40は透明ガラス製のものを用い、模擬チップ部品20のアライメントマークMCおよび模擬基板40のアライメントマークMBの両方を認識し易くした。なお、位置合わせ段階では、両アライメントマーク間の中心のズレ量を0.1μm以下とした。また、加圧力は50(N)、100(N)および150(N)の3条件について行った。この結果、得られた結果は図10のとおりである。この図10の結果から、加圧力を50(N)から150(N)の範囲で変化させた時の位置ズレ量が近似式で求まり、図11が得られた。   FIG. 9 shows the simulated substrate 40 used at that time, and the size is 240 mm × 64 mm. However, since the positional deviation amount does not change due to the difference in the Y-direction position of the substrate holding stage 7, FIG. Only the positional deviation amount for each position is obtained. In FIG. 9, the position No. 6 is the center in the X direction of the substrate holding stage. With this point as zero, the amount of misalignment between the simulated chip component 20 and the simulated substrate 40 is measured at intervals of 20 mm of 100 mm on each side. Went. In the measurement, the simulated chip component 20 and the simulated substrate 40 are made of transparent glass so that both the alignment mark MC of the simulated chip component 20 and the alignment mark MB of the simulated substrate 40 can be easily recognized. Note that, in the alignment step, the center misalignment between the alignment marks was set to 0.1 μm or less. The applied pressure was measured under three conditions of 50 (N), 100 (N), and 150 (N). As a result, the obtained result is as shown in FIG. From the result of FIG. 10, the amount of positional deviation when the applied pressure was changed in the range of 50 (N) to 150 (N) was obtained by an approximate expression, and FIG. 11 was obtained.

そこで、図11から得られた、加圧力120(N)時の位置ズレ量からオフセットを設定し、模擬チップ部品20と模擬基板40による貼り合わせを行ったところ、全てのポイントで位置ズレ量は0.5μm以下となることが確認出来た。   Therefore, when the offset is set from the positional deviation amount at the time of the applied pressure 120 (N) obtained from FIG. 11 and bonding is performed using the simulated chip component 20 and the simulated substrate 40, the positional deviation amount is obtained at all points. It was confirmed that the thickness was 0.5 μm or less.

本発明に係る実装方法では、これまでは生産条件毎に試行錯誤を伴って求めていたオフセットを簡易に求めることが出来、生産効率を向上させることから、チップ部品の基板への実装に高精度が要求されるあらゆる分野に適用することが出来る。   With the mounting method according to the present invention, it is possible to easily obtain an offset that has been obtained with trial and error for each production condition so far, and to improve production efficiency. It can be applied to all fields where is required.

1 フリップチップ実装装置
2 チップ部品
3 突起電極
4 基板
5 電極
6 ボンディングヘッド
7 基板保持ステージ
8 2視野カメラ
9 ステージヒータ
10 倣い機構
11 架台
12 制御部
20 模擬チップ部品
40 模擬基板
MB 模擬基板のアライメントマーク
MC 模擬チップ部品のアライメントマーク
DESCRIPTION OF SYMBOLS 1 Flip chip mounting apparatus 2 Chip component 3 Protruding electrode 4 Substrate 5 Electrode 6 Bonding head 7 Substrate holding stage 8 Two-field camera 9 Stage heater 10 Copying mechanism 11 Mount 12 Control unit 20 Simulated chip component 40 Simulated substrate MB Simulated substrate alignment mark MC Simulated chip part alignment mark

Claims (4)

チップ部品のアライメントマークと基板のアライメントマークを画像認識手段で認識してチップ部品と基板のアライメントを行った後にチップ部品を加圧して基板に実装する実装方法において、
アライメント後にチップ部品を加圧して実装する時に生じる位置ズレ量を相殺する実装オフセットを、基板を保持する基板保持ステージ面内の位置および接合時の加圧力の関数として設定することを特徴とする実装方法。
In a mounting method in which the alignment mark of the chip component and the alignment mark of the substrate are recognized by the image recognition means and the chip component and the substrate are aligned and then the chip component is pressurized and mounted on the substrate.
Mounting characterized by setting a mounting offset that offsets the amount of misalignment that occurs when chip parts are pressed and mounted after alignment as a function of the position within the surface of the substrate holding stage that holds the substrate and the pressure applied during bonding Method.
請求項1に記載の実装方法であって、基板保持ステージ面内の複数の位置における複数条件の加圧力に対する位置ズレ量を求め、その結果を基に、基板保持ステージ面内の位置および接合時の加圧力と位置ズレ量の関係を表す関数を導出することを特徴とする実装方法。 The mounting method according to claim 1, wherein a positional shift amount with respect to a plurality of conditions of applied pressure at a plurality of positions in the substrate holding stage surface is obtained, and based on the result, the position in the substrate holding stage surface and the bonding time A method for deriving a function representing the relationship between the applied pressure and the amount of displacement. 請求項2に記載の実装方法であって、基板保持ステージ面内の複数の位置における複数条件の加圧力に対する位置ズレ量を求めるに際して、アライメントマークが記された、透明なチップ部品を用いることを特徴とする実装方法。 3. The mounting method according to claim 2, wherein a transparent chip component on which an alignment mark is written is used when determining a positional shift amount with respect to a plurality of conditions of applied pressure at a plurality of positions in the substrate holding stage surface. Characteristic mounting method. チップ部品を吸着保持するボンディングヘッドと、ボンディングヘッドを上下方向に移動させる機構と、基板を載置保持する基板保持ステージと、ボンディングヘッドと基板保持ステージが相対的に水平方向及び回転方向に移動させる機構と、ボンディングヘッドと基板保持ステージとの空間に進退可能に設けられ且つヘッド側と基板保持ステージ側とを同時に撮像可能な2視野認識手段を有する実装装置であって、
請求項1から3の何れかに記載の実装方法を行う機能を備えた実装装置。
Bonding head for sucking and holding chip components, mechanism for moving the bonding head in the vertical direction, substrate holding stage for placing and holding the substrate, and bonding head and substrate holding stage relatively moving in the horizontal and rotational directions A mounting apparatus having a mechanism and a two-field recognition means provided in a space between the bonding head and the substrate holding stage so as to be able to advance and retreat and capable of simultaneously imaging the head side and the substrate holding stage side;
The mounting apparatus provided with the function to perform the mounting method in any one of Claim 1 to 3.
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