JPWO2011104786A1 - Pipeline type A / D converter and A / D conversion method, and dynamic type differential amplifier - Google Patents

Abstract

The A-type conversion circuit compares the input voltage with a plurality of threshold voltages, determines which of the plurality of segments belongs, and generates a first voltage and a second voltage across the segment to which the input voltage belongs. The A-type conversion circuit generates a third voltage by amplifying a difference between the first voltage and the input voltage with reference to a predetermined common voltage. The fourth voltage is generated by amplifying the difference between the second voltage and the input voltage with reference to the common voltage. The B-type converter circuit divides the third voltage and the fourth voltage into a plurality of segments, and determines which of the plurality of segments the common voltage belongs to. Subsequently, a fifth voltage and a sixth voltage are generated across the segment to which the common voltage belongs. The B-type conversion circuit generates the seventh voltage (the third voltage of the next stage) by amplifying the difference between the fifth voltage and the common voltage with reference to the common voltage, and the difference between the sixth voltage and the common voltage is The eighth voltage is generated by amplifying the common voltage as a reference.

Description

  The present invention relates to a pipeline type A / D converter.

A pipeline type A / D converter is used to convert an analog voltage into a digital signal. 1A to 1C are a block diagram and input / output characteristics showing a configuration of a general pipeline type A / D converter. A / D converter 1100 is provided with a unit conversion circuit _UC 1 to UC _n of the plurality connected in cascade (n stages).

The unit conversion circuits UC _{1 to} UC _n sequentially perform A / D conversion by m bits from the most significant bit MSB to the least significant bit LSB. FIG. 1B shows the configuration of the unit conversion circuit UC. The unit conversion circuit UC includes an operational amplifier OA1, a switch circuit SW, and a sub A / D converter SADC, and alternately repeats the sampling state φ0 and the differential amplification state φ1 in a time-division manner in synchronization with the clock signal. When the unit conversion circuit UC of a certain stage is in the sampling state φ0, the unit conversion circuit UC of the stage adjacent to it is in the differential amplification state φ1.

The input terminal Pi, the input voltage V _in from the preceding stage is input. The input voltage range is −V _ref to + V _ref . In sampling state .phi.0, sub A / D converter SADC compares the input voltage _{V in} and a plurality of reference voltages, and generates comparison data D1 indicating the comparison result k. In this example, it has a redundant configuration of the 6 values, i.e. about 2.5 bits, the input voltage V _in is sampled (quantized) as follows.
−V _ref <V _in <−5 / 8 × V _ref k = −3
−5 / 8 × V _ref <V _in <−3 / 8 × V _ref k = −2
−3 / 8 × V _ref <V _in <−1 / 8 × V _ref k = −1
−1 / 8 × V _ref <V _in <+ 1/8 × V _ref k = 0
+ 1/8 × V _ref <V _in <+ _3/8 × V _ref k = 1
+ _3/8 × V _ref <V _in <+ _5/8 × V _ref k = 2
+ _5/8 × V _ref <V _in <+ V _ref k = 3

Further, in the sampling state .phi.0, switch _{S 1} is turned on, the switch _{S 2} is turned to the input terminal Pi side. The switch circuit SW selects the input voltage _{V in,} is applied to one end of the input capacitor _C s1 _{-C s3.} As a result, the feedback capacitor Cf and the input capacitor _C s1 _{-C s3} is charged by the same input voltage _{V in.}

Then differential amplification status φ1 becomes the phase of the clock signal is switched, the switch S ₁ is turned off, the switch S ₂ is turned on the output terminal Po of the operational amplifier OA. The sub A / D converter SADC outputs the comparison result to the switch circuit SW. The switch circuit SW applies one of the reference voltage string + V _ref , −V _ref , and GND to one end of each of the input capacitors C _{s1 to} C _s3 according to the comparison result. As described above, the conversion value k indicating the comparison result can take 7 values between −3 and +3. When k is positive, the switch circuit SW applies the reference voltage + V _ref to the k input capacitors C _s and applies the ground voltage GND to the rest. On the contrary, when k is negative, the reference voltage −V _ref is applied to (−k) input capacitors C _s , and the ground voltage GND is applied to the rest. When k is zero, the ground voltage GND is applied to all the capacitors C _{s1 to} C _s3 .

If the capacitance values of all capacitors Cf and C _{s1 to} C _s3 are equal to C ₀ , the charge Q held at the inverting input terminal (−) of the operational amplifier OA is
Q = -4C ₀ · V _in (1)
Given in. Also, when the potential of the inverting input terminal (−) of the operational amplifier OA is vi, its output voltage is vo, and its gain is G,
(Vi−V _ref ) × k × C ₀ + (vi−vo) C ₀ = Q = −4C ₀ · V _in (2a)
vo = −G · vi (2b)

Therefore, the output voltage V _out (= vo) of the unit conversion circuit UC in the differential amplification state φ1 is given by Expression (3).
V _out = 4 (V _in −k / 4 × V _ref ) / {1+ (k + 1) / G} (3)

Assuming that G is infinite, Expression (3 ′) is obtained as the input / output characteristics of the unit conversion circuit UC.
V _out = 4 · (V _in −k × V _ref / 4) (3 ′)

FIG. 1C shows the input / output characteristics of the unit conversion circuit UC given by equation (3). A white circle indicates a reference voltage of the sub A / D converter SADC. In the figure, the black circles indicate the offset voltage in the X-axis direction given by (k × V _ref ) in the second term on the right side in equation (3 ′). That unit conversion circuit UC amplifies the input voltage V _in, the difference between the offset voltage gain 4.

The output signal _{V out} is supplied as an input voltage _{V in} of the next-stage unit conversion circuit UC. As shown in FIG. 1A, when a plurality of unit conversion circuits UC perform a pipeline operation in synchronization with a clock signal, data D1, D2,... Is output. Note that the unit conversion circuit UC at the final stage does not require differential amplification processing, and thus can be configured by only a comparator array (sub A / D converter).

JP 2006-54608 A

K. Sushihara and A. Matsuzawa, `` A 7b 450MSPS 50mW CMOS ADC in 0.3mm2, '' IEEE International Solid-State Circuits Conference, Digest of Technical, 2002, pp.170-171 Yusuke Asada, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, and Akira, `` A 6bit, 7mW, 250fJ, 700MS / s Subranging ADC '', IEEE Asian Solid-State Circuits Conference (A-SSCC), Taiwan, November 2009, 5-3, pp.141-144

The conversion accuracy of the conventional pipelined A / D converter 1100 as shown in FIG. 1 depends on the accuracy of the gain of the circuit system, and specifically, the ratio of the capacitors C _f and Cs _{1 to} Cs ₃ . It depends on the accuracy and the gain of the operational amplifier OA1. In the description so far, it is assumed that the gain G of the operational amplifier OA1 is infinite. However, the actual operational amplifier has a finite gain, and the gain decreases with the recent miniaturization of semiconductor processes. There is a tendency. The required gain G when the resolution is N bits and the conversion error is 1/4 LSB is
G (dB)> 6N + 10 (4)
It will be about. Therefore, when the resolution is 10 bits, the necessary gain G is 70 dB or more, and when the resolution is 12 bits, the necessary gain G is 82 dB or more. The gain of an operational amplifier using a miniaturized CMOS device in recent years is about 60 dB at most, and it is difficult to obtain such a high gain.

  Further, this conversion method is premised on negative feedback amplification using an operational amplifier. The negative feedback circuit is configured so that the accuracy of the circuit system is determined by the specific accuracy of the capacitance by increasing the gain of the operational amplifier. However, the negative feedback circuit is likely to cause an increase in oscillation and settling time. This is a major obstacle to speeding up the converter.

  SUMMARY An advantage of some aspects of the invention is to provide a pipeline A / D converter that does not use a negative feedback circuit.

One embodiment of the present invention relates to an A / D conversion method for converting an analog input voltage into digital data. This method performs the following processing.
1. 1. First step of comparing an input voltage with a plurality of threshold voltages to determine which of a plurality of segments belongs. 2. a second step of generating a first voltage and a second voltage across the segment to which the input voltage belongs; 3. A third step of generating a third voltage by amplifying the difference between the first voltage and the input voltage with reference to a predetermined common voltage. 4. Fourth step of generating a fourth voltage by amplifying the difference between the second voltage and the input voltage with reference to the common voltage. 5. A fifth step of dividing the third voltage and the fourth voltage into a plurality of segments and determining which of the plurality of segments the common voltage belongs to. 6. A sixth step of generating a fifth voltage and a sixth voltage across the segment to which the common voltage belongs. 7. A seventh step of generating a seventh voltage by amplifying a difference between the fifth voltage and the common voltage with reference to the common voltage. The eighth step of generating the eighth voltage by amplifying the difference between the sixth voltage and the common voltage with reference to the common voltage. The fifth step to the eighth step are repeatedly executed, and the eighth step to the fifth step. When returning to the step, the seventh voltage obtained in the previous seventh step is used as the third voltage in the next fifth step, and the eighth voltage obtained in the previous eighth step is used as the fourth voltage in the next fifth step. Use as voltage.

  According to this aspect, high-speed A / D conversion can be realized.

  In the sixth step, the fifth voltage and the sixth voltage may be generated by interpolating the third voltage and the fourth voltage, respectively.

  Each of the first voltage to the eighth voltage may be generated as a differential signal.

  In the sixth step, the fifth voltage and the sixth voltage may be generated by extrapolating the third voltage and the fourth voltage.

Another aspect of the present invention relates to a pipelined A / D converter that converts an analog input voltage into digital data. The A / D converter includes an A-type conversion circuit, at least one B-type conversion circuit, and a comparator row connected in series.
The A-type conversion circuit compares the input voltage with a plurality of threshold voltages and determines which one of the plurality of segments belongs to, and a voltage level equal to or higher than the upper limit of the segment to which the input voltage belongs A first amplifying circuit for generating a third voltage by amplifying a difference between the first voltage and an input voltage with a predetermined common voltage as a reference, and outputting the third voltage to a B-type conversion circuit at a subsequent stage; Generating a second voltage having a voltage level equal to or lower than the lower limit of the segment to which the input voltage belongs, amplifying a difference between the second voltage and the input voltage with reference to a predetermined common voltage, and generating a fourth voltage; And a second amplifier circuit for outputting to the B-type conversion circuit.
The B-type conversion circuit divides a portion between the third voltage and the fourth voltage from the previous stage into a plurality of segments, and determines a common sub-voltage belonging to the plurality of segments, a second sub A / D converter, The seventh voltage is generated by amplifying the difference between the fifth voltage and the common voltage having a voltage level equal to or higher than the upper limit of the segment to which the voltage belongs, and output as the third voltage to the B-type conversion circuit in the subsequent stage. And an eighth voltage is generated by amplifying a difference between the sixth voltage having a voltage level equal to or lower than the lower limit of the segment to which the common voltage belongs and the common voltage with reference to the common voltage. And a fourth amplifier circuit that outputs a fourth voltage to the conversion circuit. The comparator row divides the third voltage and the fourth voltage from the B-type conversion circuit in the previous stage into a plurality of segments, and determines which of the plurality of segments the common voltage belongs to.

  According to this aspect, high-speed A / D conversion can be realized.

  The first amplifier circuit applies an input voltage to a first capacitor row including a plurality of first capacitors, each of which has a first terminal connected in common, and a second terminal of the first capacitor row in a sampling state, and performs interpolation. In the amplification state, a first switch circuit that applies a reference voltage to the second terminals of the number of first capacitors according to the determination result by the first sub A / D converter in the first capacitor array, and the first capacitor array A first switch that is turned on in the sampling state and turned off in the interpolation amplification state, a common voltage is input to the first input terminal, and the second input terminal is And a first amplifier connected to the first terminal of the first capacitor row. The second amplifier circuit may be configured similarly to the first amplifier circuit.

  The third amplifier circuit and the fourth amplifier circuit may generate the fifth voltage and the sixth voltage by interpolating the third voltage and the fourth voltage.

  The third amplifier circuit includes a third capacitor array including a plurality of third capacitors, each having a first terminal connected in common, and each first terminal connected in common to the first terminal of the third capacitor array. Applying a third voltage to the second capacitor array including a plurality of fourth capacitors and the second terminal of the third capacitor array in the sampling state, and in the interpolation amplification state, the second sub-A / A third switch circuit that applies a fixed voltage to the second terminals of the number of third capacitors according to the determination result by the D converter; and a fourth voltage that is applied to the second terminal of the fourth capacitor row in the sampling state; A fourth switch circuit for applying a fixed voltage to the second terminals of the number of fourth capacitors corresponding to the determination result by the second sub A / D converter in the fourth capacitor row in the interpolation amplification state; A third switch which is provided between a first terminal and a fixed voltage terminal commonly connected to the capacitor string and the fourth capacitor string, and which is turned on in the sampling state and turned off in the interpolation amplification state; and a common to the first input terminal And a third amplifier having a voltage input and a second input terminal connected to a first terminal commonly connected to the third capacitor row and the fourth capacitor row. The fourth amplifier circuit may be configured similarly to the third amplifier circuit.

  When the third switch circuit applies a fixed voltage to the third capacitor row in the interpolation amplification state, the third switch circuit applies the third voltage from the previous stage as the fixed voltage, and the fourth switch circuit operates in the interpolation amplification state. When applying a fixed voltage to the 4-capacitor row, the offset voltage of the amplifier of the conversion circuit in the previous stage may be canceled by applying the fourth voltage from the previous stage as the fixed voltage.

  It should be noted that any combination of the above-described constituent elements and the expression of the present invention converted between methods, apparatuses, etc. are also effective as an aspect of the present invention.

  According to an aspect of the present invention, a high-speed A / D converter is provided.

1A to 1C are a block diagram and input / output characteristics showing a configuration of a general pipeline type A / D converter. It is a block diagram which shows the structure of the pipeline type A / D converter which concerns on embodiment. It is a figure explaining the function of an A type conversion circuit. It is a figure which shows the input-output characteristic of an A type conversion circuit. It is a circuit diagram which shows the structure of an A type conversion circuit. It is a figure explaining the function of a B type conversion circuit. It is a figure which shows the input / output characteristic of an A / D converter. It is a circuit diagram which shows the structure of a B-type conversion circuit. It is a circuit diagram which shows the structure of the B-type conversion circuit which concerns on a modification. It is a circuit diagram which shows the structure of the B-type conversion circuit which concerns on a 2nd modification. 11A and 11B are diagrams illustrating the operation of the B-type conversion circuit of FIG. FIGS. 12A and 12B are diagrams illustrating input / output characteristics of the A-type conversion circuit and the B-type conversion circuit when a differential amplifier is used. It is a circuit diagram which shows a part of structure of the B-type conversion circuit which concerns on a 3rd modification. It is a figure which shows the input-output characteristic of the B-type conversion circuit of FIG. It is a circuit diagram which shows the structure of a dynamic type differential amplifier. FIG. 16 is a waveform diagram showing an operation of the dynamic differential amplifier of FIG. 15. It is a circuit diagram which shows the structure of the amplifier which concerns on a comparison technique. 18A and 18B are circuit diagrams showing specific examples of the dynamic differential amplifier of FIG. FIGS. 19A and 19B are circuit diagrams showing another specific example of the dynamic differential amplifier. FIG. 16 is a circuit diagram showing a modification of the dynamic differential amplifier of FIG. 15.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

FIG. 2 is a block diagram showing a configuration of the pipeline type A / D converter 100 according to the embodiment. The A / D converter 100 converts the analog input voltage VI into digital data DOUT. Assume that the input voltage range of the analog input signal VI is −V _ref to + V _ref .

The A / D converter 100 includes an A-type conversion circuit UCA connected in series, at least one B-type conversion circuit UCB _{1 to} UCB _n, and a comparator array (comparator array) CA. The last-stage comparator array CA is configured as a part of the (n + 1) -th stage B-type conversion circuit UCB _{n + 1} in order to perform the same processing as the second sub-A / D converter 20 of the B-type conversion circuit described later. Alternatively, it may be configured as a single comparator row.

The conversion circuits UCA, UCB _{1 to} UCB _n and the comparator string CA sequentially perform A / D conversion by m bits from the most significant bit MSB to the least significant bit LSB.

Each of the conversion circuits UCA, UCB _{1 to} UCB _n alternately repeats the sampling state φ0 and the differential amplification state (interpolation amplification state) φ1 in a time division manner in synchronization with the clock signal. When the conversion circuit of a certain stage is in the sampling state φ0, the conversion circuit of the stage adjacent thereto is in the differential amplification state (interpolation amplification state) φ1.

(A type conversion circuit)
First, the A-type conversion circuit UCA provided in the first stage will be described.
FIG. 3 is a diagram illustrating the function of the A-type conversion circuit UCA. The A-type conversion circuit UCA receives an input signal VI and a reference voltage string VREF (for example, three voltages of + V _ref , −V _ref , and GND = 0V). The A-type conversion circuit UCA repeats the sampling state φ0 and the differential amplification state φ1 alternately.

In the sampling state φ0, the A-type conversion circuit UCA divides the interval between the reference voltages −V _ref and V _ref into a plurality of segments SEG, and determines to which segment the input signal VI belongs (sampling).

Specifically, the A-type conversion circuit UCA compares the input voltage VI with a plurality of threshold voltage strings Vth arranged at an interval ΔV (= V _ref / M) between the reference voltages −V _ref and V _ref. Then, the conversion data D1 indicating the comparison result is output. The conversion data D1 indicates the segment number k to which the input voltage VI belongs. FIG. 3 shows a case where the input voltage VI belongs to the segment SEG ₀ .

Subsequently, when the phase of the clock signal is switched, the A-type conversion circuit UCA enters the differential amplification state φ1. A type converter UCA is two intermediate voltage _Vm a in accordance with the input voltage VI, to generate the Vm _b.
The first intermediate voltage Vm _a is obtained by using _a predetermined common voltage Vc and an integer parameter ka.
_{Vm a = Vc + k a ×} V ref / M ... (5a)
And a voltage higher than the upper threshold voltage of the segment SEG _k to which the input voltage VI belongs.
The second intermediate voltage Vm _b, using an integer parameter _{k b,
Vm a = Vc + k b ×} V ref / M ... (5b)
And a voltage lower than the lower threshold voltage of the segment SEG _k to which the input voltage VI belongs. That is, the intermediate voltages Vm _a and Vm _b are determined so as to sandwich the segment SEG _k .

The intermediate voltages Vm _a and Vm _b are desirably offset with respect to the threshold voltage between the segments SEG. The offset amount is preferably V _ref / (2M).

Then, the A-type conversion circuit UCA amplifies the difference between the input voltage VI and the intermediate voltage Vma with _a gain G with reference to the common voltage Vc to generate the first output voltage Va. Similarly, the difference between the input voltage VI and the intermediate voltage Vm _b, to generate the second output voltage Vb is amplified by a gain G based on the common voltage Vc. The first output voltage Va and the second output voltage Vb are output from the first output terminal Po _a and the second output terminal Po _b , respectively.
Va = G × (Vm _a −VI−Vc) + Vc
_{= G × (k a × V} ref / M-VI) + Vc ... (6a)
_{Vb = G × (Vm b -VI} -Vc) + Vc
_{= G × (k b × V} ref / M-VI) + Vc ... (6b)

That formula (6a), differential amplification processing represented by (6b) is shifted (offset) input voltage VI to the common voltage Vc, the voltage Va obtained by amplifying the potential difference between the intermediate voltage Vm _a and the input voltage VI, the intermediate It can be understood as the process of generating a voltage Vb obtained by amplifying the potential difference between the voltage Vm _b and the input voltage VI.

FIG. 4 is a diagram showing input / output characteristics of the A-type conversion circuit UCA. In the following description, the common voltage Vc will be described as the ground voltage GND (= 0V) for the sake of simplicity of explanation and easy understanding.
The first output voltage Va and the second output voltage Vb are given by the following equations.
Va = G × (VI−k _a / M · V _ref ) (7a)
_{Vb = G × (VI-k} b / M · V ref) ... (7b)
k _a and k _b are integer parameters determined so that the two straight lines Va and Vb sandwich the voltage range of the input voltage VI, respectively. Expression (7a) represents a straight line with _a slope of G and an x-intercept of (k _a / M · V _ref ), and expression (7b) represents a slope of G and the x-intercept of (k _b / M · V _ref ). Represents a straight line. Hereinafter, (k _a / M · V _ref ) is referred to as a first offset voltage, and (k _b / M · V _ref ) is referred to as a second offset voltage.

The numerical values k _a and k _b may be determined as follows using an integer parameter α (α ≧ 1).
k _a = (k + α)
k _b = (k−α)
As apparent from FIG. 4 and equations (7a) and (7b), the difference (Vb−Va) between the two output voltages Va and Vb is
_{Vb-Va = G × (k} a -k b) / M · V ref = G × 2α / M · V ref ... (8)
Thus, it is constant regardless of the value of the input voltage VI. That is, the input voltage range of the subsequent circuit is also substantially constant regardless of the input voltage VI. For example, Vb−Va = V _ref (8a)
It is preferable to determine the values of α, M, and G so that, that is, G × 2α / M = 1.

FIG. 4 shows a case where M = 4 and G = 2, and the threshold voltage Vth is indicated by a white circle. For example, in the sampling state φ0, when the input voltage VI is determined to be k = 0, that is, −V _ref / 8 <VI <V _ref / 8,
Va = G × (VI−1 / M · V _ref ) (9a)
Vb = G × (VI + 1 / M · V _ref ) (9b)
The output voltages Va and Vb given by are output. Here, α = 1.

Next, a specific configuration example of the A-type conversion circuit UCA will be described.
FIG. 5 is a circuit diagram showing a configuration of the A-type conversion circuit UCA. The A-type conversion circuit UCA includes a first sub A / D converter 10, a first amplifier circuit 11a, and a second amplifier circuit 11b.

The first sub A / D converter 10 compares the input voltage VI with the threshold voltage string Vth in the sampling state φ0, determines which of the plurality of segments the input voltage Vi belongs to, and a conversion indicating the result Data D1 is generated. For example, the threshold voltage string Vth is
Vth _j = V _ref / (2M) + j × V _ref / M (10)
You may decide to satisfy | fill. Here, j is an integer taking a range of -M to M.

The input signal VI is sampled by the first sub A / D converter 10 as follows.
−V _ref <VI <−5 / 8 × V _ref k = −3
−5 / 8 × V _ref <VI <−3 / 8 × V _ref k = −2
−3 / 8 × V _ref <VI <−1 / 8 × V _ref k = −1
−1 / 8 × V _ref <VI <+ 1/8 × V _ref k = 0
+ 1/8 × V _ref <VI <+ _3/8 × V _ref k = 1
+ _3/8 × V _ref <VI <+ _5/8 × V _ref k = 2
+ _5/8 × V _ref <VI <+ V _ref k = 3

The configuration of the first sub A / D converter 10 is not particularly limited, and a known technique or a technique that can be used in the future may be used. For example, the comparators disclosed in Non-Patent Documents 1 and 2 proposed by the present inventor can be suitably used as the first sub A / D converter 10 of the present invention. Alternatively, the threshold voltage Vth may be generated by resistance-dividing the reference voltage string -V _ref , GND, V _ref and voltage comparison may be performed using a comparator array (comparator string).

The first amplifier circuit 11a generates the first voltage Vm _a having an upper limit or more voltage levels of the segment the input voltage VI belongs, the difference between the first voltage Vm _a and the input voltage VI as a reference to a predetermined common voltage Vc Amplification is performed to generate the third voltage Va.

The second amplifier circuit 11b generates the second voltage Vm _b having a voltage level below the lower limit of the segment the input voltage VI belongs, the difference between the second voltage Vm _b and the input voltage VI as a reference to a predetermined common voltage Vc Amplify to generate the third voltage Vb. The first voltage Vm _a second voltage Vm _b is sandwich segments input voltage VI belongs.

The first amplifier circuit 11a includes a first switch circuit 12a, a first amplifier 14a, first capacitor rows C _{a1 to} C _aM , and a first switch S _1a . Similarly, the second amplifier circuit 11b includes a second switch circuit 12b, a second amplifier 14b, second capacitor rows C _{b1 to} C _bM , and a second switch S _1b .

First, the first amplifier circuit 11a will be described. The first amplifier 14a is an inverting amplifier, and its gain is (−G). When the common voltage Vc (ground voltage GND) is applied to the non-inverting input terminal of the first amplifier 14a and the voltage of the inverting input terminal is Vi, the output voltage Va is
Va = −G × Vi (11)
It becomes.

The first switch _S1a is provided between the inverting input terminal of the first amplifier 14a and a fixed voltage terminal (ground terminal). The first switch S _1a is turned on in the sampling state .phi.0, off the differential amplifier state .phi.1.

One end (first terminal) of each of the first capacitor arrays C _{a1 to} C _aM is connected in common with the inverting input terminal of the first amplifier 14a. The capacitance values of the capacitors C _{a1 to} C _aM are assumed to be C ₀ equally.

The first switch circuit 12a is supplied with a comparison result by the first sub A / D converter 10, that is, conversion data D1 indicating a value k, or a control signal corresponding thereto. The first switch circuit 12a is a switch matrix including a plurality of switches therein, and the other end (second terminal) of each of the first capacitor columns C _{a1 to} C _aM is set in accordance with the value k of the conversion data D1. Any one of the input voltage VI, the reference voltage V _ref , GND, and −V _ref is selectively applied.

Specifically, in the sampling state φ0, the first switch circuit 12a applies the input voltage VI to the second terminals of all the capacitors C _{a1 to} C _aM . At this time, since the first switch S _1a is on, the capacitors C _{a1 to} C _aM are charged by the input voltage VI, and the total amount Q of charges stored in them is
Q = -M ・ C ₀・ VI (12)
It becomes.

In the differential amplification state φ1, the first switch circuit 12a applies the reference voltage V _ref to the second terminals of j capacitors among the capacitors C _{a1 to} C _aM , and the ground voltage GND to the second terminals of the remaining capacitors. Is applied. The number j is determined according to the value k. At this time, when the potential of the inverting input terminal of the first amplifier 14a is vi, the following formula (13) is established according to the conservation law of charge.
j · C ₀ · (VI−V _ref ) + (M−j) · C ₀ · VI = Q = −M · C ₀ · VI (13)

When formula (13) is arranged,
vi = − (VI + j · V _ref / M) (14)
Get. From Expressions (11) and (14), the first output voltage Va is given by Expression (15).
Va = −G × Vi = G × (VI + j · V _ref / M) (15)

When the first switch circuit 12a applies the reference voltage −V _ref to the second terminals of the j capacitors and applies the ground voltage GND to the second terminals of the remaining capacitors, the first output voltage Va is given by the formula ( 16).
Va = −G × Vi = G × (VI−j · V _ref / M) (16)

That is, according to the A-type conversion circuit UCA of FIG. 5, the first output voltage Va that satisfies the above-described equation (7a) can be generated. When k _a = k + 1 in equation (7a), the state of the first switch circuit 12a is as follows.
(1) When k ≧ 0 The first switch circuit 12a applies −V _ref to (k + 1) capacitors and applies the ground voltage GND to the remaining M− (k + 1) capacitors.
(2) When k = −1 The first switch circuit 12a applies the ground voltage GND to all M capacitors.
(3) When k ≦ −2 The first switch circuit 12a applies the reference voltage V _ref to (−k + 1) capacitors and applies the ground voltage GND to the remaining M − (− k + 1) capacitors. .

When generalized as k _a = k + α, the state of the first switch circuit 12a is as follows.
(1) _{k a} first switch circuit 12a when ≧ 1 is a _{-V ref} is applied to the _{k a} number of capacitors, applying a ground voltage GND to the remaining M- _{(k a)} number of capacitors.
(2) When k _a = 0 The first switch circuit 12a applies the ground voltage GND to all M capacitors.
(3) _{k a} ≦ -1 first switch circuit 12a when the reference voltage _{V ref} is applied to the _{k a} number of capacitors, applying a ground voltage GND to the remaining M- _{(k a)} number of capacitors.

The second switch circuit 12b, a second amplifier 14b, capacitor _C b1 _{-C bM,} circuit group including a second switch _{S 1b} generates the second output voltage Vb, the circuit group for generating a first output voltage Va as described above And generating a second output voltage Vb that satisfies the equation (7b).

In the equation (7b), when k _b = k−1, the state of the second switch circuit 12b is as follows.
(1) When k ≧ 2, the second switch circuit 12b applies −V _ref to (k−1) capacitors and applies the ground voltage GND to the remaining M− (k−1) capacitors. .
(2) When k = 1 The second switch circuit 12b applies the ground voltage GND to all M capacitors.
(3) k ≦ 0
The second switch circuit 12b applies the reference voltage V _ref to (−k + 1) capacitors and applies the ground voltage GND to the remaining M − (− k + 1) capacitors.

When generalized as k _b = k−α, the state of the second switch circuit 12b is as follows.
(1) _{k b} second switch circuit 12b when ≧ 1 is a _{-V ref} is applied to the _{k b} pieces of capacitors, applying a ground voltage GND to the remaining M- _{(k b)} pieces of capacitors.
(2) When k _b = 0 The second switch circuit 12b applies the ground voltage GND to all M capacitors.
(3) _{k b} ≦ -1 second switch circuit 12b when the reference voltage _{V ref} is applied to the _{k b} pieces of capacitors, applying a ground voltage GND to the remaining M- _{(k b)} pieces of capacitors.

  The above is the configuration of the A-type conversion circuit UCA. When the common voltage Vc is different from the ground voltage GND, the ground terminal in the figure may be replaced with the common voltage terminal.

(B type conversion circuit)
The B type conversion circuit UCB receives the first input voltage (third voltage) Vi _a and the second input voltage (fourth voltage) Vi _b from the previous A type conversion circuit UCA or B type conversion circuit UCB. In the following description, for ease of understanding, it is assumed that the preceding stage is an A-type conversion circuit UCA.

  First, the function of the B-type conversion circuit UCB will be described. The B-type conversion circuit UCB repeats the sampling state φ0 and the interpolation amplification state φ1 alternately. FIG. 6 is a diagram for explaining the function of the B-type conversion circuit UCB. FIG. 7 is a diagram showing input / output characteristics of the A / D converter 100.

As described above, the input voltages Vi _a and Vi _b generated by the preceding A-type conversion circuit UCA are voltage-converted so that the input voltage VI matches the common voltage Vc. Therefore, the B-type conversion circuit UCB divides the two input voltages Vi _a and Vi _b into a plurality of segments SEG _{1 to} SEG ₇ in the sampling state φ0, and the common voltage Vc (GND) is divided into any segment SEG _j . Determine if it belongs. The interval between the segments SEG is set equal to the following ΔV.
ΔV = (Vi _b −Vi _a ) / L (17)
L is an integer of 2 or more. As described above, since the difference between the two voltages Vi _a (Va) and Vi _b (Vb) from the previous stage is given by equation (8), the interval ΔV of the segment SEG is
ΔV = G × 2α / M · V _ref / L (18)
And is proportional to the original reference voltage V _ref . When equation (8a) holds,
ΔV = V _ref / L (18a)
It is.

FIG. 6 shows a case where L = 8. The B-type conversion circuit UCB does not use the reference voltages V _ref and -V _ref from the outside, but performs sampling (quantization) using the input voltages Vi _a and Vi _b from the previous stage. This is one of the features of the circuit UCB.

The B-type conversion circuit UCB outputs conversion data D2 indicating a value j when the common voltage Vc (GND) belongs to the j-th segment SEG _j . FIG. 6 shows a state in which the ground voltage GND belongs to the j = 4th segment SEG ₄ .

Sampling in the B-type conversion circuit UCB is performed when the two offset voltages (k _a × V _ref / M) and (k _b × V _ref / M) obtained in the previous stage are divided into a plurality of segments. This is equivalent to determining which segment the input voltage VI belongs to.

Subsequently, when the phase of the clock signal is switched, the B-type conversion circuit UCB enters the interpolation amplification state φ1, and the seventh voltage (first output voltage) Va _o , the eighth voltage (equation (19a) to (19d)) and it outputs a second output voltage) Vb _o.
Vo _a = −H × Vm _a
Vm _a = {(L−j _a ) · Vi _a + j _a · Vi _b )} / L (19a)
Vo _b = −H × Vm _b
Vm _b = {(L−j _b ) · Vi _a + j _b · Vi _b )} / L (19b)

j _a and j _b are integers determined according to the conversion value j. For example, the numerical values j _a and j _b may be determined as follows using an integer parameter β (β ≧ 1).
j _a = (j−β) (20a)
j _b = (j + β) (20b)
Specifically, β = 1 may be set.

A fifth voltage (referred to as a first intermediate voltage) Vm _a appearing in the equation (19a) is a voltage that internally divides the two input voltages Vi _a and Vi _b into j _a : (L−j _a ). The (referred to as a second intermediate voltage) sixth voltage appearing in equation (19b) Vm _b are the two input voltages Vi _a and Vi _b, j b: a voltage obtained by internally dividing the _{(L-j b).}

The B-type conversion circuit UCB determines the internal dividing points j _a and j _b so that the two intermediate voltages Vm _a and Vm _b sandwich the segment SEG _j to which the common voltage Vc (GND) belongs. The B-type conversion circuit UCB generates output voltages Vo _a and Vo _b by inverting and amplifying the two intermediate voltages Vm _a and Vm _b with _a gain (−H) with respect to the common voltage Vc. FIG. 6 shows a case where H = 4.

Focusing on two output differential voltage Vo _a and Vo _b, equation (19a), the following equation holds from (19b) (21).
_{Vo b -Vo b = -H × {} (j a -j b) · Va i + (j b -j a) Vb i} / L ... (21)
If the expressions (20a) and (20b) are substituted into the expression (21), the expression (22) is obtained.
_{Vb o -Va o = -H × {} -2β · (Vb i -Va i)} / L ... (22)
Substituting equation (8) into equation (22) yields equation (23).
_{Vb o -Va o = -H × {} -2β · G × 2α / M · V ref} / L ... (23)

When β = 1, H = 4, G × 2α / M = 1, and L = 8,
Vo _b -Vo _a = _{V ref}
Thus, the input voltage range for the B-type conversion circuit UCB in the subsequent stage is constant.

  The B-type conversion circuit UCB in the second and subsequent stages repeats the same processing. As a result, high resolution A / D conversion can be performed by pipeline processing.

  The above is the function of the B-type conversion circuit UCB. Next, the configuration of the B-type conversion circuit UCB for realizing this function will be described. FIG. 8 is a circuit diagram showing a configuration of the B-type conversion circuit UCB.

The B-type conversion circuit UCB generates a second sub A / D converter 20, _a third amplifier circuit 21a that generates _a seventh voltage (first output voltage) Vo _a, and an eighth voltage (second output voltage) Vo _b . A fourth amplifier circuit 21b is provided.

The second sub-A / D converter 20, the sampling state .phi.0, divided negative input voltage (fifth voltage) Vi _a and positive input voltage (sixth voltage) Vi _b into a plurality of segments _SEG 0 _{~SEG 8} Then, it is determined to which segment SEG _j the common voltage Vc (GND) belongs. The second sub A / D converter 20 outputs the conversion data D2 indicating the value j when the common voltage Vc (GND) belongs to the j-th segment SEG _j .

The configuration of the second sub A / D converter 20 is not particularly limited, and a known technique or a technique that can be used in the future may be used. The second sub A / D converter 20 generates a plurality of threshold voltages Vth _{1 to} Vth ₈ by dividing the two input voltages Vi _a and Vi _b as shown in FIG. Sampling may be performed in comparison with threshold voltages Vth _{1 to} Vth ₈ . In this case, the second sub A / D converter 20 can be configured by a comparator array (comparator array). As the second sub A / D converter 20, the comparators described in Non-Patent Documents 1 and 2 proposed by the present inventor can be used.

Third amplifier circuit 21a, the difference between the fifth voltage Vm _a and the common voltage Vc having an upper limit or more voltage levels of the segment to which a common voltage Vc belongs, a seventh voltage Vo _a by amplifying the common voltage Vc as the reference Generate.

Similarly fourth amplifier circuit 21b, a difference between the sixth voltage Vm _b and the common voltage Vc having a voltage level below the lower limit of segments common voltage Vc belongs, eighth voltage Vo by amplifying the common voltage Vc as the reference _b is generated.
The seventh voltage Vo _a and the eighth voltage Vo _b become the third voltage Vi _a and the fourth voltage Vi _b in the subsequent stage, respectively.

Focusing on the third amplifier circuit 21a, the configuration will be described.
Third amplifier circuit 21a, the third switch circuit _{22 aa,} the fourth switch circuit _{22 ab,} third amplifier 24a, the third capacitor column _C aa1 _{-C AAL,} the fourth capacitor column _C ab1 _{-C Abl,} the third switch S _1a is included. Fourth amplifier circuit 21b, the fifth switch circuit _{22 ba,} the sixth switch circuit _{22 bb,} fourth amplifier 24b, the fifth capacitor column _C ba1 _{-C BAL,} sixth capacitor column _C bb1 _{-C bBL,} the fourth switch S _1b is included. The third amplifier circuit 21a and the fourth amplifier circuit 21b are configured similarly.

The third amplifier 24a is an inverting amplifier, and each gain is (-H).
The third switch _S1a is provided between the inverting input terminal of the third amplifier 24a and the fixed voltage terminal (ground terminal). The third switch S _1a is turned on in the sampling state .phi.0, off the interpolation amplification status .phi.1.

Third capacitor column _C aa1 _{-C AAL,} the fourth capacitor column _C ab1 _{-C Abl} each end (first terminal) is connected in common with the inverting input terminal of the third amplifier 24a. Capacitor _C aa1 _{-C AAL,} the capacitance value of C ab1 _{-C Abl} is assumed to be equally _{C 0.}

The third switch circuit _22aa and the fourth switch circuit _22ab are _supplied with the sampling result by the first sub A / D converter 10, that is, the conversion data D indicating the value j, or a control signal corresponding thereto. The third switch circuit 22 _aa and the fourth switch circuit 22 _ab are a switch matrix including a plurality of switches therein.

In sampling state .phi.0, the third switch circuit _{22 aa,} the third capacitor column _C aa1 _{-C AAL} second ends (second terminal) connected to the first input terminal Pi _a, the fourth switch circuit _{22 ab} is The other end (second terminal) of each of the fourth capacitor rows C _{ab1 to} C _abM is connected to the second input terminal Pi _b . As a result, the third capacitor string C _aa is charged with the first input voltage Vi _a , and the fourth capacitor string C _ab is charged with the second input voltage Vi _b .

The third switch circuit _{22 aa} is connected in the interpolation amplification status .phi.1, while the L third capacitor column _{C aa1 ~C aaL (L-j} a) number of the fixed voltage terminal of the second terminal (ground terminal) Open or short-circuit the remaining j _a capacitors.
The fourth switching circuit _{22 ab} is connected in the interpolation amplification status .phi.1, a _{j a} number of second terminals of the L-number of the fourth capacitor column _C ab1 _{-C Abl} a fixed voltage terminal (ground terminal _{P GND),} the remaining (L−j _a ) capacitors are opened or short-circuited. At this time, the charge Q at the inverting input terminal of the third amplifier 24a is
_{Q = -C 0 · Vi a ·} (L-j a) -C 0 · Vi b · j a ... (24a)
It becomes. The capacitance Ctot at this time is
Ctot = L · C ₀ (25)
Since it is, the potential Vm _a at the inverting input terminal of the third amplifier 24a is
Vm _a = Q / Ctot = {(L−j _a ) · Vi _a + j _a · Vi _b } / L (26a)
It can be seen that this is consistent with the equation (19a).

The third amplifier 24a inverts amplifies the potential Vm _a inverting input terminal with a gain (-H), and outputs a first output voltage Vo _a from the first output terminal Po _a.
Vo _a = (− H) × Vm _a (27)

The fourth amplifier circuit 21b will be described. In sampling state .phi.0, the fifth switch circuit _{22 ba} includes a fifth capacitor column _C ba1 _{-C BAL} second ends (second terminal) connected to the first input terminal Pi _a, the sixth switch circuit _{22 bb} is The other end (second terminal) of each of the sixth capacitor rows C _{bb1 to} C _bbL is connected to the second input terminal Pi _b . As a result, the fifth capacitor column _{C ba} is charged with the first input voltage Vi _a, sixth capacitor column _{C bb} is charged by the second input voltage Vi _b.

In the interpolation amplification state φ1, the fifth switch circuit 22 _ba uses (L−j _b ) second terminals of the L fifth capacitor arrays C _{ba1 to} C _baL as fixed voltage terminals (ground terminals P _GND ). connect open the remaining j _b-number of capacitors or short-circuited.
The sixth switch circuit 22 _bb connects j _b second terminals of the L sixth capacitor rows C _{bb1 to} C _bbL to the fixed voltage terminal (ground terminal P _GND ) in the interpolation amplification state φ1, and the rest (L−j _b ) capacitors are opened or short-circuited. At this time, the charge Q at the inverting input terminal of the fourth amplifier 24b is
_{Q = -C 0 · Vi a ·} (L-j b) -C 0 · Vi b · j b ... (24b)
It becomes. Potential Vm _b of the inverting input terminal of the third amplifier 24a is
Vm _b = Q / Ctot = {(L−j _b ) · Vi _a + j _b · Vi _b } / L (26b)
It can be seen that this is consistent with the equation (19b). The above is the configuration of the B-type conversion circuit UCB.

  According to the A / D converter 100 according to the embodiment, it is sufficient that the gains G and H of the amplifiers of the A-type conversion circuit UCA and the B-type conversion circuit UCB are about 2 to 8 times, and are as strict as the conventional ones. High gain accuracy is not required. Therefore, an open-loop type broadband amplifier that does not use negative feedback can be used. When a negative feedback system is used, it is necessary to give sufficient consideration to the stability (oscillation) of the circuit, so that the difficulty of design increases, and problems that occur when the settling time becomes long occur. Since the A / D converter 100 can be configured as an open loop type, such a problem can be solved, and a high-speed and high-accuracy A / D converter can be easily obtained even by using a fine CMOS technology. Can be realized.

  Needless to say, if the problem associated with the negative feedback circuit can be solved, the A / D converter 100 according to the embodiment may use a negative feedback amplifier.

  Hereinafter, modifications of the A / D converter 100 will be described.

(First modification)
FIG. 9 is a circuit diagram showing a configuration of a B-type conversion circuit according to a modification. As described above, in the A / D converter 100 according to the embodiment, the accuracy of the gain required for the amplifier may be lower than that of the conventional one, but the third amplifier 24a and the fourth amplifier 24b belonging to the same conversion circuit are not required. The relative accuracy of the gain H is required to some extent. It is well known that such relative accuracy can usually be achieved by using integrated circuit technology (eg, pairing of corresponding elements). When higher relative accuracy is required, the circuit of FIG. 9 is effective.

  The B-type conversion circuit UCB of FIG. 9 further includes a gain adjustment circuit 26 in addition to the B-type conversion circuit UCB of FIG. The third amplifier 24a and the fourth amplifier 24b are variable gain amplifiers, and the gain adjustment circuit 26 digitally adjusts the gains H of the third amplifier 24a and the fourth amplifier 24b to reduce linearity errors.

In addition to or in place of adjustment by the gain adjustment circuit 26, a technique of performing differential amplification processing while swapping the third amplifier 24a and the fourth amplifier 24b is also effective. The input switches 28a and 28b switch the input voltages Vi _a and Vi _b to the two input terminals Pi _a and Pi _b of the B-type conversion circuit UCB and output them. Similarly, the output switches 29a and 29b switch the voltage from the two output terminals Po _a and Po _b of the B-type conversion circuit UCB between the two output terminals Po _a ′ and Po _b ′, and output them.

  If the amplification factors of the third amplifier 24a and the fourth amplifier 24b are the same, the conversion characteristics match even if the input / output terminals are swapped. When a mismatch occurs in the amplification factor, the conversion characteristics can be matched by combining with the gain adjustment circuit 26.

(Second modification)
By the way, in the description so far, it has been assumed that the offset voltage of the amplifier is zero. However, since an actual amplifier has an offset voltage by a certain amount and degrades accuracy, a countermeasure is necessary. Therefore, in the second modification, the problem of the offset voltage is solved by devising the switch operation of the amplifier.

FIG. 10 is a circuit diagram showing a configuration of a B-type conversion circuit according to the second modification. The switch circuits 22 _aa , 22 _ab , 22 _ba , and 22 _bb in FIG. 8 have a configuration in which the ground voltage GND is applied to the capacitor rows C _aa , C _ab , C _ba , and C _bb . On the other hand, the switch circuits 22 _aa , 22 _ab , 22 _ba , and 22 _{bb in} FIG. 10 apply the input voltages Vi _a and Vi _b from the previous stage to the capacitor arrays C _aa , C _ab , C _ba , and C _bb .

  11A and 11B are diagrams illustrating the operation of the B-type conversion circuit of FIG. FIG. 11A shows the sampling state φ0, and FIG. 11B shows the interpolation amplification state φ1.

Reference is made to FIG. When the noted B-type conversion circuit UCB _i is in the sampling state φ0, the previous stage is the interpolation amplification state φ1, and the previous stage switches _S1a and _S1b are off. When the offset voltages V _{off — a} and V off — b exist in the third amplifier 24 a (14 a) and the fourth amplifier 24 b (14 b) in the _previous stage, the signal components V _{sig_a} and V _{sig_b} are included in the voltages Vi _a and Vi _b from the _{previous stage.} The offset voltages V _{off — a} and V off — _b are superimposed on each other. In the B-type conversion circuit UCB _i , the capacitor string is _charged with (V _{sig_a} + V _{off_a} ) and (V _{sig_b} + V _{off_b} ). The charge accumulated at node x is
_{Q x = - (V sig_a +} V off_a) · C 0 · (L-j) - (V sig_b + V off_b) · C 0 · j ... (27)

Subsequently, the noted B-type conversion circuit UCB _i transitions to the interpolation amplification state φ1. At this time, the previous conversion circuit is in the sampling state, and the switches S _1a and S _1b are turned on. At this time, the input voltages Vi _a and Vi _b of the B-type conversion circuit UCB _i become the offset voltages V _{off_a} and V _{off_b} , respectively. In the interpolation amplification state φ1 shown in FIG. 11B, the following relational expression (28) is established. V _x indicates the voltage of the node x.
_{(V x -V off_a) · C} 0 · (L-j) + (V x + V off_b) · C 0 · j = Q x
=-(V _{sig_a} + V _{off_a} ) · C ₀ · (L−j) − (V _{sig_b} + V _{off_b} ) · C ₀ · j (28)

Therefore,
_{(-V off_a) · C 0 ·} (L-j) + (V x -V off_b) · C 0 · j = Q x
V _x = − {V _{sig_a} · (L−j) + V _{sig_b} · j} / L (29)
_Thus , the influence of the offset voltages V _{off — a} and V off — _b is removed, and highly accurate A / D conversion can be realized.

(Third Modification)
So far, embodiments using single-ended amplifiers have been described, but those skilled in the art will appreciate that differential amplifiers can be used.
FIGS. 12A and 12B are diagrams illustrating input / output characteristics of the A-type conversion circuit and the B-type conversion circuit when a differential amplifier is used.

  When a differential circuit is used, an inverted signal centered on the common voltage Vc is obtained. Therefore, in addition to the internal division method (interpolation interpolation) described in the embodiment, an external division method (extrapolation interpolation) is used. Is possible. FIG. 13 is a circuit diagram showing a part of the configuration of the B-type conversion circuit according to the third modification. FIG. 13 shows only the third amplifier circuit 21a on the amplifier a side. FIG. 14 is a diagram showing input / output characteristics of the B-type conversion circuit of FIG.

In the configuration of FIG. 8, only the straight lines V _{in_p} inside the straight lines V _ap and V _bp shown by bold lines can be generated by the internal division method (interpolation). On the other hand, in the configuration of FIG. 13, a straight line V _{ex_p} outside the straight lines V _ap and V _bp can be generated.

The B-type conversion circuit UCB in FIG. 13 receives differential first input voltages Vi _ap and Vi _an and second input voltages Vi _bp and Vi _bn . The third amplifier circuit 21a of the B-type conversion circuit UCB includes a second sub A / D converter 20, third switch circuits 22 _ap and 22 _an , a third amplifier 24 a, capacitor rows C _ap and C _an , and a switch S _1a . .

The switch _S1a is provided between the input terminals of the third amplifier 24a.
Capacitor column _{C ap} includes third capacitor column _C aa1 _{-C AAL,} the fourth capacitor column _C ab1 _{-C Abl.} The same applies to the capacitor row _Can .

The third switch circuits 22 _ap and 22 _an are matrix switches, and charge the capacitor arrays C _ap and C _an according to the control signal from the second sub A / D converter 20.

When the voltage is generated by the internal division method, in the sampling state φ0, the third switch circuit 22 _ap receives the normal rotation input voltage V _ap for the capacitor column C _aa and the normal rotation input for the capacitor column C _ab . The voltage V _bp may be applied. The third switch circuit 22 _an may apply the inverted input voltage V _an to the capacitor column C _ba and the inverted input voltage V _bn to the capacitor column C _bb . This is the same as in FIG. V in — _p and V in — _n can be generated by the internal division method.
V in — _p = {(L−j) V _ap + j · V _bp } / L (30p)
V in — _n = {(L−j) V _an + j · V _bn } / L (30n)

When the voltage is generated by the external division method, in the sampling state φ0, the third switch circuit 22 _ap outputs the normal input voltage Vap with respect to the capacitor column C _{aa and the} inverted input voltage V with respect to the capacitor column C _ab . _What is necessary is _just to apply _bn .
In the interpolation amplification state φ1, when (L + j) capacitors in the third capacitor column _Caa are grounded and j capacitors in the fourth capacitor column _Cab are grounded, the input terminal of the third amplifier 24a is
V _ex — _p = {(L + j) · V _ap + j · V _bn } / L (31p)
Get. Since V _bn = −V _bp here, the equation (31p) is
V _ex — _p = {(L + j) · V _ap −j · V _bp } / L (31p)
Rewritten. This is nothing but a voltage that divides the two voltages V _ap and V _bp into j: (L + j).

The third switch circuit 22 _an may apply the inverted input voltage V _an to the capacitor column C _{ba and the forward} input voltage V _bn to the capacitor column C _bb . As a result, the voltage V _{ex_n} represented by the formula (31n) is obtained.
V _ex — _n = {(L + j) · V _an −j · V _bn } / L (31n)
This is nothing but a voltage that divides the two inverted voltages V _an and V _bn into j: (L + j).

  That is, in the B-type conversion circuit UCB of FIG. 13, the voltage applied to the capacitor array is expanded to the inverting side (n), and the number of capacitors may be increased as necessary. When the extrapolation method is used, the gain H of the third amplifier 24a and the fourth amplifier 24b can be further reduced.

  In the embodiments, the case where the common voltage Vc is the ground voltage GND has been described, but the present invention is not limited to this. When it is desired to operate the circuit in the positive voltage range, the common voltage Vc may be the midpoint voltage Vdd / 2 of the power supply voltage Vdd. Alternatively, Vref / 2 may be used when the reference voltage Vref is applied.

  As described above, relative accuracy is required for the gain (-G) of the first amplifier 14a and the second amplifier 14b belonging to the same conversion circuit, but absolute accuracy is not required. Further, each gain has a property that it is sufficient to be several times, or several tens of times at most. The same applies to the third amplifier 24a and the fourth amplifier 24b. Therefore, a preferred configuration of the dynamic differential amplifier having such characteristics will be described.

FIG. 15 is a circuit diagram showing a configuration of the dynamic differential amplifier 30. The dynamic differential amplifier 30 amplifies the signals V _i1 and V _i2 input to the first input terminal P _i1 and the second input terminal P _i2 , and the amplified signals V _o1 and V _o2 to the first output terminal P. _{o1 is} output from the second output terminal _Po2 .

The dynamic differential amplifier 30 includes a first load capacitor C _L1 , a second load capacitor C _L2 , an input differential pair 32, an initialization circuit 34, a control circuit 36, and a tail current source M 0.

The first load capacitor C _L1 is provided between the first output terminal P _o1 and the fixed voltage terminal (ground terminal). The second load capacitor _{C L2,} is provided between the second output terminal _{P o2} ground terminal.

The initialization circuit 34 initializes the charges of the first load capacitor C _L1 and the second load capacitor C _L2 . Initialization circuit 34 includes, for example, initialization transistors M3 and M4. The initialization transistor M3 is provided between the first load capacitor _CL1 and the second fixed voltage terminal (power supply terminal). Similarly, the initialization transistor M4 is provided between the second load capacitor _CL2 and the power supply terminal. The initialization transistors M3 and M4 are controlled to be turned on and off in synchronization with a control clock _VCLK that transitions to a low level at a predetermined cycle. When the initialization transistors M3 and M4 are turned on, the first load capacitor C _L1 and the second load capacitor C _L2 are charged by the power supply voltage V _DD and the respective charges are initialized.

The input differential pair 32 includes an input transistor M1 and an input transistor M2. The input transistor M1 has the first load capacitor C _L1 as a load, and a first input signal V _i1 is input to a control terminal (gate) thereof. Similarly, the input transistor M2 uses the second load capacitor C _L2 as a load, and a second input signal V _i2 is input to the gate thereof. The tail current source M0 supplies an operating current (tail current) I ₀ = I _D1 + I _D2 to the input differential pair 32.

When the midpoint voltage (V _o1 + V _o2 ) / 2 of the potentials V _o1 and V _o2 of the first output terminal P _o1 and the second output terminal P _o2 reaches the predetermined threshold voltage Vth, the control circuit 36 The charge / discharge paths of the first load capacitor C _L1 and the second load capacitor C _L2 are cut off.

A first switch SW1 and a second switch SW2 are provided to cut off the charge / discharge path of the first load capacitor C _L1 and the second load capacitor C _L2 . The first switch SW1 is provided between the first load capacitor _CL1 and the input transistor M1. The second switch SW2 is provided between the second load capacitor _CL2 and the input transistor M2.

The control circuit 36 switches between conduction and interruption of the charge / discharge paths of the first load capacitor C _L1 and the second load capacitor C _L2 by switching the first switch SW1 and the second switch SW2 on and off.

The basic configuration of the dynamic differential amplifier 30 has been described above. Next, the operation will be described. FIG. 16 is a waveform diagram showing the operation of the dynamic differential amplifier 30 of FIG. The horizontal axis represents time, and the vertical axis represents output voltages V _o1 and V _o2 .

1. Initialization State Prior to amplification, the dynamic differential amplifier 30 is set to an initialization state (t <t ₀ ). In the initialization state, the control clock _VCLK becomes low level and the initialization transistors M3 and M4 are turned on. The control circuit 36 turns on the first switch SW1 and the second switch SW2. As a result, the power supply voltage V _DD is applied to the first load capacitor C _L1 and the second load capacitor C _L2 , and the output voltages V _o1 and V _o2 are initialized to the power supply voltage V _DD .

2. Amplification state When the control clock _VCLK becomes high level, the initialization transistors M3 and M4 are turned off, and the amplification state is established (t ₀ <t <t ₁ ). In the amplified state, currents I _D1 and I _D2 corresponding to the input voltages V _i1 and V _i2 flow through the input transistor M1 and the input transistor M2, respectively. The currents I _D1 and I _D2 are given by the equations (32a) and (32b), where g _{m is} the mutual conductance of the input transistor M1 and the input transistor M2, and I ₀ is the tail current.
_{I D1 = I 0/2 +} g m × (V i1 -V i2) / 2 ... (32a)
I _D2 = I ₀ / 2−g _m × (V _i1 −V _i2 ) / 2 (32b)
Note that I ₀ = I _D1 + I _D2 holds.

When the elapsed time from the start of amplification is t, the output voltages V _o1 and V _o2 are given by the equations (33a) and (33b), respectively.
V _o1 = V _DD −I _D1 / C _L1 · t (33a)
V _o2 = V _DD −ID ₂ / C _L2 · t (33b)

The control circuit 36 monitors the midpoint voltage V _x = (V _o1 + V _o2 ) / 2 of the output voltages V _o1 and V _{o2. When} the control circuit 36 reaches a predetermined threshold voltage Vth, the first switch is reached at the time t ₁ . SW1 and the second switch SW2 are turned off. When the capacitance values of the first load capacitor C _L1 and the second load capacitor C _L2 are equally written as C _L , the midpoint voltage V _x is given by Expression (34).
V _x = V _DD −I ₀ × t / (2 × C _L ) (34)

When the threshold voltage Vth is the midpoint voltage V _DD / 2 of the power supply voltage, the period T of the amplification state is given by Expression (35).
T = _CL × V _DD / I ₀ (35)
The output voltages V _o1 and V _{o2 at} this time are expressed by equations (36a) and (36b).
V _o1 = V _DD / 2-g _m1 / 2 × (V _i1 −V _i2 ) / I ₀ × V _DD (36a)
V _o2 = V _DD / 2 + g _m2 / 2 × (V _i1 −V _i2 ) / I ₀ × V _DD (36b)

Therefore, the differential gain G of the dynamic differential amplifier 30 is given by the equation (37).
G = (V _o1 −V _o2 ) / (V _i1 −V _i2 )
= − (G _m1 + g _m2 ) / 2 × V _DD / (I _D1 + I _D2 ) (37)

The conductance of the input transistor M1 and the input transistor M2 is
g _m1 = 2 × I _D1 / V _eff (38a)
g _m2 = 2 × I _D2 / V _eff (38b)
Therefore, this relationship is substituted into the equation (37) to obtain the equation (39).
G = −V _DD / V _eff (39)
Note that V _eff = V _GS −Vt. V _GS is a gate-source voltage, and Vt is a gate-source threshold voltage of the MOSFET.

Energy consumption E _c per amplification single dynamic differential amplifier 30 of FIG. 15,
_{E c = Q · V DD =} 2 · I D · T · V DD = C L · V DD 2 ... (40)
It becomes. Therefore, the power consumption P _d is expressed by the repetition frequency f _c .
_{P d = f c · E c} = f c · C L · V DD 2 ... (41)
It becomes.

The advantage of the dynamic differential amplifier 30 of FIG. 15 becomes clear by comparison with the amplifier of FIG. FIG. 17 is a circuit diagram showing a configuration of an amplifier 1030 according to the comparison technique. The amplifier 1030 includes load resistors R _L1 and R _L2 instead of the initialization circuit. It should be noted that the capacitors C _L1 and C _L2 and the switches SW1 and SW2 are provided for sampling the drain voltages of the transistors M1 and M2, and have different functions from the dynamic differential amplifier 30 of FIG. is there.

In the amplifier 1030, the drain currents of the input transistor M1 and the input transistor M2 constantly flow through the load resistors R _L1 and R _L2 . Since the output voltages V _o1 and V _o2 in the bias state are set to about ½ of the power supply voltage V _DD , the resistors R _L1 and R _L2 are
R _L = V _DD / 2 _ID (42)
Holds. Here, R _L = R _L1 = R _L2 and I _D = (I _D1 + I _D2 ) / 2. The mutual conductance g _m of the transistors M1 and M2 is obtained from the relational expression of voltage and current in the saturation region of the MOS transistor:
g _m = 2 · _ID / V _eff (43)
Given in. Therefore, the differential gain G of this circuit is
G = −g _m · R _L = −V _DD / V _eff (44)
It becomes. That is, it can be seen that the gain of the dynamic differential amplifier 30 of FIG. 15 is the same as that of the amplifier 1030 of FIG.

Consider the power consumption of the amplifier of FIG. Since the voltage V _eff is normally about 0.2V, when V _DD = 1V, the voltage V _eff is about 5 times. The time response of amplifier 1030 is
V _o1 −V _o2 = G · (V _i1 −V _i2 ) · (1−e ^{1 / τ} ) (45)
τ = R _L・ C _L
It is. Considering that a steady current 2 · _ID flows in this circuit, the power consumption _PD is
P _D = 2 · _{ID D} · V _DD = V _DD ² / R _L = C _L · V _DD ² / τ (46)

  As is apparent from the equation (45), the response time constant τ of the amplifier 1030 is determined by the product of the resistance and the capacity. Therefore, in order to increase the response speed, that is, to shorten the time constant τ, it is necessary to reduce the resistance value. is there. However, when the resistance value is lowered, the power consumption given by equation (46) increases in inverse proportion.

In the amplifier of Figure 17, assuming a 1% settling, for a half cycle 5 · tau is necessary, the power consumption P _D is given by equation (47).
P _D = C _L · V _DD ² / τ = 10 · f _c · C _L · V _DD ² (47)

Comparing the amplifier of FIG. 15 of FIG. 17, the advantages of the dynamic differential amplifier 30 of FIG. 15 become apparent as follows.
First, the dynamic differential amplifier 30 of FIG. 15, since the power consumption _{P D} is given by the equation (41), in comparison with the power _{P D} of the amplifier 1030 of FIG. 17 given by equation (47), about It turns out that it can reduce to about 1/10.

In the circuit of Figure 17, when designing a repetition frequency f _c in inverse proportion to the load resistor R _L, it is possible to reduce power consumption, to a variable resistance value over a wide band is not easy, it is unrealistic . That is, in reality, the resistance _RL must be set low so that a sufficient response speed can be obtained at the assumed maximum repetition frequency _fcmax , and the power consumption increases as shown in the equation (47). In this regard, according to the configuration of FIG. 15, the power consumption is irrelevant to the operating current as shown in the equation (41), and therefore the power consumption does not increase even if the operating current is increased for the purpose of speeding up. There are advantages. Also in the case of lowering the frequency f _c may provide the amplifier operating at very low power consumption.

Next, a more specific configuration example of the dynamic differential amplifier 30 will be described.
18A and 18B are circuit diagrams showing a specific example of the dynamic differential amplifier 30 of FIG.

In the dynamic differential amplifier 30a of FIG. 18A, the control circuit 36a includes a first voltage dividing capacitor C ₁ , a second voltage dividing capacitor C ₂ , and a comparator 38. First divided capacitor _{C 1,} the second divided capacitor _{C 2} are provided in series between the first output terminal _{P o1} of the second output terminal _{P o2.} Capacitance value of the first divided capacitor _{C 1} and the second divided capacitor _{C 2} is equal _{C 0.} Comparator 38, first divided capacitor _{C 1,} the potential _{V x} of the second partial pressure of the connection point capacitor _{C 2} with a predetermined threshold voltage Vth, the switch SW1 with a signal corresponding to the comparison result, SW2 To control.

As shown in the lower part of FIG. 18A, the comparator 38 may include an inverter 39. Inverter 39 receives power supply voltage V _DD and ground voltage GND, and its threshold voltage Vth is V _DD / 2. The number of stages of the inverter 39 may be designed according to the control logic of the switches SW1 and SW2.

Initialization circuit 34a, a potential _{V x} of the first divided capacitor _{C 1} and the second divided capacitor _{C 2} of the connection point _{N x,} the first output terminal _{P o1,} as in the second output terminal _{P o2,} supply voltage Initialize to V _DD . More specifically, between the node N _x and the power supply terminal, the initialization transistor M5 is provided, which turns on, the potential of the node N _x is initialized.

By the initialization, the charges of the capacitors C ₁ and C ₂ are initialized to zero. Precharge is released and amplification starts. When the output voltages V ₁ and V ₂ are generated at the first output terminal P _o1 and the second output terminal P _o2 , Expression (48) is established if the parasitic capacitance is ignored.
_{C 0 (V x -V 1)} = C 0 (V x -V 2) ... (48)
Solving Equation (48) for V _x yields Equation (49).
V _x = (V ₁ + V ₂ ) / 2 (49)
That is, the potential V _{x at} the connection point N _x becomes a midpoint voltage between the two output voltages V _o1 and V _o2 , and the midpoint voltage V can be compared with the threshold voltage as in the circuit of FIG.

A control clock _VCLK is input to the gate of the tail current source M0. As a result, the tail current source M0 can be turned off in the initialization state, so that power consumption can be further reduced.

The dynamic differential amplifier 30b shown in FIG. 18B includes a logic gate 40 in addition to the dynamic differential amplifier 30a shown in FIG. The logic gate 40 supplies the logical product of the output signal CNT of the control circuit 36 and the control clock V _CLK to the gate of the tail current source M0. According to this configuration, the charge / discharge paths of the first load capacitor C _L1 and the second load capacitor C _L2 can be more reliably interrupted. Further, by turning off the tail current source M0, the potentials of the first output terminal P _o1 and the second output terminal P _o2 do not _{drop to} the ground potential (0 V). Therefore, the power consumption can be further reduced as compared with FIG.

  FIGS. 19A and 19B are circuit diagrams showing another specific example of the dynamic differential amplifier. In the dynamic differential amplifier 30c shown in FIG. 19A, the control circuit 36c is composed of a logic gate. Specifically, the control circuit 36c is an AND gate. FIG. 19B is a circuit diagram showing a specific configuration of the control circuit 36c. The control circuit 36c includes a NAND gate 42 and an inverter (NOT gate) 44 provided in the subsequent stage.

The NAND gate 42 includes P-channel transistors M _P1 and M _P2 , and N-channel transistors M _N1 , M _N2 , M _N3 , and M _N4 . The first P-channel transistor M _P1 , the first N-channel transistor M _N1 , and the second N-channel transistor M _N2 are sequentially stacked so as to form a first path between the power supply terminal and the ground terminal. The second P-channel transistor M _P2 , the third N-channel transistor M _N3 , and the fourth N-channel transistor M _N4 are sequentially stacked so as to form a second path parallel to the first path between the power supply terminal and the ground terminal.

The first input signal V ₁ is applied to the gates of the first P-channel transistor M _P1 , the first N-channel transistor M _N1 , and the fourth N-channel transistor M _N4 . The second input signal V ₂ is applied to the gates of the second P-channel transistor M _P2 , the second N-channel transistor M _N2 , and the third N-channel transistor M _N3 . The output terminal of the NAND gate 42 is connected to the drains of the first and second P-channel transistors M _P1 and M _P2 .

If the average drain current of the N-channel transistor is I _DN and the average drain current of the P-channel transistor is I _DP , the voltage-current characteristics can be approximated by the equations (50a) and (50b) in a fine transistor.
I _DN = K _N (V _GS −V _TN ) (50a)
I _DP = −K _P (V _GS −V _TP ) (50b)

The output of the NAND gate 42 changes its logic state when the total current flowing through the P-channel transistor is equal to the total current flowing through the N-channel transistor. Therefore,
I _DN = K _N (V ₁ −V _TN ) + K _N (V ₂ −V _TN )
= 2 · K _N {(V ₁ + V ₂ ) / 2−V _TN } (51a)
I _DP = K _P (V _DD −V ₁ + V _TP ) + K _P (V _DD −V ₂ + V _TP )
= 2 · K _P {− (V ₁ + V ₂ ) / 2 + V _DD + V _TP } (51b)

From these, the input voltages V ₁ and V ₂ giving I _DN = I _DP are
(V ₁ + V ₂ ) / 2 = (K _N · V _TN + K _P · V _TP ) / (K _N + K _P ) + K _P / (K _N + K _P ) · V _DD (52)
Thus, it can be seen that the output logic state is switched at the midpoint voltage of V ₁ and V ₂ . As described above, the midpoint voltage can be compared with the threshold voltage Vth by using the NAND gate 42 shown in FIG. 19B instead of the voltage dividing capacitors C ₁ and C ₂ .

  15 to 19 show the case where the input differential pair 32 is configured by an N-channel MOSFET, but on the contrary, it may be configured by using a P-channel MOSFET. In this case, the N channel and the P channel are replaced, the power supply voltage and the ground voltage are inverted, and the gate signal of each transistor is inverted if necessary.

In the embodiment, the case where the control circuit 36 cuts off the charge / discharge path of the load capacitors C _L1 and C _L2 according to the midpoint voltage Vx of the output voltages V _o1 and V _o2 has been described. You may comprise with the timer circuit which measures elapsed time.

FIG. 20 is a circuit diagram showing a modification of the dynamic differential amplifier 30 of FIG. In the dynamic differential amplifier 30 of FIG. 15, a tail current source M0 is provided to set the operating current of the input transistors M1 and M2. Since the drain-source voltage of the tail current source M0 is required to be 0.2 V or more, it is difficult to use in a situation where the power supply voltage _VDD is low. Therefore, the dynamic differential amplifier 30d in FIG. 20 is configured by a pseudo differential circuit in which the tail current source M0 in FIG. 15 is omitted. Input to the transistors M1, M2 respectively on the drain side, turned in synchronization with the control clock _{V CLK,} switching transistors M5, M6 of off controlled is provided. The switch transistors M5 and M6 are turned off in the initialization state and turned on in the amplification state.

In the dynamic differential amplifier 30d of FIG. 20, the operating currents of the input transistor M1 and the input transistor M2 are controlled by controlling the gate voltages V _i1 and V _i2 of the input transistor M1 and the input transistor M2. Since the switch transistors M5 and M6 function as switches that are switched between the on and off states, their drain-source voltage Vds is substantially zero in the operating state. Therefore, the dynamic differential amplifier 30d can operate even with the power supply voltage V _DD lower than the drain-source voltage Vds (≈0.2V) of the tail current source M0 as compared with FIG.

In FIG. 20, the transistors M5 and M6 may be omitted, and the gate voltages V _i1 and V _i2 may be controlled so that the input transistors M1 and M2 are turned off during a period in which the transistors M5 and M6 are to be turned off.
Moreover, you may combine FIG. 20 and FIG.18 (b). In this case, the output of the gate 40 in FIG. 18B may be input to the gates of the transistors M5 and M6 in FIG.

  The dynamic differential amplifier described with reference to FIGS. 15 to 20 can be suitably used for the above-described A / D converter, but its application is not limited. The dynamic differential amplifier does not require absolute accuracy of gain, but can be used for various applications that require relative accuracy, and can suitably reduce power consumption.

  Although the present invention has been described using specific words and phrases based on the embodiments, the embodiments are merely illustrative of the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangements can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... A / D converter, UCA ... A type conversion circuit, UCB ... B type conversion circuit, 10 ... 1st sub A / D converter, 11a ... 1st amplifier circuit, 11b ... 2nd amplifier circuit, 12a ... 1st switch Circuit, 12b ... second switch circuit, 14a ... first amplifier, 14b ... second amplifier, Ca ... first capacitor row, Cb ... second capacitor row, 20 ... second sub A / D converter, 21a ... third amplification Circuit, 21b ... 4th amplifier circuit, 22aa ... 3rd switch circuit, 22ab ... 4th switch circuit, 22ba ... 5th switch circuit, 22bb ... 6th switch circuit, 24a ... 3rd amplifier, 24b ... 4th amplifier, 26 ... gain adjustment circuit.

  The present invention relates to a pipeline type A / D converter.

Claims (24)

An A / D conversion method for converting an analog input voltage into digital data,
A first step of comparing the input voltage with a plurality of threshold voltages to determine which of a plurality of segments belongs;
A second step of generating a first voltage and a second voltage across a segment to which the input voltage belongs;
A third step of generating a third voltage by amplifying a difference between the first voltage and the input voltage with reference to a predetermined common voltage;
A fourth step of generating a fourth voltage by amplifying a difference between the second voltage and the input voltage with reference to the common voltage;
A fifth step of dividing between the third voltage and the fourth voltage into a plurality of segments and determining which of the plurality of segments the common voltage belongs to;
A sixth step of generating a fifth voltage and a sixth voltage across a segment to which the common voltage belongs;
A seventh step of generating a seventh voltage by amplifying a difference between the fifth voltage and the common voltage with reference to the common voltage;
An eighth step of generating an eighth voltage by amplifying a difference between the sixth voltage and the common voltage with reference to the common voltage;
With
The fifth to eighth steps are repeatedly executed,
When returning from the eighth step to the fifth step, the seventh voltage obtained in the previous seventh step is used as the third voltage in the next fifth step, and the eighth voltage obtained in the previous eighth step is used. An A / D conversion method characterized by being used as a fourth voltage in the next fifth step.   2. The A / D conversion according to claim 1, wherein in the sixth step, the fifth voltage and the sixth voltage are generated by interpolating the third voltage and the fourth voltage, respectively. Method.   The A / D conversion method according to claim 1, wherein each of the first voltage to the eighth voltage is generated as a differential signal.   4. The A / D according to claim 3, wherein in the sixth step, the fifth voltage and the sixth voltage are generated by extrapolating the third voltage and the fourth voltage. 5. Conversion method. A pipeline type A / D converter for converting an analog input voltage into digital data,
A type conversion circuit connected in series, at least one B type conversion circuit and a comparator row,
The A-type conversion circuit is
A first sub A / D converter that compares the input voltage with a plurality of threshold voltages and determines which of the plurality of segments belongs;
Generating a first voltage having a voltage level equal to or higher than an upper limit of a segment to which the input voltage belongs, and generating a third voltage by amplifying a difference between the first voltage and the input voltage with reference to a predetermined common voltage; A first amplifier circuit that outputs to a subsequent B-type converter circuit;
Generating a second voltage having a voltage level equal to or lower than a lower limit of a segment to which the input voltage belongs, and generating a fourth voltage by amplifying a difference between the second voltage and the input voltage based on a predetermined common voltage; A second amplifier circuit that outputs to the B-type converter circuit at the subsequent stage;
With
The B-type conversion circuit is
A second sub A / D converter that divides between the third voltage and the fourth voltage from the previous stage into a plurality of segments and determines which of the plurality of segments the common voltage belongs to;
A seventh voltage is generated by amplifying a difference between the fifth voltage having a voltage level equal to or higher than the upper limit of the segment to which the common voltage belongs and the common voltage, and the B-type conversion circuit in the subsequent stage generates the seventh voltage. A third amplifier circuit that outputs a third voltage;
An eighth voltage is generated by amplifying a difference between the sixth voltage having a voltage level equal to or lower than a lower limit of the segment to which the common voltage belongs and the common voltage, and the B-type conversion circuit in the subsequent stage generates the eighth voltage. A fourth amplifier circuit that outputs a fourth voltage;
With
The comparator row divides the third voltage and the fourth voltage from the B-type conversion circuit in the previous stage into a plurality of segments, and determines which of the plurality of segments the common voltage belongs to Characteristic A / D converter. The first amplifier circuit includes:
A first capacitor row including a plurality of first capacitors each having a first terminal connected in common;
In the sampling state, the input voltage is applied to the second terminal of the first capacitor row, and in the interpolation amplification state, the number of the first capacitor rows in accordance with the determination result by the first sub A / D converter. A first switch circuit for applying a reference voltage to the second terminal of the first capacitor;
A first switch provided between the first terminal and the fixed voltage terminal of the first capacitor row, which is turned on in the sampling state and turned off in the interpolation amplification state;
A first amplifier having the common voltage input to the first input terminal and a second input terminal connected to the first terminal of the first capacitor row;
Including
6. The A according to claim 5, wherein the second amplifier circuit includes a second capacitor row, a second switch circuit, a second switch, and a second amplifier, and is configured similarly to the first amplifier circuit. / D converter.   The third and fourth amplifier circuits generate the fifth voltage and the sixth voltage by interpolating the third voltage and the fourth voltage, respectively. A / D converter described in 1. The third amplifier circuit includes:
A third capacitor row including a plurality of third capacitors each having a first terminal connected in common;
A fourth capacitor row including a plurality of fourth capacitors, each first terminal connected in common with the first terminal of the third capacitor row;
In the sampling state, the third voltage is applied to the second terminal of the third capacitor row, and in the interpolation amplification state, the number of the third capacitor row according to the determination result by the second sub A / D converter A third switch circuit for applying a fixed voltage to the second terminal of the third capacitor;
In the sampling state, the fourth voltage is applied to the second terminal of the fourth capacitor row, and in the interpolation amplification state, the number of the fourth capacitor rows according to the determination result by the second sub A / D converter A fourth switch circuit for applying a fixed voltage to the second terminal of the fourth capacitor;
A third switch provided between the first terminal and the fixed voltage terminal that are commonly connected to the third capacitor row and the fourth capacitor row, and is turned on in the sampling state and turned off in the interpolation amplification state;
A third amplifier in which the common voltage is input to the first input terminal, and the second input terminal is connected to the first terminal commonly connected to the third capacitor row and the fourth capacitor row;
Including
The fourth amplifier circuit includes a fifth capacitor row, a sixth capacitor row, a fifth switch circuit, a sixth switch circuit, a fourth switch, and a fourth amplifier, and is configured in the same manner as the third amplifier circuit. The A / D converter according to claim 7.   The third switch circuit applies the third voltage from the previous stage as the fixed voltage when the fixed voltage is applied to the third capacitor row in the interpolation amplification state, and the fourth switch circuit performs interpolation. When the fixed voltage is applied to the fourth capacitor row in the amplification state, the offset voltage of the amplifier of the conversion circuit in the previous stage is canceled by applying the fourth voltage from the previous stage as the fixed voltage. The A / D converter according to claim 8.   The A / D converter according to claim 8, wherein the first to fourth amplifier circuits are configured in a differential manner.   The third amplifying circuit and the fourth amplifying circuit combine the normal voltage signal and the inverted signal of the third voltage, and the normal voltage signal and the inverted signal of the fourth voltage to combine the fifth voltage and the sixth voltage. The A / D converter according to claim 10, wherein the A / D converter is generated by either interpolation or extrapolation of the third voltage and the fourth voltage. The third switch circuit applies a normal signal or an inverted signal of the third voltage to the second terminal of the third capacitor row in the sampling state;
12. The A / D converter according to claim 11, wherein the fourth switch circuit applies a normal signal or an inverted signal of the fourth voltage to a second terminal of the fourth capacitor row in a sampling state. .   The A / D converter according to claim 8, wherein the B-type conversion circuit further includes a gain adjustment unit capable of digitally controlling the gains of the third amplifier and the fourth amplifier. An input switch provided before the B-type conversion circuit, for swapping the third voltage and the fourth voltage to supply the B-type conversion circuit;
An output switch provided at a subsequent stage of the B-type conversion circuit, swapping the seventh voltage and the eighth voltage and outputting the swapped output to the B-type conversion circuit at the subsequent stage;
The A / D converter according to claim 5, further comprising: Each of the first amplifier and the second amplifier includes a dynamic differential amplifier;
The dynamic differential amplifier is:
First and second input terminals;
First and second output terminals;
A first load capacitor provided between the first output terminal and the fixed voltage terminal;
A second load capacitor provided between the second output terminal and the fixed voltage terminal;
An initialization circuit for initializing charges of the first and second load capacitors;
An input differential pair including first and second input transistors, each of which has the first and second load capacitors as loads, and each control terminal connected to the first and second input terminals;
A control circuit that cuts off a charging / discharging path of the first and second load capacitors when a midpoint voltage of the potential of each of the first output terminal and the second output terminal reaches a predetermined threshold voltage;
The A / D converter according to claim 6, further comprising: Each of the third amplifier and the fourth amplifier includes a dynamic differential amplifier,
The dynamic differential amplifier is:
First and second input terminals;
First and second output terminals;
A first load capacitor provided between the first output terminal and the fixed voltage terminal;
A second load capacitor provided between the second output terminal and the fixed voltage terminal;
An initialization circuit for initializing charges of the first and second load capacitors;
An input differential pair including first and second input transistors, each of which has the first and second load capacitors as loads, and each control terminal connected to the first and second input terminals;
A control circuit that cuts off a charging / discharging path of the first and second load capacitors when a midpoint voltage of the potential of each of the first output terminal and the second output terminal reaches a predetermined threshold voltage;
The A / D converter according to claim 8, comprising: A first switch provided between the first load capacitor and the first input transistor;
A second switch provided between the second load capacitor and the second input transistor;
Further comprising
The A / D converter according to claim 15 or 16, wherein the control circuit cuts off a charging / discharging path of the first and second load capacitors by turning off the first and second switches. . The dynamic differential amplifier further includes a tail current source for supplying a tail current to the input differential pair,
The A / D converter according to any one of claims 15 to 17, wherein the control circuit cuts off a charging / discharging path of the first and second load capacitors by turning off the tail current source. . The control circuit includes:
First and second voltage dividing capacitors provided in series between the first output terminal and the second output terminal;
A comparator for comparing a potential at a connection point of the first and second voltage dividing capacitors with a predetermined threshold voltage;
The A / D converter according to claim 15, comprising:   The A / D converter according to claim 19, wherein the comparator includes an inverter that receives a power supply voltage and a ground voltage as a power supply.   The A / of claim 19, wherein the initialization circuit initializes a potential at a connection point of the first and second voltage dividing capacitors to the same potential as that of the first and second output terminals. D converter. The control circuit includes a NAND gate that receives a potential of each of the first load capacitor and the second load capacitor, and cuts off a charge / discharge path of the first and second load capacitors according to an output of the NAND gate. ,
The NAND gate is
A first P-channel transistor, a first N-channel transistor, and a second N-channel transistor that are sequentially stacked to form a first path between a power supply terminal and a ground terminal;
A second P-channel transistor, a third N-channel transistor, and a fourth N-channel transistor that are sequentially stacked to form a second path parallel to the first path between the power supply terminal and the ground terminal;
Including
A first input signal is applied to the gates of the first P-channel transistor, the first and fourth N-channel transistors,
A second input signal is applied to the gates of the second P-channel transistor, the second and third N-channel transistors,
The A / D converter according to claim 21, wherein an output terminal of the NAND gate is connected to drains of the first and second P-channel transistors. First and second input terminals;
First and second output terminals;
A first load capacitor provided between the first output terminal and the fixed voltage terminal;
A second load capacitor provided between the second output terminal and the fixed voltage terminal;
An initialization circuit for initializing charges of the first and second load capacitors;
An input differential pair including first and second input transistors, each of which has the first and second load capacitors as loads, and each control terminal connected to the first and second input terminals;
A control circuit that cuts off a charging / discharging path of the first and second load capacitors when a midpoint voltage of the potential of each of the first output terminal and the second output terminal reaches a predetermined threshold voltage;
A dynamic differential amplifier comprising: A first switch provided between the first load capacitor and the first input transistor;
A second switch provided between the second load capacitor and the second input transistor;
Further comprising
24. The dynamic differential amplifier according to claim 23, wherein the control circuit cuts off a charging / discharging path of the first and second load capacitors by turning off the first and second switches.

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