JPS6478320A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS6478320A
JPS6478320A JP62233656A JP23365687A JPS6478320A JP S6478320 A JPS6478320 A JP S6478320A JP 62233656 A JP62233656 A JP 62233656A JP 23365687 A JP23365687 A JP 23365687A JP S6478320 A JPS6478320 A JP S6478320A
Authority
JP
Japan
Prior art keywords
data
increase
bus
bits
arrangement order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62233656A
Other languages
Japanese (ja)
Other versions
JPH0774986B2 (en
Inventor
Junji Hatsuzaki
Yoshiyuki Fukuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62233656A priority Critical patent/JPH0774986B2/en
Publication of JPS6478320A publication Critical patent/JPS6478320A/en
Publication of JPH0774986B2 publication Critical patent/JPH0774986B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To minimize the increase of the software load and the increase of the hardware quantity of converting the arrangement order of bits between the data on a 3rd device and the data on a data bus so that the constant arrangement order of bits is secured between the input/output data for the 3rd device. CONSTITUTION:A data bit connection part 5 is set between a 3rd device 3 and a data bus 4 and controlled by a bus master having the using right of the bus 4. The arrangement order of bits is converted by the control of the bus master between the data on the device 3 and the data on the bus 4. So that the arrangement order of bits is fixed between the input/output data for the device 3. Thus only the part 5 added to the device 3 is used for the hardware needed for connection even when many 1st devices 1 are connected. Then the increase of hardware is not needed at all. Thus it is possible to minimize the increase of the software load and the increase the hardware quantity.
JP62233656A 1987-09-19 1987-09-19 Data bus connection system Expired - Lifetime JPH0774986B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62233656A JPH0774986B2 (en) 1987-09-19 1987-09-19 Data bus connection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62233656A JPH0774986B2 (en) 1987-09-19 1987-09-19 Data bus connection system

Publications (2)

Publication Number Publication Date
JPS6478320A true JPS6478320A (en) 1989-03-23
JPH0774986B2 JPH0774986B2 (en) 1995-08-09

Family

ID=16958465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62233656A Expired - Lifetime JPH0774986B2 (en) 1987-09-19 1987-09-19 Data bus connection system

Country Status (1)

Country Link
JP (1) JPH0774986B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261264A (en) * 1991-06-11 1993-11-16 The Boeing Company Automated forming station
JP2002123826A (en) * 2000-10-13 2002-04-26 Canon Inc Data processing method and image processing device
JP2002269551A (en) * 2001-03-08 2002-09-20 Canon Inc Image processing unit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561866A (en) * 1978-11-02 1980-05-09 Casio Comput Co Ltd Memory designation system
JPS6017547A (en) * 1983-07-08 1985-01-29 Nec Corp Action history memory device
JPS61114350A (en) * 1984-11-07 1986-06-02 Toshiba Corp Memory device
JPS61292739A (en) * 1985-06-20 1986-12-23 Ricoh Co Ltd Memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561866A (en) * 1978-11-02 1980-05-09 Casio Comput Co Ltd Memory designation system
JPS6017547A (en) * 1983-07-08 1985-01-29 Nec Corp Action history memory device
JPS61114350A (en) * 1984-11-07 1986-06-02 Toshiba Corp Memory device
JPS61292739A (en) * 1985-06-20 1986-12-23 Ricoh Co Ltd Memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261264A (en) * 1991-06-11 1993-11-16 The Boeing Company Automated forming station
JP2002123826A (en) * 2000-10-13 2002-04-26 Canon Inc Data processing method and image processing device
JP2002269551A (en) * 2001-03-08 2002-09-20 Canon Inc Image processing unit

Also Published As

Publication number Publication date
JPH0774986B2 (en) 1995-08-09

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