JPS6398220A - Ternary logical operation circuit device - Google Patents
Ternary logical operation circuit deviceInfo
- Publication number
- JPS6398220A JPS6398220A JP61244352A JP24435286A JPS6398220A JP S6398220 A JPS6398220 A JP S6398220A JP 61244352 A JP61244352 A JP 61244352A JP 24435286 A JP24435286 A JP 24435286A JP S6398220 A JPS6398220 A JP S6398220A
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- Prior art keywords
- circuit
- josephson
- superconducting
- state
- arithmetic
- Prior art date
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- 230000008878 coupling Effects 0.000 abstract description 3
- 238000010168 coupling process Methods 0.000 abstract description 3
- 238000005859 coupling reaction Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 11
- 239000013642 negative control Substances 0.000 description 4
- 239000013641 positive control Substances 0.000 description 4
- 238000013016 damping Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003359 percent control normalization Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、例えばジョゼフソン素子のような超伝導材料
素子を用いて3値論理演算を行なう演算回路装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic circuit device that performs three-value logic operations using superconducting material elements such as Josephson elements.
(従来の技術)
論理変数が3個の真理値を存する三値論理システムの研
究が広く行なわれている。この三値論理システムは、従
来の二進数システムに比べて、ハードウェアの簡易化、
面積の縮小化、特に情報レベルの多値化による記憶密度
の増大を図ることができると共に、更に段数の減少によ
る演算時間及び伝搬遅延の短縮化を図ることができる等
の種々の利点を達成することができる。(Prior Art) Three-valued logic systems in which logic variables have three truth values have been widely studied. This ternary logic system has simplified hardware compared to the traditional binary system.
It achieves various advantages such as reducing the area, increasing storage density by increasing the number of information levels in particular, and shortening calculation time and propagation delay by reducing the number of stages. be able to.
一方、三輪理演算回路装置としてジョゼフソン素子のよ
うな超伝導素子を有する論理演算回路装置が実用化され
ている。第6図はジョゼフソン素子を有する従来の演算
回路である。制御ライン1に2個のインダクタンスL1
及びL2を直列に接続し、これらインダクタンスL、及
びL2に2個のインダクタンスL3及びL4を磁気的に
結合する。このインダクタンスL3及びL4の直列枝路
に共振現像を防止するためのダンピング抵抗R1を並列
に接続すると共に更に2個のジョゼフソン素子J1及び
J2の直列枝路を並列に接続し、ジョゼフソン素子JI
とJ2との間の接続点を接地する。インダクタンスし3
とL4との間の接続点にバイアス線2を接続すると共に
、このバイアス線2を負荷抵抗RLを介して接地する。On the other hand, logic arithmetic circuit devices having superconducting elements such as Josephson elements have been put into practical use as tricycle logic arithmetic circuit devices. FIG. 6 shows a conventional arithmetic circuit having a Josephson element. Two inductances L1 on control line 1
and L2 are connected in series, and two inductances L3 and L4 are magnetically coupled to these inductances L and L2. A damping resistor R1 for preventing resonance development is connected in parallel to the series branches of the inductances L3 and L4, and the series branches of two Josephson elements J1 and J2 are connected in parallel, and the Josephson element JI
Ground the connection point between and J2. Inductance 3
A bias line 2 is connected to the connection point between and L4, and this bias line 2 is grounded via a load resistor RL.
第7図は、第6図に示す演算回路のジョゼフソン素子の
闇値特性を示す線図である。横軸は制御電流1cを示し
、縦軸はバイアス電流りを示す。FIG. 7 is a diagram showing the dark value characteristics of the Josephson element of the arithmetic circuit shown in FIG. The horizontal axis shows the control current 1c, and the vertical axis shows the bias current.
ハツチングを付して示す闇値ラインの外側においてジョ
ゼフソン素子は電圧状態(常伝導状態)を占め、内側に
おいて超電導状態を占める。従って、第7図に示すよう
にバイアス電流■、を固定し制御電流工。を変化させる
ことによりジョゼフソン素子が超電導状態と電圧状態と
の間で切り換わることになる。一方、負荷抵抗R5の両
端においては、ジョゼフソン素子が超電導状態にあると
きは零電位となり、電圧状態にあるときには所定の電位
を発生する。従って、素子が超電導状態と電圧状態との
間で切り換わるように制御電流Icを切り換え、ジョゼ
フソン素子が電圧状態にあるときを“1”とし、超電導
状態にあるときを0”とし、一方負荷抵抗RLの両端に
電位差が生じるときを1とし、零電位のときを0とすれ
ば、And動作が達成される。Outside the dark value line shown with hatching, the Josephson element is in a voltage state (normal conduction state), and inside it is in a superconductivity state. Therefore, as shown in Fig. 7, the bias current (2) is fixed and the control current is adjusted. By changing , the Josephson device switches between a superconducting state and a voltage state. On the other hand, at both ends of the load resistor R5, when the Josephson element is in a superconducting state, it has a zero potential, and when it is in a voltage state, it generates a predetermined potential. Therefore, the control current Ic is switched so that the element switches between the superconducting state and the voltage state, and it is set as "1" when the Josephson element is in the voltage state, and as 0 when it is in the superconducting state, while the load If the value is 1 when a potential difference occurs between both ends of the resistor RL, and the value is 0 when the potential is zero, an And operation is achieved.
(発明が解決しようとする問題点)
上述したジョゼフソン素子を有する演算回路は、複雑な
闇値を達成でき、多値論理システムを構成する上で有利
である。しかしながら、電圧値として“0”と“1”に
対応する2値だけしかとり得す、従って3値論理回路を
構成することができない欠点があった。また、闇値特性
が規則的であるため、特異な関数を表現するためには回
路構成が複雑になる不都合があった。(Problems to be Solved by the Invention) The arithmetic circuit having the Josephson element described above can achieve complex dark values and is advantageous in configuring a multivalued logic system. However, it has the disadvantage that only two values corresponding to "0" and "1" can be taken as voltage values, and therefore a three-value logic circuit cannot be constructed. Furthermore, since the dark value characteristic is regular, there is a disadvantage that the circuit configuration becomes complicated in order to express a unique function.
従って、本発明の目的は上述した欠点を解消し、3値論
理演算を高速で且つ低い消費電力で行なうことができる
超電導素子を有する演算回路を提供するものである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to eliminate the above-mentioned drawbacks and provide an arithmetic circuit having a superconducting element that can perform three-value logic operations at high speed and with low power consumption.
(問題点を解決するための手段及び作用)本発明による
3値論理演算回路装置は、闇値特性に応じて超伝導状態
と常伝導状態との間で切り換わる超伝導素子を含む少な
くとも1個以上の超伝導回路素子を有する第1及び第2
の演算回路を具え、第1の演算回路の各超伝導回路素子
と第2の演算回路の各超伝導回路素子とを制御電流供給
線で結合し、演算指令に応−じて値の異なる3個の制御
電流のいずれか1個の制御電流を制御電流供給線に供給
して第1及び第2の演算回路から超伝導状態又は電圧状
態を出力させ、第1及び第2の演算回路の出力に基いて
3個の論理値のいずれか1個を出力するように構成した
ことを特徴とするものである。(Means and effects for solving the problem) A three-value logic operation circuit device according to the present invention includes at least one superconducting element that switches between a superconducting state and a normal conducting state according to dark value characteristics. A first and a second circuit having the above superconducting circuit elements.
Each superconducting circuit element of the first arithmetic circuit and each superconducting circuit element of the second arithmetic circuit are connected by a control current supply line, and three Any one of the control currents is supplied to the control current supply line to output a superconducting state or a voltage state from the first and second arithmetic circuits, and the output of the first and second arithmetic circuits is The present invention is characterized in that it is configured to output any one of three logical values based on the following.
このように、第1及び第2の演算回路の各超伝導回路素
子を制御電流供給ラインで結合しているので、3個の制
御電流のいずれか1個の制御電流を各超伝導回路素子に
供給することによって演算指令に応じて第1及び第2の
演算回路から超伝導状態又は電圧状態を出力することが
でき、これらの出力に基いて3値の出力が形成される。In this way, since each superconducting circuit element of the first and second arithmetic circuits is connected by a control current supply line, any one of the three control currents can be applied to each superconducting circuit element. By supplying the superconducting state or the voltage state, the first and second arithmetic circuits can output a superconducting state or a voltage state according to the arithmetic command, and a three-valued output is formed based on these outputs.
この結果、簡単な回路構成で3値論理演算を実行するこ
とができる。As a result, ternary logic operations can be performed with a simple circuit configuration.
(実施例)
第1図は本発明による三値論理演算を行なう演算回路の
一実施例の構成を示す回路図である。本例では一重否定
の演算を実行する3値論理演算回路装置について説明す
る。本発明では正の電圧状態を発生させるp回路10と
負の電圧状態を発生させるn回路20とを制御電流供給
ラインで結合し、その中点に負荷抵抗を接続し、負荷抵
抗に正、O5負の3種の電圧状態を出力して3値論理演
算を実行する。p回路10とn回路20はほぼ同一の構
成をしており、p回路10は制御電流入力端子30に接
続されている2個のインダクタンスLpl+ Lpzの
直列枝路と、オフセント電流入力端子31に接続されて
いる2個のインダクタンスLp3+ Lp4の直列枝路
と、ジョゼフソン回路(超伝導回路素子)とを有してい
る。ジョゼフソン回路は2個のインダクタンスL□s
Lp&の直列枝路にダンピング抵抗R3を並列に接続す
ると共に、更に2個のジョゼフソン素子J、、 Jtの
直列枝路を並列に接続した構成とする。信号源側のイン
ダクタンスLp++ Lglt+ LP31L、4とジ
ョゼフソン回路側のインダクタンスL R5+L、6と
を誘導結合することによって信号源とジョゼフソン回路
とを接続する。また、バイアス電流入力端子33をジョ
ゼフソン回路のインダクタンスLpSとLp&との接続
点に接続して正のバイアス電流子■、を供給する。この
バイアス電流+18及び後述するn回路側のバイアス電
流−■、は、臨界電流がサイクリックに変動する値に選
択する。(Embodiment) FIG. 1 is a circuit diagram showing the configuration of an embodiment of an arithmetic circuit that performs three-value logic operations according to the present invention. In this example, a three-value logic operation circuit device that performs a single negation operation will be described. In the present invention, the p-circuit 10 that generates a positive voltage state and the n-circuit 20 that generates a negative voltage state are connected by a control current supply line, a load resistor is connected to the midpoint of the line, and a positive voltage, O5 is connected to the load resistor. It outputs three types of negative voltage states and executes three-value logic operations. The p-circuit 10 and the n-circuit 20 have almost the same configuration, and the p-circuit 10 is connected to a series branch of two inductances Lpl+Lpz connected to a control current input terminal 30 and an offset current input terminal 31. It has two series branches of inductances Lp3+Lp4 and a Josephson circuit (superconducting circuit element). The Josephson circuit has two inductances L□s
A damping resistor R3 is connected in parallel to the series branch of Lp&, and the series branches of two Josephson elements J, . . . Jt are further connected in parallel. The signal source and the Josephson circuit are connected by inductively coupling the inductance Lp++ Lglt+ LP31L, 4 on the signal source side and the inductance L R5+L, 6 on the Josephson circuit side. Further, the bias current input terminal 33 is connected to the connection point between the inductances LpS and Lp& of the Josephson circuit to supply a positive bias current element (2). The bias current +18 and the bias current -2 on the n circuit side, which will be described later, are selected to values that cause the critical current to vary cyclically.
n回路20も2個のインダクタンスLnl+ Ln2の
直列枝路と、2個のインダクタンスし。3+ L114
の直列枝路とジョゼフソン回路とを有している。ジョゼ
フソン回路は2個のインダクタンスLnS+ Ln&の
直列枝路にダンピング抵抗R2を並列接続し更に2個の
ジョゼフソン素子J:l+ Jaの直列枝路を並列接続
した構成とする。また、バイアス電流入力端子34をジ
ョゼフソン素子J、とJ4との間の接続点に接続して負
のバイアス電流−■、を供給する。9回路の2個のイン
ダクタンスLllll l、、2の直列枝路をn回路の
インダクタンスLRII LR2の直列枝路に接続し、
L+11+ L11□の直列枝路の他端を接地して9回
路及びn回路に制御電流■8をそれぞれ供給する。また
、9回路のインダクタンスLp3+Lp4の直列枝路を
n回路のインダクタンスし。。The n-circuit 20 also has two series branches of inductances Lnl+Ln2 and two inductances. 3+ L114
It has a series branch of , and a Josephson circuit. The Josephson circuit has a configuration in which a damping resistor R2 is connected in parallel to a series branch of two inductances LnS+Ln&, and a series branch of two Josephson elements J:l+Ja is connected in parallel. Further, the bias current input terminal 34 is connected to the connection point between the Josephson elements J and J4 to supply a negative bias current -■. Connect the series branches of the two inductances Lllll l,, 2 of the 9 circuits to the series branches of the inductances LRII LR2 of the n circuit,
The other end of the series branch of L+11+L11□ is grounded to supply the control current ■8 to the 9 circuit and the n circuit, respectively. In addition, the series branches of the inductance Lp3+Lp4 of 9 circuits are made into the inductance of n circuits. .
Ln4の直列枝路に接続し、Lnl+ Ln4の直列枝
路の他端を接地してn回路10及びn回路20にオフセ
ント電流をそれぞれ供給する。It is connected to the series branch of Ln4, and the other end of the series branch of Lnl+Ln4 is grounded to supply offset currents to the n-circuit 10 and the n-circuit 20, respectively.
尚、制御電流■8及びオフセット電流Toffの9回路
及びn回路における流れる方向は、9回路とn回路とで
は互いに逆向きとなるように設定する。従って、例えば
9回路に正の制御電流又はオフセット電流が流れる場合
n回路には負の制御電流又はオフセット電流が流れ、9
回路に負の制御電流又はオフセット電流が流れる場合n
回路には正の制御電流又はオフセット電流が流れる。9
回路のバイアス電流入力端子33を2個の抵抗R3+
R4の直列枝路を介してn回路のバイアス入力端子34
に接続し、また抵抗R3とR4との接続点に負荷インダ
クタンスLLと負荷抵抗RLとを直列に接続し、負荷抵
抗1?Lの他端を接地する。R3及びR4はジョゼフソ
ン素子が超電導状態にあるときに電流が負荷側に流れる
のを阻止する作用を果す。更に、n回路10のジョゼフ
ソン素子J1とJ2の接続点をn回路20のインダクタ
ンスL*SとLn&の接続点に接続すると共に接地する
。このように構成すれば、n回路10のジョゼフソン素
子J、及びJ2及びn回路20のジョゼフソン素子J、
及びJ4が共に超電導状態になれば負荷抵抗RLの両端
間の電圧は零となり、n回路10のジョゼフソン素子J
、及びJ2が電圧状態でn回路20のジョゼフソン素子
J3及びJ4が超電導状態になると負荷抵抗RLに正の
電圧が生じ、9回路のジョゼフソン素子J、及びJ2が
超電導状態でn回路のジョゼフソン素子J3及びJ4が
電圧状態になると負荷抵抗Rtに負の電圧が発生する。Note that the directions in which the control current 8 and the offset current Toff flow in the 9th circuit and the n circuit are set to be opposite to each other in the 9th circuit and the n circuit. Therefore, for example, if a positive control current or offset current flows in 9 circuits, a negative control current or offset current flows in 9 circuits, and 9
When a negative control current or offset current flows in the circuit n
A positive control current or offset current flows through the circuit. 9
Bias current input terminal 33 of the circuit is connected to two resistors R3+
Bias input terminal 34 of the n circuit via the series branch of R4
Also, a load inductance LL and a load resistance RL are connected in series to the connection point of the resistors R3 and R4, and the load resistance 1? Ground the other end of L. R3 and R4 function to prevent current from flowing to the load side when the Josephson element is in a superconducting state. Furthermore, the connection point between the Josephson elements J1 and J2 of the n-circuit 10 is connected to the connection point between the inductances L*S and Ln& of the n-circuit 20, and is also grounded. With this configuration, the Josephson element J of the n circuit 10, and the Josephson element J2 of the n circuit 20,
and J4 both become superconducting, the voltage across the load resistor RL becomes zero, and the Josephson element J of the n circuit 10
, and J2 are in a voltage state and the Josephson elements J3 and J4 of the n circuit 20 are in a superconducting state, a positive voltage is generated in the load resistor RL, and the Josephson elements J and J2 of the 9 circuits are in a superconducting state and the Josephson elements J3 and J4 of the n circuit 20 are in a superconducting state. When the sensor elements J3 and J4 enter a voltage state, a negative voltage is generated across the load resistor Rt.
第2図a及びbはn回路10及びn回路20の各ジョゼ
フソン素子の闇値特性を示す線図である。n回路10に
は正のオフセット電流■。ffを供給しn回路20には
負のオフセット電流−Ioffを供給しているので、9
回路の動作点はA点に固定され、n回路の動作点はD点
に固定される。従って、制御電流1.が零の場合9回路
のジョゼフソン素子は電圧状態となりn回路のジョゼフ
ソン素子は超電導状態となり、負荷抵抗RLには正電圧
が発生する。次に、正の制御電流■8を供給すると、9
回路の動作点はB点に移動し、n回路の動作点はE点に
移動する。従って、9回路のジョゼフソン素子は超電導
状態となり、n回路のジョゼフソン素子は電圧状態とな
り、負荷抵抗RLの電圧は負となる。更に、負の制御電
流Iにを供給すると、9回路の動作点は0点に移動し、
n回路の動作点はF点に移動する。従って、9回路及び
n回路のジョゼフソン素子は共に超電導状態となり、負
荷抵抗RLの電圧は零となる。制御電流の零、正。FIGS. 2a and 2b are diagrams showing the dark value characteristics of each Josephson element of the n-circuit 10 and the n-circuit 20. A positive offset current ■ is applied to the n circuit 10. ff and a negative offset current -Ioff is supplied to the n circuit 20, so 9
The operating point of the circuit is fixed at point A, and the operating point of the n circuit is fixed at point D. Therefore, the control current 1. When is zero, the Josephson elements of nine circuits are in a voltage state, the Josephson elements of n circuits are in a superconducting state, and a positive voltage is generated in the load resistor RL. Next, when positive control current ■8 is supplied, 9
The operating point of the circuit moves to point B, and the operating point of the n circuit moves to point E. Therefore, the Josephson elements of nine circuits are in a superconducting state, the Josephson elements of n circuits are in a voltage state, and the voltage of the load resistor RL becomes negative. Furthermore, when a negative control current I is supplied, the operating point of the 9 circuits moves to the 0 point,
The operating point of the n circuit moves to point F. Therefore, both the 9-circuit and n-circuit Josephson elements become superconducting, and the voltage across the load resistor RL becomes zero. Control current zero, positive.
負の各状態をO+ + 1.−1とし、負荷抵抗RL
の零、正、負の各電圧状態を0+ +1+ 1とすれ
ば、第1表に示す真理表が得られ、−重否定の論理演算
を実行することができる。Each negative state is O+ + 1. -1, load resistance RL
If the zero, positive, and negative voltage states of are set to 0+ +1+ 1, the truth table shown in Table 1 is obtained, and the logical operation of -multiple negation can be executed.
表1
尚、否定論理演算については、第1図に示す演算回路を
用い、オフセット電流及び制御電流を第3図に示すよう
に設定することにより表2に示す真理表の否定演算を行
なうことができる。Table 1 Regarding the negative logical operation, the negative operation of the truth table shown in Table 2 can be performed by using the arithmetic circuit shown in Figure 1 and setting the offset current and control current as shown in Figure 3. can.
表2
次に、3値OR動作を実行する実施例について説明する
。3値OR動作は、2個の制御電流■8及びI7を用い
、制御電流Ix 、 Ivが1,0゜1の3値の組み合
せに対して表3に示す真理表に従う出力を発生させるこ
とにより達成される。Table 2 Next, an example of performing a ternary OR operation will be described. Three-value OR operation uses two control currents ■8 and I7, and generates an output according to the truth table shown in Table 3 for a three-value combination of control currents Ix and Iv of 1,0°1. achieved.
表3
この動作は、本発明の2回路とN回路の出力が制御電流
Ix 、 IYの3値1.0.1の組み合せに対して4
表a及びbの真理表で示す出力をそれぞれ得ることによ
り達成される。Table 3 This operation shows that the output of the two circuits and the N circuit of the present invention is 4 for the combination of control currents Ix and IY of 3 values of 1.0.1.
This is achieved by obtaining the outputs shown in the truth tables of tables a and b, respectively.
表4 この3値OR動作を実行する回路構成を第4図に示す。Table 4 FIG. 4 shows a circuit configuration for executing this three-value OR operation.
この3値OR回路では9回路に2個のジョセフソン回路
素子(超伝導回路素子)を用い、n回路には1個のジョ
セフソン回路素子を用い、負荷部分は第1図に示す回路
を用いる。尚、第1図で用いた部材と同一の部材には同
一符号を付して説明する。第1のジョセフソン回路素子
40の2個のインダクタンスと磁気結合する2個のイン
ダクタンスLIO+ Ll+の直列枝路の一端を制御電
流IXの入力端子41に接続し、他端をn回路20のジ
ョセフソン回路素子のインダクタンスと磁気結合する2
個のインダクタンスLllll Ln2の直列枝路に接
続する。また、第2ジョセフソン回路素子42の2個の
インダクタンスと磁気結合する2個のインダクタンスL
I2+ L13の直列枝路の一端を制御電流Iyの入力
端子43に接続し、他端をn回路20のジョセフソン回
路素子のインダクタンスと磁気結合する2個のインダク
タンスLF13+ LP11の直列枝路に接続する。こ
れにより9回路のジョセフソン回路素子とn回路のジョ
セフソン回路素子とが制御電流供給ラインにより結合さ
れることになる。更に、p回路10のバイアス電流入力
端子33を2個のインダクタンスLIl+ L+sの接
続点に接続し、これらインダクタンスLI4.LI5の
直列枝路の一端を第1ジョセフソン回路素子40の2個
のインダクタンスの接続点に接続し、他端を第2ジョセ
フソン回路素子42の2個のインダクタンスの接続点に
接続するQ制御電流■8又はI7のいずれか一方が正の
制御電流となるとジョセフソン回路素子40又は42の
いずれかが切り換わって電圧状態になり、次いで画素子
供に電圧状態となり負荷側に電流が供給される。他方、
制御電流18又は■7が共に又は一方だけが負の制御電
流となると、これらジョセフソン回路素子40及び42
の閾値特性が非対称のため超伝導状態に維持され、バイ
アス電流■8は全てジョセフソン回路素子40又は42
に流れ負荷側には流れず、この結果表4aの真理表に示
す演算動作を実行する。このような動作を行なう9回路
と第1図に示すn回路により3値OR回路が達成される
。In this three-value OR circuit, two Josephson circuit elements (superconducting circuit elements) are used for the 9 circuits, one Josephson circuit element is used for the n circuit, and the circuit shown in Figure 1 is used for the load section. . The same members as those used in FIG. 1 will be described with the same reference numerals. One end of the series branch of the two inductances LIO+ Ll+ magnetically coupled to the two inductances of the first Josephson circuit element 40 is connected to the input terminal 41 of the control current IX, and the other end is connected to the Josephson circuit element of the n circuit 20. Magnetically coupled with the inductance of the circuit element 2
Inductance Lllll is connected to the series branch of Ln2. In addition, two inductances L magnetically coupled to the two inductances of the second Josephson circuit element 42
One end of the series branch of I2+ L13 is connected to the input terminal 43 of the control current Iy, and the other end is connected to the series branch of two inductances LF13+ LP11 magnetically coupled to the inductance of the Josephson circuit element of the n-circuit 20. . As a result, nine Josephson circuit elements and n Josephson circuit elements are coupled by the control current supply line. Furthermore, the bias current input terminal 33 of the p-circuit 10 is connected to the connection point of the two inductances LI1+L+s, and these inductances LI4. Q control in which one end of the series branch of LI5 is connected to the connection point of the two inductances of the first Josephson circuit element 40, and the other end is connected to the connection point of the two inductances of the second Josephson circuit element 42. When either current 8 or I7 becomes a positive control current, either Josephson circuit element 40 or 42 switches to a voltage state, and then the pixel becomes a voltage state and current is supplied to the load side. . On the other hand,
When both or only one of the control currents 18 and 7 becomes a negative control current, these Josephson circuit elements 40 and 42
is maintained in a superconducting state due to the asymmetric threshold characteristics of
The flow does not flow to the load side, and the arithmetic operation shown in the truth table of result table 4a is executed. A three-value OR circuit is achieved by nine circuits that perform such operations and the n circuits shown in FIG.
このOR動作を、第5図a ”−cの闇値特性図を以て
説明する。第5図aは9回路の第1のジョセフソン回路
素子40の闇値動作特性を示し、第5図すは第2のジョ
セフソン回路素子42の闇値動作特性を示し、第5図C
はn回路のジョセフソン回路素子の闇値動作特性を示す
。制御電流Ix及びryが共にOのときの9回路のジョ
セフソン回路素子40及び42の動作点及びn回路のジ
ョセフソン回路素子の動作点を点50.60及び70に
それぞれ定める。This OR operation will be explained with reference to the dark value characteristic diagrams shown in FIG. 5a''-c. FIG. FIG. 5C shows the dark value operating characteristics of the second Josephson circuit element 42.
represents the dark value operating characteristic of an n-circuit Josephson circuit element. When the control currents Ix and ry are both O, the operating points of the 9-circuit Josephson circuit elements 40 and 42 and the operating points of the n-circuit Josephson circuit element are determined at points 50, 60, and 70, respectively.
この状態から制御電流■8及びIYがTに切り換わると
各動作点50.60及び70は動作点51.61及び7
1にそれぞれ移動する。9回路及びn回路にバイアス電
流■3及び−■、がそれぞれ供給されると各動作点は5
2.62及び72にそれぞれ移動し、9回路のジョセフ
ソン回路素子40及び42が超伝導状態となりn回路の
ジョセフソン回路素子が電圧状態に切り換わり、この結
果Tの出力が生ずる。制御電流がIx=O,Iv=Tと
なると共にバイアス電流■、及び−■、が供給されると
、ジョセフソン回路素子40.42及びn回路のジョセ
フソン回路素子の動作点はそれぞれ点539点62及び
点73となる(尚、n回路のジョセフソン回路素子は制
御電流が■、たけ作用するので点72に対してAの制御
電流の位置となる)。この結果、3個のジョセフソン回
路素子が共に超伝導状態となり、従って0を出力する。When the control currents 8 and IY switch to T from this state, the operating points 50.60 and 70 change to the operating points 51.61 and 7.
1 respectively. When bias currents ■3 and -■ are supplied to the 9 circuit and the n circuit, respectively, each operating point becomes 5.
2.62 and 72, respectively, nine Josephson circuit elements 40 and 42 become superconducting and n Josephson circuit elements switch to a voltage state, resulting in an output of T. When the control current becomes Ix=O, Iv=T and the bias currents ■ and −■ are supplied, the operating points of the Josephson circuit element 40, 42 and the Josephson circuit element of the n circuit are respectively 539 points. 62 and point 73 (note that since the control current acts on the Josephson circuit element of n circuits as much as 1, the control current is at the position of A with respect to point 72). As a result, all three Josephson circuit elements become superconducting and therefore output a zero.
制御電流が■つ”1. Iy=下となると共にバイアス
電流I、l及び−I、がそれぞれ供給されると、各動作
点は点549点62及び点74となり、この結果2回路
は電圧状態となり、n回路は超伝導状態となり、従って
1が出力される。制御電流がIx=1.IY=Oとなる
と、各動作点はそれぞれ点541点63及び点75とな
り、この結果2回路が電圧状態となりn回路が超伝導状
態となり、従って1が出力される。制御電流がIx=1
+ h=tとなると、各動作点は点541点64及び点
76となり、この結果2回路は電圧状態となりn回路が
超伝導状態となり、従って1が出力される。更に、制御
電流IX=O,Iv=0となると9回路及びn回路共に
超伝導状態となり、従ってOが出力される。When the control current becomes ``1.Iy=lower'' and the bias currents I, l, and -I are respectively supplied, the operating points become points 549, 62, and 74, and as a result, the two circuits are in the voltage state. Therefore, the n circuit enters the superconducting state, and therefore outputs 1. When the control current becomes Ix = 1. IY = O, the operating points become points 541, 63, and 75, respectively, and as a result, the two circuits become voltage state, the n circuit becomes a superconducting state, and therefore 1 is output.The control current becomes Ix=1
+ When h=t, the respective operating points are points 541, 64, and 76, and as a result, two circuits are in a voltage state and n circuits are in a superconducting state, so that 1 is output. Furthermore, when the control currents IX=O and Iv=0, both the 9th circuit and the nth circuit become superconducting, and therefore, 0 is output.
このように2個の制御電流lx 、 Iyとバイアス電
流Is、Isを閾値特性に対して適切に選択することに
より、簡単な回路構成で表3に示す3値OR動作を実行
することができる。By appropriately selecting the two control currents lx and Iy and the bias currents Is and Is with respect to the threshold characteristics in this manner, the three-value OR operation shown in Table 3 can be performed with a simple circuit configuration.
なお、3値AND動作も3値OR回路と同様な動作によ
り実行することができる。Note that the ternary AND operation can also be performed by the same operation as the ternary OR circuit.
(発明の効果)
以上説明したように本発明によれば、9回路のジョセフ
ソン回路素子(超伝導回路素子)とn回路のジョセフソ
ン回路素子とを制御電流供給ラインで結合し、演算指令
に応じて3個の制御電流のいずれか1個の制御電流を各
ジョセフソン回路素子に供給し、9回路及びn回路から
超伝導状態又は電圧状態を出力させる構成としているの
で、簡単な回路構成で種々の3値論理演算を実行するこ
とができる。(Effects of the Invention) As explained above, according to the present invention, nine Josephson circuit elements (superconducting circuit elements) and n Josephson circuit elements are connected by a control current supply line, and arithmetic commands are Accordingly, one of the three control currents is supplied to each Josephson circuit element, and the superconducting state or voltage state is output from the 9 circuits and the n circuit, so the circuit structure is simple. Various ternary logic operations can be performed.
第1図は一重否定の論理演算を実行する3値論理演算回
路装置の一例の構成を示す回路図、第2図は第1図の3
値論理演算回路の闇値特性を示す線図、
第3図は否定論理演算を行なう場合の闇値特性を示す線
図、
第4図は3値OR論理演算を実行する3値論理演算回路
装置の一例の構成を示す回路図、第5図は第4図に示す
演算回路装置の闇値特性を示す線図、
第6図は従来の超伝導素子を有する2値論理演算回路の
構成を示す回路図、
第7図は第6図の2値論理演算回路の闇値特性を示す線
図である。
10・・・9回路 20・・・n回路J、、
J、、 J、、 J4・・・ジョゼフソン素子30・
・・制御信号入力端子
31、33.34・・・オフセント電流入力端子40、
42・・・ジョセフソン回路素子41、43・・・制御
信号入力端子
第2図
一制ずまF電動A)−
一%制御電う礼9JA)−
第3図
a
□ 制御電流 □
第5図
b
−電液IX −−電境Zy→
−を農IX、IY−FIG. 1 is a circuit diagram showing the configuration of an example of a ternary logic operation circuit device that executes a logical operation of single negation, and FIG.
A diagram showing the dark value characteristics of a value logic operation circuit. Figure 3 is a diagram showing the dark value characteristics when performing a negative logic operation. Figure 4 is a 3-value logic operation circuit device that performs a 3-value OR logic operation. A circuit diagram showing the configuration of an example, FIG. 5 is a diagram showing the dark value characteristics of the arithmetic circuit device shown in FIG. 4, and FIG. 6 shows the configuration of a conventional binary logic arithmetic circuit having a superconducting element. Circuit Diagram FIG. 7 is a diagram showing dark value characteristics of the binary logic operation circuit of FIG. 6. 10...9 circuits 20...n circuits J,,
J,, J,, J4... Josephson element 30.
...Control signal input terminals 31, 33.34...Offcent current input terminals 40,
42...Josephson circuit elements 41, 43...Control signal input terminals Fig. 2 - 1% control current 9JA) - Fig. 3 a □ Control current □ Fig. 5 b -Electrolyte IX--electrode Zy→-IX, IY-
Claims (1)
切り換わる超伝導素子を含む少なくとも1個以上の超伝
導回路素子を有する第1及び第2の演算回路を具え、第
1の演算回路の各超伝導回路素子と第2の演算回路の各
超伝導回路素子とを制御電流供給線で結合し、演算指令
に応じて値の異なる3個の制御電流のいずれか1個の制
御電流を制御電流供給線に供給して第1及び第2の演算
回路から超伝導状態又は電圧状態を出力させ、第1及び
第2の演算回路の出力に基いて3個の論理値のいずれか
1個を出力するように構成したことを特徴とする3値論
理演算回路装置。1. A first and a second arithmetic circuit having at least one superconducting circuit element including a superconducting element that switches between a superconducting state and a normal conducting state according to threshold characteristics; Each superconducting circuit element of the arithmetic circuit and each superconducting circuit element of the second arithmetic circuit are connected by a control current supply line, and any one of three control currents having different values is controlled according to an arithmetic command. Supplying current to the control current supply line to output a superconducting state or a voltage state from the first and second arithmetic circuits, and determining one of three logical values based on the outputs of the first and second arithmetic circuits. A ternary logic operation circuit device characterized in that it is configured to output one.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61244352A JPS6398220A (en) | 1986-10-15 | 1986-10-15 | Ternary logical operation circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61244352A JPS6398220A (en) | 1986-10-15 | 1986-10-15 | Ternary logical operation circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6398220A true JPS6398220A (en) | 1988-04-28 |
JPH0477487B2 JPH0477487B2 (en) | 1992-12-08 |
Family
ID=17117422
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61244352A Granted JPS6398220A (en) | 1986-10-15 | 1986-10-15 | Ternary logical operation circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6398220A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5361934A (en) * | 1976-11-16 | 1978-06-02 | Fujitsu Ltd | Ternary logical circuit using josephson junction device |
JPS585033A (en) * | 1981-07-01 | 1983-01-12 | Hitachi Ltd | Superconductive logical circuit |
-
1986
- 1986-10-15 JP JP61244352A patent/JPS6398220A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5361934A (en) * | 1976-11-16 | 1978-06-02 | Fujitsu Ltd | Ternary logical circuit using josephson junction device |
JPS585033A (en) * | 1981-07-01 | 1983-01-12 | Hitachi Ltd | Superconductive logical circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0477487B2 (en) | 1992-12-08 |
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