JPH0481020A - Ternary multiplication circuit device - Google Patents
Ternary multiplication circuit deviceInfo
- Publication number
- JPH0481020A JPH0481020A JP2190696A JP19069690A JPH0481020A JP H0481020 A JPH0481020 A JP H0481020A JP 2190696 A JP2190696 A JP 2190696A JP 19069690 A JP19069690 A JP 19069690A JP H0481020 A JPH0481020 A JP H0481020A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- arithmetic
- state
- superconducting
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005265 energy consumption Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000013016 damping Methods 0.000 description 3
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は超伝導素子を用いた3値の乗算を行なう演算回
路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic circuit device that performs three-value multiplication using superconducting elements.
(従来の技術)
超伝導素子を用いた3個演算回路としては、同じ出願人
により既に特開昭63−98220号(特願昭61−2
44352号)が開示されており、そこには第3図の回
路が提案されている。この図では、正の電圧状態を発生
するP回路lと負の電圧状態を発生させるn回路2とを
連結し、2回路の2個の制御信号電流線はn回路の2個
の制御信号電流線と方向が同じようになるように加えら
れている。図のJl、J2.J3.J4は例えばジョセ
フソン素子のような超伝導素子である。このような回路
では3値の二重否定や論理和演算(OR)は達成できる
が3僅の乗算を行なわせるためには、このようなOR演
算や二重否定のできる基本回路を複数個接続して演算を
行なわせなければならない。(Prior art) As a three-piece arithmetic circuit using superconducting elements, the same applicant has already published Japanese Patent Application Laid-Open No. 63-98220 (Patent Application No. 61-2).
No. 44352), in which the circuit shown in FIG. 3 is proposed. In this figure, a P circuit l that generates a positive voltage state and an n circuit 2 that generates a negative voltage state are connected, and the two control signal current lines of the two circuits are connected to the two control signal currents of the n circuit. They are added so that the lines and directions are the same. Jl, J2 in the figure. J3. J4 is a superconducting element such as a Josephson element. Such a circuit can perform 3-value double negation and logical sum operation (OR), but in order to perform 3-value multiplication, it is necessary to connect multiple basic circuits that can perform such OR operation and double negation. and then perform the calculation.
(発明が解決しようとする課題)
上述したジョセフソン素子を有する3個演算回路装置は
、否定、二重否定、OR,AND等の基本演算回路を行
なうことができる。しかし乗算のような一つのまとまっ
た機能を行なわせるためには上述の基本回路を複数個用
いなければならない。(Problems to be Solved by the Invention) The three arithmetic circuit device having the Josephson element described above can perform basic arithmetic circuits such as negation, double negation, OR, and AND. However, in order to perform a single integrated function such as multiplication, a plurality of the above-mentioned basic circuits must be used.
このため素子数や回路数も多くなり、また乗算を達成さ
せるための速度も遅くなる。This increases the number of elements and circuits, and also slows down the speed at which multiplication is accomplished.
従って、本発明の目的は上述した欠点を解消し、3個乗
算演算を基本回路装置−組を用いて高速で且つ低い消費
電力で行なうことができる演算回路を提供するものであ
る。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to eliminate the above-mentioned drawbacks and provide an arithmetic circuit that can perform three multiplication operations at high speed and with low power consumption using a basic circuit device set.
(課題を解決するだめの手段)
本発明による3個乗算回路装置は、闇値特性に応して超
伝導状態と常伝導状態との間で切り換わる超伝導素子を
含む少なくとも1個以上の超伝導回路素子を有する第1
及び第2の演算回路を具え、第1の演算回路の各超伝導
回路素子と第2の演算回路の各超伝導回路素子とを制御
電流供給線で結合し、演算指令に応して値の異なる3個
の制?Il電流のいずれか1個の制御電流を制御電流供
給線に供給して第1及び第2の演算回路から超伝導状態
又は電圧状態を出力させ、第1及び第2の演算回路の出
力に基いて3個の論理値のいずれか1個を出力するよう
に構成したことを特徴とするものである。(Means for Solving the Problem) A three-multiplying circuit device according to the present invention includes at least one superconducting element that switches between a superconducting state and a normal conducting state according to dark value characteristics. a first having a conductive circuit element;
and a second arithmetic circuit, each superconducting circuit element of the first arithmetic circuit and each superconducting circuit element of the second arithmetic circuit are coupled by a control current supply line, and a value is adjusted according to an arithmetic command. Three different systems? A control current of one of the Il currents is supplied to the control current supply line to cause the first and second arithmetic circuits to output a superconducting state or a voltage state, and based on the outputs of the first and second arithmetic circuits. The device is characterized in that it is configured to output any one of three logical values.
このように、第1及び第2の演算回路の各超伝導回路素
子の制御電流供給線をその方向が反対になるように結合
しているので、3個の制御電流値のうちいずれか1個の
制御電流を2本の制御線に供給することによって一つの
演算回路が超伝導状態であれば他の演算回路は電圧状態
となる組合せによって第1表の真理値表が示す乗算指示
に応した入力に対応した出力値を出力させる。この結果
簡単な回路構成で3値の乗算演算を実行することができ
る。In this way, since the control current supply lines of each superconducting circuit element of the first and second arithmetic circuits are coupled so that their directions are opposite, any one of the three control current values By supplying a control current of Output the output value corresponding to the input. As a result, a three-value multiplication operation can be performed with a simple circuit configuration.
第1表
(実施例)
第1図は本発明による3値乗算を行なう演算回路の一実
施例の構成を示す回路図である。本発明では正の電圧状
態を発生させるP回路30と負の電圧状態を発生させる
n回路40を制御電流供給ラインと抵抗R3とR4を介
して結合し、その中点に負荷インピーダンスRLとLL
を接続し、負荷抵抗に正、O1負の3種の電圧状態を出
力して3値乗算を実行する。制御電流供給ラインの端子
6から流れる電流の方向は、2回路とn回路は同し方向
であるが、端子7から流れる電流の方向は2回路とn回
路とでは方向が逆方向となっており、乗算を一ケの基本
素子で実行させることができる。Table 1 (Embodiment) FIG. 1 is a circuit diagram showing the configuration of an embodiment of an arithmetic circuit that performs three-value multiplication according to the present invention. In the present invention, a P circuit 30 that generates a positive voltage state and an N circuit 40 that generates a negative voltage state are coupled to a control current supply line via resistors R3 and R4, and load impedances RL and LL are connected to the middle point of the P circuit 30 that generates a positive voltage state and the N circuit 40 that generates a negative voltage state.
is connected, three voltage states, positive and O1 negative, are output to the load resistor to perform three-value multiplication. The direction of the current flowing from the terminal 6 of the control current supply line is the same for the 2nd circuit and the n circuit, but the direction of the current flowing from the terminal 7 is opposite for the 2nd circuit and the n circuit. , multiplication can be performed with one basic element.
P回路30は2ケのジョセフソン素子J5とJ6、制御
線と結合するためのインダクタンスLP5とLP6、ダ
ンピング抵抗R1、入力信号IXの電流をジョセフソン
素子に結合させる2ケのインダクタンスLP1. L
P2、入力信号IYの電流をジョセフソン素子に結合さ
せる2ケのインダクタンスLP3 LP4、また、こ
の素子に正のバイアス電流を流すための端子5をもって
いる。n回路40は2回路と同様に2ケのジョセフソン
素子J7とJ8、そのインダクタンスのL n5.
L n6、ダンピング抵抗R2、制御電流とジョセフソ
ン素子J7とJ8、そのインダクタンスのLn3とLn
4#よびLnlとLn2、負のバイアス電流を流すため
の端子8をもっている。The P circuit 30 includes two Josephson elements J5 and J6, inductances LP5 and LP6 for coupling to the control line, a damping resistor R1, and two inductances LP1. for coupling the current of the input signal IX to the Josephson elements. L
P2, two inductances LP3 and LP4 for coupling the current of the input signal IY to the Josephson element, and a terminal 5 for passing a positive bias current to this element. Similarly to the second circuit, the n circuit 40 includes two Josephson elements J7 and J8, and their inductance L n5.
L n6, damping resistor R2, control current and Josephson elements J7 and J8, and their inductances Ln3 and Ln
4#, Lnl and Ln2, and a terminal 8 for flowing a negative bias current.
第2図(a)および第2図(b)はP回路30およびn
回路40の各ジョセフソン素子の闇値特性を示す線図で
ある。2回路は+IBのバイアス電流が供給されている
ので、信号電流tXが加わらない状態では動作点はA点
にあり、n回路は−IBのバイアス電流が供給されてい
るのでD点にある。FIGS. 2(a) and 2(b) show the P circuit 30 and n
4 is a diagram showing the dark value characteristics of each Josephson element of the circuit 40. FIG. Since the 2nd circuit is supplied with a bias current of +IB, its operating point is at point A when no signal current tX is applied, and the operating point of the n circuit is at point D because it is supplied with a bias current of -IB.
この状態で制御電流IX、:!:IYに負の電流が流れ
ると2回路では制′a電流が負方向に2ケ加わるので動
作点はB点を経由して0点に移動し、2回路は正の方向
の電圧状態にスイッチする。n回路では、2本の制御線
がお互いに逆向きに接続されているので動作点はD点に
留まり超伝導状態のままである。したがって第1図の負
荷インピーダンスには正電圧が発生し、正の電流が流れ
る。次にIXの信号電流に負方向、IYの信号電流に正
方向電流を加えると2回路の第2図(a)では制御電流
が相殺されて動作点はA点のままで2回路は超伝導状態
、n回路の第2図(b)では、制御電流が負方向に加わ
るので動作点は、E点を経由してF点に移動しn回路は
負の電圧状態にスイッチする。したがって、負荷インピ
ーダンスの端子電流は、負電流となり、第1図のRLに
は負の電流が流れる。次に、IXとIYの信号電流に正
の電流が供給されると2回路の制御電流は正の方向に加
わるので動作点はA点からG点を経由してH点に移り、
2回路は正の電圧状態にスイッチする。n回路では、制
御電流は相殺されるので動作点はD点のままであり、超
伝導状態を維持する。したがって、負荷インピーダンス
の端子電圧は正電圧となり、負荷インピーダンスには正
の電流が流れる。In this state, the control current IX, :! :When a negative current flows through IY, two limiting currents are applied in the negative direction in the two circuits, so the operating point moves to the zero point via point B, and the two circuits switch to a positive voltage state. do. In the n-circuit, the two control lines are connected in opposite directions, so the operating point remains at point D and remains in the superconducting state. Therefore, a positive voltage is generated in the load impedance shown in FIG. 1, and a positive current flows. Next, when a negative direction current is added to the signal current of IX and a positive direction current is added to the signal current of IY, the control currents are canceled out in the two circuits shown in Figure 2 (a), the operating point remains at point A, and the two circuits become superconducting. In FIG. 2(b) of the n circuit, the control current is applied in the negative direction, so the operating point moves from point E to point F, and the n circuit switches to a negative voltage state. Therefore, the terminal current of the load impedance becomes a negative current, and a negative current flows through RL in FIG. Next, when a positive current is supplied to the signal currents of IX and IY, the control currents of the two circuits are added in the positive direction, so the operating point moves from point A to point H via point G.
2 circuits switch to a positive voltage state. In the n-circuit, the control currents cancel each other out, so the operating point remains at point D, maintaining the superconducting state. Therefore, the terminal voltage of the load impedance becomes a positive voltage, and a positive current flows through the load impedance.
制御信号IXとIYと共にO電流の場合には2回路もn
回路も超伝導状態のままで負荷インピーダンスの端子電
圧は0のままである。In the case of O current with control signals IX and IY, two circuits are also n
The circuit also remains in a superconducting state and the terminal voltage of the load impedance remains zero.
制御電流の零、正、負の各状態を0.−11とし、負荷
抵抗RLの端子電圧の零、正、負の各電圧状態をO,+
1.−1とすれば第1表に示す真理値表が得られ、乗算
演算を実行することができる。The zero, positive, and negative states of the control current are set to 0. −11, and the zero, positive, and negative voltage states of the terminal voltage of the load resistor RL are O, +
1. If it is set to -1, the truth table shown in Table 1 is obtained, and the multiplication operation can be executed.
第1図は本発明による3値乗算を行なう演算回路の一実
施例の構成を示す回路図であり、第2図(a)および第
2図(b)はそれぞれ2回路およびn回路の各ジョセフ
ソン素子の闇値特性を示す線図であり、
第3図は従来技術による超伝導素子を用いた3値演算回
路の回路図である。
1.30・・・2回路
2.40・・・n回路
5・・・正のバイアス電流を流すための端子6.7・・
・制御電流供給ラインの端子8・・・負のバイアス電流
を流すための端子JL J2. J3. J4. J5
. J6. J7. J8・・・ジョセフソン素子
Lnl、 Ln2. Ln3. Ln4. Ln5.
Ln6. Lpl+ Lp2Lp6・・・インダクタン
ス
LL、RL・・・負荷インピーダンス
R1,R2・・・ダンピング抵抗
R3,R4・・・抵抗
Lp3. Lp4. Lp5FIG. 1 is a circuit diagram showing the configuration of an embodiment of an arithmetic circuit that performs three-value multiplication according to the present invention, and FIG. 2(a) and FIG. 2(b) are each Joseph FIG. 3 is a diagram showing the dark value characteristics of a superconducting element, and FIG. 3 is a circuit diagram of a three-value arithmetic circuit using a superconducting element according to the prior art. 1.30...2 circuits 2.40...n circuit 5...Terminal for flowing positive bias current 6.7...
- Terminal 8 of control current supply line...Terminal JL for flowing negative bias current J2. J3. J4. J5
.. J6. J7. J8...Josephson element Lnl, Ln2. Ln3. Ln4. Ln5.
Ln6. Lpl+ Lp2Lp6...Inductance LL, RL...Load impedance R1, R2...Damping resistance R3, R4...Resistance Lp3. Lp4. Lp5
Claims (1)
わる超伝導素子を含む第1および第2の演算回路を連結
し、第1回路の制御電流供給線を第2回路の制御電流供
給線に接続するときはお互いに電流方向が逆になるよう
に接続し、3値の乗算指令に応じて値の異なる3個の制
御電流のいずれか1個の制御電流を制御電流供給線に供
給して一つの演算回路が超伝導状態なら他の演算回路は
電圧状態になるように制御して3値の乗算動作の出力を
出力するように構成したことを特徴とする3値乗算回路
装置。1. Connect the first and second arithmetic circuits including a superconducting element that switches between a superconducting state and a normal conducting state according to threshold characteristics, and connect the control current supply line of the first circuit to the control current supply line of the second circuit. When connecting to the line, connect them so that the current directions are opposite to each other, and supply one of the three control currents with different values to the control current supply line according to the three-value multiplication command. A ternary multiplication circuit device characterized in that, if one arithmetic circuit is in a superconducting state, the other arithmetic circuits are controlled to be in a voltage state and output an output of a ternary multiplication operation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2190696A JPH06101680B2 (en) | 1990-07-20 | 1990-07-20 | Ternary multiplication circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2190696A JPH06101680B2 (en) | 1990-07-20 | 1990-07-20 | Ternary multiplication circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0481020A true JPH0481020A (en) | 1992-03-13 |
JPH06101680B2 JPH06101680B2 (en) | 1994-12-12 |
Family
ID=16262335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2190696A Expired - Fee Related JPH06101680B2 (en) | 1990-07-20 | 1990-07-20 | Ternary multiplication circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06101680B2 (en) |
-
1990
- 1990-07-20 JP JP2190696A patent/JPH06101680B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH06101680B2 (en) | 1994-12-12 |
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