JPS6339025A - Parallel interface circuit for printer - Google Patents

Abstract

PURPOSE:To secure the simple connection to two host devices by using a switch circuit which switches the joint part of two systems connected to those host devices and connects both systems. CONSTITUTION:A parallel interface circuit set between a host device and a printer contains connectors INFA(IN)2 and INFA(OUT)28 connected to one of two host devices, connectors INFB(IN)1 and INFB(OUT)27 connected to the other host device, and a switch 11 which decides connection to either one of both host devices. The output signal delivered from the switch 11 fixes the signal outputted from the INFB27 at 1 and 0 via OR circuits 19 and 20 and AND circuits 21 and 22 respectively when the switch 11 is turned off. Thus the logical connection is cut between the INFB27 and the host device. Then the other INFA28 only can have the logical connection to the host device set at the other side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel interface circuit for a printer, and more particularly to a parallel interface circuit for a print having a switching circuit for switching a connection with a host device.

[Conventional technology]

Conventionally, the parallel interface circuit of this type of printer has a control circuit 5 for controlling the printer, as shown in FIG.
7 and a connection section 51.59 connected to the host device, and data from the host device is sent to the connection section 51.59. is supplied to the control circuit 57 via the latch circuit 53, and the control circuit 57
The control signal from the controller is configured to be supplied to the host device via the connection section 59.

[Problem that the invention seeks to solve]

The conventional printer interface circuit described above has only one set of connection parts with the host device, so it has the disadvantage that a printer must be prepared for each host device or the connection must be changed each time the printer is used. There is.

[Means for solving problems]

A parallel interface circuit for a printer according to the present invention is an interface circuit connected between a host device and a printer, and is logically connected to one connection section and connected to at least two systems connected to the host device, and the other The connection section has a switching circuit that logically establishes a non-contact state and sends a signal indicating the non-connection state to the host device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a parallel interface circuit which is an embodiment of the present invention. In FIG. 1, this embodiment is a parallel interface circuit provided between a host device and a printer, and a connection connected to one host device, a connector IN.
Connector INFB that connects FA (IN>2 and INFA (OUT>28) to another host device.
(IN)1, INFB (OUT>27), and a switching circuit having a switch 11 that switches which host device to connect to, and when the switch 11 is OFF, it is connected to the connection connector INFA side, and the switch 11 When is ON, it is configured to be connected to the connection connector INFB side.

One connector 1 connected to the host device is data 1
02 to the control circuit 17 via the latch circuit 9 and further via the internal bus 108, and the other connection connector 2, which is further connected to the Ike's binary device, is connected to supply data 1 to the control circuit 17 via the latch circuit 9.
04 is connected to the latch circuit 10 through an internal bus 108 to the control circuit 17. Connector 1 ORs strobe (STB) signal 101, circuit 7,
The connector 2 is connected to the NAND circuit 14 of the latch circuit via the AND circuit 12, and the connector 2 connects the probe 1-lobe (SBT) signal 103 to the OR circuit 8 and the AND circuit 12.
It is connected to the NAND AND circuit 14 of the latch circuit through. A NAND AND circuit 14112 is connected to be supplied to the control circuit 17 and the OR circuit 18 . OR circuit 18 is connected to supply signal 114 to OR circuit 19.23.

The control circuit 17 supplies the signal 113 to the OR circuit 18 and also outputs the signal 113 to the NANDAN of the latch circuit via the INV circuit 16.
D circuit 15 is installed. The control circuit 17 outputs the signal 115 to O.
R circuits 20 and 24, and signal 116 is supplied to AND circuit 2.
2.25 and the signal 117 to the AND circuit 2.1.2.
6.

The control circuit 17 is connected to supply the read pulse 109 to the GE terminals of the latch circuits 9 and 10 via the OR circuit 3.4.

The switch 11 inputs the input signal 111 to the OR circuit 7, IN
is supplied to the GE terminal of the latch circuit 9 via the V circuit 5,
Furthermore, the input signal 111 is connected to be supplied to the OR circuit 3 via the input signal 111. The switch 11 is supplied with the signal 110 of the INV circuit 13 to the OR circuit 4.8, and the output signal 106 of the OR circuit 8 is supplied to the latch circuit 10 via the TNV circuit 6.
It is connected so that it is supplied to the GE terminal of. The input signal 111 of this switch 11 is the OR circuit 19, 20, A
The signal 110 is connected to be supplied to the AND circuits 21, 22 . It is connected to be supplied to OR circuits 23 and 24. OR circuit 19.20
AND circuits 21, 22 are connected to supply each control signal to the connector 27, and OR circuits 23, 24
and AND circuits 25 and 26 are connected to supply each control signal to the connection connector 28.

Next, to explain the operation of this embodiment, STB signals 101 and 103 are LOW active strobe signals for receiving data 102 and 104 from the host device, and BUSY signals 118 and 122 are LOW active strobe signals for receiving data 102 and 104 from the host device.
This signal indicates SY/READY and indicates the BUSY state at the 1° level. ACK signals 119 and 123 are LOW active stroke signals indicating a data request to the host device. DCK signals 120 and 124 are device connect signals indicating connection of the printer, and are "1".
Indicates that the level is connected.

FAULT signals 121 and 125 indicate whether or not there is an abnormality in the printer, and are signals that indicate a normal state at the "°" level.

The operation when the switch 11 is OFF and the host devices on the connectors 2 and 28 are connected will be described with reference to the time chart during data transfer shown in FIG. For the data 104 from the connector 2, one input signal 110 of the OR circuit 8 is 0'.

Since the STB signal 103 is at a low active stroke level, it is latched into the latch circuit 10 by the LOW active stroke of the STB signal 103.

Since one input signal 111 of the OR circuit 7 is at the "'1" level, one input signal 105 of the AND circuit 12 is at the "'1" level.
1" level, the strobe signal 106 is latched by a latch circuit consisting of NAND circuits 14 and 15, and its output signal 112 becomes "1" level, and the BUSY signal 12
2 becomes the "1" level. The control circuit 17 recognizes the input of data when the signal 112 is at the "1" level, and resets the latch circuit consisting of the NAND circuits 14 and 15 by setting the signal 113 to the "1" level, and also outputs the BUSY signal 122. 1'' level, outputs the LOW active READ pulse 109, and reads the input data latched in the latch circuit 10 via the internal bus 108. At this time, one input signal 111 of the OR circuit 3 is at the "1" level. Therefore, the data of the latch circuit 9 is not output to the internal bus 108.

By setting the signal 113 to the "0" level after reading the data, one input signal 110 is set to the "O" level. The control circuit 17 receives the BUSY signal 12 via the OR circuit 23.
2 is set to 0'' level, and the signal 115 outputs a LOW active ACK signal 123 via the OR circuit 24 to request the next data.

The control circuit 17 outputs signals 116 and 1 during normal data transfer.
17 is set to “1” level, and one input signal 111 is set to “1” level.
"DCN through AND circuits 25 and 26 which are the level
The signal 124 and the FAULT signal 125 are set to "1" level. Also, when an abnormality occurs, signals 116 and 117 are set to 0.
" level, DCN signal 124 and FAULT signal 1
25 to °'O" level and signal 113 to "1".
level, and the BUSY signal 122 is set to "1" level.

On the other hand, even if a strobe pulse is erroneously input to the STB signal 101, one input signal 111 of the OR circuit 7 becomes ``1''.
” level, the signal 105 remains at the “1” level and is ignored. Since the input signal 111 of one of the OR circuits 19 and 20 is at the “1” level, the BUSY signal 1
18 and ACK signal remain at “1pa level,” and the AN
Since the input signal 110 of one of the D circuits 21 and 22 is at the 'O' level, the DCK signal 120 and the FAUFT signal 1
21 becomes 0" level, indicating that it is not logically connected to the host device connected to the connection connector 1.27 side. When the switch 11 is ON, the host device of the connection connector 1.27@ It is the same as the case of OFF except that is connected.

[Effects of the Invention] As described above, the present invention has the advantage that it has at least two connection parts with higher-level devices and has a switching circuit therefor, so that it can be easily connected to two higher-level devices at low cost.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a time chart in this embodiment, and FIG. 3 is a diagram showing a conventional interface circuit. 1.2.17.28...Connector, 3.4°7.
8, 18.19, 20.23.24...OR circuit, 5
, 6, 13. 16... INV circuit, 9, 10... Latch circuit, 11... Switch, 12, 21, 22.2
5.26...AND circuit, 14.15...NAND
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Claims (1)

[Claims] In an interface circuit that connects a host device and a printer, one connection section is logically connected to at least two connections connected to the host device, and the other connection section is logically disconnected. 1. A parallel interface circuit for a printer, comprising: a switching circuit for transmitting a signal indicating a non-contact state to a host device;