JPS628007B2 - - Google Patents

Info

Publication number
JPS628007B2
JPS628007B2 JP55047345A JP4734580A JPS628007B2 JP S628007 B2 JPS628007 B2 JP S628007B2 JP 55047345 A JP55047345 A JP 55047345A JP 4734580 A JP4734580 A JP 4734580A JP S628007 B2 JPS628007 B2 JP S628007B2
Authority
JP
Japan
Prior art keywords
semiconductor layer
silicon semiconductor
contact window
polycrystalline
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55047345A
Other languages
Japanese (ja)
Other versions
JPS56144530A (en
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4734580A priority Critical patent/JPS56144530A/en
Publication of JPS56144530A publication Critical patent/JPS56144530A/en
Publication of JPS628007B2 publication Critical patent/JPS628007B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678—Beam shaping, e.g. using a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 本発明は、素子を立体的に構成することに依り
高密化した多層構造半導体装置を製造するのに好
適な方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method suitable for manufacturing a highly dense multilayer structure semiconductor device by three-dimensionally configuring elements.

近年、絶縁膜上に成長させた多結晶シリコン或
いは非晶質シリコンなどをレーザ・アニールして
単結晶化し、そこに素子を形成することに依り、
所謂SOS（Silicon on Sapphire）類似の半導体
装置を得ることができるようになつた。 In recent years, by laser annealing polycrystalline silicon or amorphous silicon grown on an insulating film to make it a single crystal, and forming devices there,
It has become possible to obtain semiconductor devices similar to so-called SOS (Silicon on Sapphire).

このようなことが可能になると、前記のように
して素子を形成した上に更に二酸化シリコンなど
の絶縁膜及びレーザ・アニールに依り単結晶化し
たシリコン層などを多層に形成して素子を立体的
に作り込み高集積化した半導体装置を得ることが
できるようになる。 If this becomes possible, it will be possible to form a three-dimensional device by forming multiple layers of an insulating film such as silicon dioxide and a single-crystal silicon layer by laser annealing on top of the device formed as described above. This makes it possible to obtain highly integrated semiconductor devices.

そのような場合、シリコン半導体基板、第１
層、第２層………の各シリコン半導体層は電気的
に接続されなければならない。 In such a case, the silicon semiconductor substrate, the first
Each silicon semiconductor layer of layer, second layer, etc. must be electrically connected.

本発明は、前記のような多層構造の半導体装置
を製造する場合の前記電気的接続を容易且つ確実
に行ない得るようにするものであり、以下これを
詳細に説明する。 The present invention enables the electrical connection to be easily and reliably made when manufacturing a semiconductor device having a multilayer structure as described above, and will be described in detail below.

第１図乃至第５図は本発明一実施例を説明する
為の工程要所に於ける半導体装置の要部側断面図
であり、次に、これ等の図を参照しつつ記述す
る。 1 to 5 are side sectional views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

第１図参照 (1) n+型シリコン半導体基板１に熱酸化法を適
用して二酸化シリコンからなる第１層目絶縁層
２を厚さ１〔μｍ〕程度に形成し、それを通常
のフオト・リソグラフイ技術にてパターニング
してコンタクト窓を形成する。Refer to Figure 1 (1) Apply a thermal oxidation method to an n + type silicon semiconductor substrate 1 to form a first insulating layer 2 made of silicon dioxide to a thickness of about 1 [μm], and then apply a thermal oxidation method to the n - Form a contact window by patterning using lithography technology.

(2) 化学気相成長法を適用して多結晶シリコン半
導体層３を厚さ0.5〔μｍ〕程度に成長させ
る。(2) Apply chemical vapor deposition to grow polycrystalline silicon semiconductor layer 3 to a thickness of about 0.5 [μm].

第２図参照 (3) 蒸着法を適用してアルミニウム膜を形成し、
それを通常のフオト・リソグラフイ技術にてパ
ターニングしてコンタクト窓領域を覆うマスク
４を形成する。See Figure 2 (3) Form an aluminum film by applying the vapor deposition method,
This is patterned using a conventional photolithography technique to form a mask 4 covering the contact window region.

(4) レーザ・ビームを照射して多結晶シリコン半
導体層３を単結晶シリコン半導体層３′に変換
する。尚、マスク４に覆われたコンタクト窓領
域の部分は多結晶シリコンのままであることは
当然である。(4) Convert the polycrystalline silicon semiconductor layer 3 into a single-crystalline silicon semiconductor layer 3' by irradiating with a laser beam. It goes without saying that the contact window region covered by the mask 4 remains polycrystalline silicon.

第３図参照 (5) マスク４を除去してから、気相成長法を適用
し、厚さ１〔μｍ〕程度の二酸化シリコンから
なる第２層目絶縁層５を形成し、これを通常の
フオト・リソグラフイ技術にてパターニングし
てコンタクト窓を形成する。See Figure 3 (5) After removing the mask 4, a vapor phase growth method is applied to form a second insulating layer 5 made of silicon dioxide with a thickness of approximately 1 [μm]. A contact window is formed by patterning using photolithography technology.

(6) 化学気相成長法を適用して多結晶シリコン半
導体層６を厚さ0.5〔μｍ〕程度に成長させ
る。(6) Apply chemical vapor deposition to grow polycrystalline silicon semiconductor layer 6 to a thickness of about 0.5 [μm].

第４図参照 (7) 前記工程３と同様にしてマスク７を形成す
る。See FIG. 4 (7) A mask 7 is formed in the same manner as in step 3 above.

(8) レーザ・ビームを照射して多結晶シリコン半
導体層６を単結晶シリコン半導体層６′に変換
する。この場合も、マスク７の下になつている
部分は多結晶シリコンのまま残る。(8) Convert the polycrystalline silicon semiconductor layer 6 into a single-crystalline silicon semiconductor layer 6' by irradiating the laser beam. In this case as well, the portion under the mask 7 remains as polycrystalline silicon.

第５図参照 (9) マスク７を除去してから、今度は残留してい
る多結晶シリコン半導体層６を露出し、単結晶
シリコン半導体層６′を覆うマスクを形成す
る。Refer to FIG. 5 (9) After removing the mask 7, the remaining polycrystalline silicon semiconductor layer 6 is exposed and a mask covering the single crystal silicon semiconductor layer 6' is formed.

(10) イオン注入法（或いは気相拡散法など適宜の
技法）を適用し、例えば燐イオンのデポジシヨ
ンを行ない拡散させると、多結晶シリコンは結
晶グレインが小さいので不純物の拡散は急速に
進行し、多結晶シリコン半導体層６，３を介
し、シリコン半導体基板１に達する。(10) When applying an ion implantation method (or an appropriate technique such as a vapor phase diffusion method) to deposit and diffuse phosphorus ions, for example, polycrystalline silicon has small crystal grains, so impurity diffusion progresses rapidly. It reaches the silicon semiconductor substrate 1 via the polycrystalline silicon semiconductor layers 6 and 3.

このようにして、シリコン半導体基板１、単結
晶シリコン半導体層３′、単結晶シリコン半導体
層６′は多結晶シリコン半導体層３，６を介して
容易且つ確実に電気接続されるものである。単結
晶シリコン半導体層３′に配線或いは素子を形成
するには工程中の適当な時期を選んで行なえば良
く、また、前記実施例の如く、２層構成であれ
ば、単結晶シリコン半導体層６′には通常の従来
技術を適用して素子を形成できる。尚、第５図に
は単結晶シリコン半導体層６′に通常のMIS電界
効果トランジスタを形成した状態が表わされてい
て、８はゲート酸化膜、９はシリコン・ゲート電
極、１０Ｓはn+型ソース領域、１０Ｄはn+型ド
レイン領域を示している。 In this way, silicon semiconductor substrate 1, single crystal silicon semiconductor layer 3', and single crystal silicon semiconductor layer 6' are easily and reliably electrically connected via polycrystalline silicon semiconductor layers 3 and 6. To form wiring or elements on the single crystal silicon semiconductor layer 3', it is only necessary to select an appropriate time during the process, and if the structure is two layers as in the above embodiment, the single crystal silicon semiconductor layer 6 ' can be formed by applying ordinary conventional techniques. Incidentally, FIG. 5 shows a state in which an ordinary MIS field effect transistor is formed in a single crystal silicon semiconductor layer 6', where 8 is a gate oxide film, 9 is a silicon gate electrode, and 10S is an n + type transistor. The source region and 10D indicate an n + type drain region.

以上の説明で判るように、本発明に依れば、シ
リコン半導体基板上に絶縁層及び多結晶（或いは
非晶質）シリコン半導体層をレーザ・アニールし
て得た単結晶シリコン半導体層を多層に形成し、
それ等単結晶シリコン半導体層に素子を形成する
ようにした半導体装置の製造方法に於いて、前記
絶縁層にコンタクト窓を形成してから多結晶（或
いは非晶質）シリコン半導体層を形成し、コンタ
クト窓領域をマスクで覆つてからレーザ・アニー
ルを行なつて該シリコン半導体層を単結晶シリコ
ン半導体層に変換する工程を前記コンタクト窓を
位置合せして複数回繰返すことに依り多層化し、
そのコンタクト窓領域に残留する多結晶（或いは
非晶質）シリコン層に不純物を導入して各単結晶
シリコン半導体層を電気的に接続するようにして
いる。多結晶シリコンは単結晶シリコンに比較し
てグレインが小さく、また、非晶質は勿論結晶で
はないから、導入された不純物は僅かの熱処理で
急速に拡散され、各単結晶シリコン半導体層を容
易且つ確実に電気接続することができる。ここ
で、接続に使用する多結晶シリコン半導体層は、
必然的に形成されるものを利用するのであるか
ら、その実施は容易である。 As can be seen from the above description, according to the present invention, a single crystal silicon semiconductor layer obtained by laser annealing an insulating layer and a polycrystalline (or amorphous) silicon semiconductor layer on a silicon semiconductor substrate is formed into a multilayer structure. form,
In such a method of manufacturing a semiconductor device in which an element is formed in a single crystal silicon semiconductor layer, a contact window is formed in the insulating layer, and then a polycrystalline (or amorphous) silicon semiconductor layer is formed, multilayering by aligning the contact windows and repeating the step of covering the contact window region with a mask and then performing laser annealing to convert the silicon semiconductor layer into a single crystal silicon semiconductor layer a plurality of times;
Impurities are introduced into the polycrystalline (or amorphous) silicon layer remaining in the contact window region to electrically connect the single crystal silicon semiconductor layers. Polycrystalline silicon has smaller grains than single-crystal silicon, and since polycrystalline silicon is of course not crystalline, the introduced impurities can be rapidly diffused with a small amount of heat treatment, making it easy to form each single-crystal silicon semiconductor layer. A reliable electrical connection can be made. Here, the polycrystalline silicon semiconductor layer used for connection is
It is easy to implement because it uses something that is naturally formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第５図は本発明一実施例を説明する
為の工程要所に於ける半導体装置の要部側断面図
である。 図に於いて、１はシリコン半導体基板、２は絶
縁膜、３は多結晶シリコン半導体層、３′は単結
晶シリコン半導体層、４はマスク、５は絶縁膜、
６は多結晶シリコン半導体層、６′は単結晶シリ
コン半導体層である。 1 to 5 are side cross-sectional views of essential parts of a semiconductor device at important points in the process for explaining one embodiment of the present invention. In the figure, 1 is a silicon semiconductor substrate, 2 is an insulating film, 3 is a polycrystalline silicon semiconductor layer, 3' is a single crystal silicon semiconductor layer, 4 is a mask, 5 is an insulating film,
6 is a polycrystalline silicon semiconductor layer, and 6' is a single crystal silicon semiconductor layer.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体基板上にコンタクト窓を有する絶縁膜
を形成してから多結晶半導体層を形成し、該多結
晶半導体層のコンタクト窓領域部分を覆うマスク
を形成してからレーザ・アニールを行なつて前記
多結晶半導体層の露出部分を単結晶化する工程、
更に、前記コンタクト窓に位置合せされたコンタ
クト窓を有する絶縁膜を形成してから多結晶半導
体層を形成し、該多結晶半導体層のコンタクト窓
領域部分を覆うマスクを形成してからレーザ・ア
ニールを行なつて単結晶化する工程を少なくとも
１回実施し、しかる後、コンタクト窓領域部分に
残留している多結晶半導体層に不純物を導入して
前記半導体基板及び各単結晶半導体層を電気的に
接続する工程を含んでなることを特徴とする半導
体装置の製造方法。1. Form an insulating film having a contact window on a semiconductor substrate, then form a polycrystalline semiconductor layer, form a mask covering the contact window region of the polycrystalline semiconductor layer, and then perform laser annealing. a step of converting the exposed portion of the polycrystalline semiconductor layer into a single crystal;
Furthermore, an insulating film having a contact window aligned with the contact window is formed, a polycrystalline semiconductor layer is formed, a mask is formed to cover the contact window region of the polycrystalline semiconductor layer, and then laser annealing is performed. After that, an impurity is introduced into the polycrystalline semiconductor layer remaining in the contact window region to electrically connect the semiconductor substrate and each single-crystalline semiconductor layer. 1. A method for manufacturing a semiconductor device, comprising the step of connecting to.
JP4734580A 1980-04-10 1980-04-10 Manufacture of semiconductor device Granted JPS56144530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4734580A JPS56144530A (en) 1980-04-10 1980-04-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4734580A JPS56144530A (en) 1980-04-10 1980-04-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS56144530A JPS56144530A (en) 1981-11-10
JPS628007B2 true JPS628007B2 (en) 1987-02-20

Family

ID=12772564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4734580A Granted JPS56144530A (en) 1980-04-10 1980-04-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56144530A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5890763A (en) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp Semiconductor device
JPS5892257A (en) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp Semiconductor device
JPS5893372A (en) * 1981-11-30 1983-06-03 Toshiba Corp Mos-type integrated circuit
JP4193206B2 (en) * 2001-07-25 2008-12-10 セイコーエプソン株式会社 Semiconductor thin film manufacturing method, semiconductor device manufacturing method, semiconductor device, integrated circuit, electro-optical device, and electronic apparatus
JP5094099B2 (en) * 2006-12-04 2012-12-12 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS56144530A (en) 1981-11-10

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