JPH0235710A - Forming method for thin film semiconductor layer - Google Patents
Forming method for thin film semiconductor layerInfo
- Publication number
- JPH0235710A JPH0235710A JP18606188A JP18606188A JPH0235710A JP H0235710 A JPH0235710 A JP H0235710A JP 18606188 A JP18606188 A JP 18606188A JP 18606188 A JP18606188 A JP 18606188A JP H0235710 A JPH0235710 A JP H0235710A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- thin film
- film
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000010409 thin film Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 40
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 40
- 239000010408 film Substances 0.000 claims abstract description 35
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 241000293849 Cordylanthus Species 0.000 abstract description 11
- 238000002955 isolation Methods 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000007787 solid Substances 0.000 abstract 2
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229910005091 Si3N Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 206010004950 Birth mark Diseases 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 which is active JfJ Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄ＩＩ？半導体調の形成方法に関するもので
ある。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to thin II? The present invention relates to a semiconductor-like forming method.
本発明は薄映半導体層の形成方法において、絶縁性基板
上に非単結晶薄膜半導体層を形成し、該半導体ｌＷ４上
に選択的に耐酸化膜を形成する。その後、酸化性雰囲気
中で全面にエネルギービームを照射して露出している半
導体ｊ−を酸化すると共に、制酸化膜下の半導体層を熱
処理することにより、活性Ｊ＠となる半導体層の固相成
長と同時に素子骨＋１０１１領域となる選択酸化（ＬＯ
ＧＯ３’）層の形成を可能にし、且つバースビークのな
い選択酸化層形成を−り能にしたものである。The present invention is a method for forming a thin film semiconductor layer, in which a non-single crystal thin film semiconductor layer is formed on an insulating substrate, and an oxidation-resistant film is selectively formed on the semiconductor IW4. After that, the entire surface is irradiated with an energy beam in an oxidizing atmosphere to oxidize the exposed semiconductor j-, and the semiconductor layer under the anti-oxidation film is heat-treated to form a solid phase of the semiconductor layer that becomes active J@. Selective oxidation (LO
This makes it possible to form a GO3') layer and to form a selective oxidation layer without birthmarks.
一般に、半導体装置、特に薄膜半導体装置を形成する場
合、ゲート絶縁物として、また容量としであるいは素子
分離時の耐酸化マスクとしてＳｉ３Ｎ２股が用いられて
いる。このＳ＋３Ｎ４膜は誘電率が大きく耐酸化性、耐
薬品性に優れ、上記用途として通している。また、ゲー
ト絶縁物を容量として使う場合、Ｓ ｉＪ ４ Ｃは単
独としては使われず５ｉＯ２ＳｉｊＮ４Ｓｉｆ２のサン
ドイッチ構造にする場合が多い。Generally, when forming a semiconductor device, especially a thin film semiconductor device, Si3N bifurcated material is used as a gate insulator, a capacitor, or an oxidation-resistant mask during element isolation. This S+3N4 film has a large dielectric constant and excellent oxidation resistance and chemical resistance, and is accepted for the above-mentioned applications. Furthermore, when using the gate insulator as a capacitor, S iJ 4 C is not used alone, but a sandwich structure of 5iO2SijN4Sif2 is often used.
また、半導体築槓回路における素子分離の寸法として、
ＳＳ１０２Ｓｉ３Ｎ４を耐酸化マスクとじて用い素子部
以外を熱酸化するいわゆるＬｏｃｕｓ法（選択酸化法）
が主流になっている。In addition, as the dimension of element separation in a semiconductor construction circuit,
The so-called Locus method (selective oxidation method) uses SS102Si3N4 as an oxidation-resistant mask to thermally oxidize areas other than the element part.
has become mainstream.
また、薄膜半導体装置等の多結晶シリコンによる活性ｒ
−を結晶改善する方法としてエキシマレーザを照４・ｊ
シて結晶成長させるという方法も知られている。In addition, the activation of polycrystalline silicon in thin film semiconductor devices
Excimer laser light is used as a method to improve the crystallization of -4.j
A method of growing crystals by cutting is also known.
（発明が解決しようとする課題〕
ところで、半導体装置において、上記ＳｉＳｉ３Ｎ４を
ゲート絶縁膜や容着として使う場合、上述のように５ｉ
Ｏ２Ｓｉ３Ｎ＋ ５ｉ０２のサントイツナ構造にし
ているが、この上部の５ｉ（ｂ １％ｊはＳｉｓＮ４Ｍ
！Ｑ表面を約１１００℃で熱酸化して形成される。この
熱酸化処理は通常、塩気炉内において行なっていたため
、この熱酸化時に活性ＪｆＪである単結晶シリコンノル
仮中に欠陥が生じたり、不純物が拡散する等の不都合が
あった。(Problems to be Solved by the Invention) By the way, when using the above-mentioned SiSi3N4 as a gate insulating film or adhesive in a semiconductor device, the 5i
The structure is O2Si3N+ 5i02, but the upper 5i (b 1%j is SisN4M
! It is formed by thermally oxidizing the Q surface at about 1100°C. Since this thermal oxidation treatment is usually carried out in a salt air furnace, there are disadvantages such as defects occurring in the monocrystalline silicon precipitate, which is active JfJ, and impurities diffusing during this thermal oxidation.
一方、１、ｏｃｏｓ法による素子分離においては、所謂
バーズビークの問題があり、バーズビークのない選択酸
化層の形成が望まれている。On the other hand, in element isolation using the 1. ocos method, there is a problem of so-called bird's beak, and it is desired to form a selective oxidation layer without bird's beak.
また、エキシマレーザ照射による活性層の結晶成長につ
いては、照射時に活性層の多結晶シリコン上を５ｉ（ｂ
欣等でキャンピングする必要がある。Regarding crystal growth of the active layer by excimer laser irradiation, 5i (b
It is necessary to camp in Shin etc.
本発明は、このような点に鑑み成されたもので、その目
的とすることころは活性層の結晶成長と素子分離のため
の選択酸化層の形を同時に行なってし程の簡略化を図る
と共に、バーズビークのない選択酸化ｊ脅の形成を可能
にした薄膜半導体層の形成方法を提供することにある。The present invention has been made in view of these points, and its purpose is to simultaneously grow the crystals of the active layer and form the selective oxidation layer for element isolation, thereby simplifying the process. Another object of the present invention is to provide a method for forming a thin film semiconductor layer that enables selective oxidation formation without bird's beaks.
本発明の１ＷＩＩＷ半導体層の形成方法は、絶縁性基板
（１）上に多結晶又は非晶質の非単結晶薄膜半導体Ｉｎ
＋２１を形成し、該ス導体層（２）上に選択的にＳ
ｉ ）Ｎ ４等の耐酸化膜（４）を形成する。その後、
酸化性雰囲気中で全面にエキシマレーザ−等の工フルギ
ービームを照射して露出している半導体層（２）を選択
酸化Ｊると共に、耐酸化９９＋４１下の半導体１ｍ （
２１を熱処理するようにしたものである。The method for forming a 1WIIW semiconductor layer of the present invention is to form a polycrystalline or amorphous non-single crystal thin film semiconductor In on an insulating substrate (1).
+21 and selectively S on the S conductor layer (2).
i) Form an oxidation-resistant film (4) such as N4. after that,
In an oxidizing atmosphere, the exposed semiconductor layer (2) is selectively oxidized by irradiating the entire surface with a mechanical beam such as an excimer laser.
21 was heat-treated.
上述の本発明の形成方法によれば、酸化性雰囲気中でエ
ネルギービームを高温・短時間照射するので、活性層で
ある非単結晶薄膜半導体ｒｆ４（２１の耐酸化膜（４）
が形成されない領域が選択酸化され、ここに素子分離領
域となる選択酸化層（６１が形成されると共に、同時工
程で耐酸化膜（４）下の活性層となる非単結晶薄膜半導
体層（２）が固相成従する。この面相成長に際しては、
耐酸化膜（４）がキャンピング（−として作用するので
、キャツピング層の形成工程が省略される。According to the above-described formation method of the present invention, since the energy beam is irradiated at high temperature and for a short time in an oxidizing atmosphere, the non-single crystal thin film semiconductor rf4 (oxidation-resistant film (4) of 21) which is the active layer
The regions where the oxidation-resistant film (4) is not formed are selectively oxidized, and a selective oxidation layer (61) which becomes an element isolation region is formed therein, and at the same time, a non-single crystal thin film semiconductor layer (2) which becomes an active layer under the oxidation-resistant film (4) is formed. ) becomes a solid phase.During this phase growth,
Since the oxidation-resistant film (4) acts as a camper (-), the step of forming a capping layer is omitted.
また、エネルギービームは直進して照射され、その照射
された部分のみが酸化されるため、バーズビーク現象が
制御され、バーズビークのない選択酸化層（６）が形成
される。In addition, since the energy beam is irradiated in a straight line and only the irradiated portion is oxidized, the bird's beak phenomenon is controlled and a selective oxidation layer (6) without bird's beak is formed.
以下、第１図を参照しながら本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail with reference to FIG.
第１図は、本実施例に係る薄膜半導体装置の形成方法を
示す土程図である。以Ｌ ｍを追ってその工程を説明す
る。FIG. 1 is a stage diagram showing a method for forming a thin film semiconductor device according to this embodiment. The process will be explained below.
面、本例はＰチャンネル型薄膜トランジスタについて述
べるが、ｎチャンネル型薄膜トランジスタにも通用でき
る。On the other hand, although this example describes a P-channel thin film transistor, the present invention can also be applied to an N-channel thin film transistor.
まず、同図Ａに不すように、５ｉ０２からなる絶縁物（
１）上に例えばＰ型を呈した多結晶シリコン清秋（２）
を例えばＣＶＤ法等で成長させる。First, as shown in Figure A, an insulator made of 5i02 (
1) Polycrystalline silicon Kiyoaki with, for example, P-type on top (2)
is grown by, for example, the CVD method.
次に、同図Ｂに示すように、多結晶シリコン薄膜（２）
の表面に熱酸化を施してゲート用の５ｔ０２ｖｉＩ化膜
（３）を形成する。その後、該５ｉ０２酸化股（３）上
ニ同様ニケ）Ｊ’ｌＪノＳｉａＮ４ＭＩＩ９！’＋４１
をＣＶＤ法等で成長させる。Next, as shown in Figure B, a polycrystalline silicon thin film (2) is formed.
A 5t02viI film (3) for a gate is formed by thermally oxidizing the surface. After that, the 5i02 oxidized crotch (3) (same as above) J'lJノSiaN4MII9! '+41
is grown by CVD method or the like.
次に、素子分離のため、同図Ｃに示すように、Ｓｉ３Ｎ
４薄膜（４）及び５ｉ０２酸化股（３）の一部をホトリ
ソグラフィー技術を用いてエツチング除去し、下層に存
していた多結晶シリコン’ａ ＭＩｊ！＋２）の一部（
２Ａ）を露出させる。Next, for element isolation, Si3N
4 thin film (4) and a part of the 5i02 oxide layer (3) were etched away using photolithography technology, and the polycrystalline silicon 'a MIj! that existed in the underlying layer was removed. +2) part (
2A) Expose.
次に、同図りに示すように、酸化性雰囲気中、例えば０
２或は０３雰囲気中でＳｉ３Ｎ４薄膜（４）及び露出さ
れた多結晶シリコン部分（２＾）を含む全面にエキシマ
レーザ（５）を照射して高温・短時間の熱処理を施し、
多結晶シリコン部分（２Ａ）を熱酸化することにより絶
縁物＋１＋に達する５ｉ０２のフィールド絶縁層（６）
に変えるとともに、Ｓｉ３Ｎ４薄膜（４）の表面を同時
熱酸化して５ｔ（ｈ酸化膜（７）を形成する。Next, as shown in the same figure, in an oxidizing atmosphere, for example, 0
2 or 03 atmosphere, the entire surface including the Si3N4 thin film (4) and the exposed polycrystalline silicon portion (2^) is irradiated with an excimer laser (5) to perform heat treatment at high temperature and for a short time.
Field insulation layer (6) of 5i02 reaching insulation +1+ by thermal oxidation of polycrystalline silicon part (2A)
At the same time, the surface of the Si3N4 thin film (4) is simultaneously thermally oxidized to form a 5T(h oxide film (7)).
このフィールド絶縁層（６）が素子分離領域となる。This field insulating layer (6) becomes an element isolation region.
また、このエキシマレーザ（５）の照射によって同時に
、Ｓｉ３Ｎ４薄梗（４）ドの活性層となる多結晶シリコ
ン＠ 膜（２）が結晶成長する。この場合、５ｉｉＮ＋
Ｍ膜（４）が活性１ｉ！ （２）のエキシマレーザ（
５）の照射に対する一種のキャンピング作用を果たして
いる。Further, at the same time, the irradiation with the excimer laser (5) causes crystal growth of the polycrystalline silicon film (2) which becomes the active layer of the Si3N4 thin layer (4). In this case, 5iiN+
M membrane (4) is active 1i! (2) excimer laser (
5) It plays a kind of camping effect against the irradiation.
一方、フィールド絶縁層（６）では、エキシマレーザ（
５）の直進照射及び短時間照射により、照射された多結
晶シリコン部分（２Ａ）のみ熱酸化され、活性７ｍ ＋
２１側に熱酸化が進行しないため、いわゆるバースビー
ク現象が発生しない。On the other hand, in the field insulating layer (6), the excimer laser (
By direct irradiation and short-time irradiation in 5), only the irradiated polycrystalline silicon portion (2A) is thermally oxidized, resulting in an active area of 7m +
Since thermal oxidation does not proceed to the 21 side, the so-called birthbeak phenomenon does not occur.
次に、同図Ｅに示すように、全面にゲート電極となる不
純物（例えばｎ型不純物）をドープした多結晶シリコン
層（８）をＣＶＤ法等で成長させ、次いで同図ドに示ず
ように、多結晶シリコン層（８）、５ｉ（ｈ酸化１ｉ＋
７１． Ｓｉ３Ｎ＋ ＊膜（４）及び５ｉ０２酸化膜（
３）を順次選択エツチングして多結晶シリコン屓（８）
よりなるゲート電極（９）及び５ｔ（ｈ酸化膜（３）と
５ｉｔＮ＋薄躾（４）と５ｉ０２酸化１１！Ｊ （７１
からなるゲート絶縁膜（１０）を形成すると共に、活性
Ｊ＊ （２１の表面部のうり、ゲート部以外の■＄分を
露出させる。Next, as shown in Figure E, a polycrystalline silicon layer (8) doped with an impurity (for example, an n-type impurity) that will become the gate electrode is grown on the entire surface by CVD, and then as shown in Figure D. , polycrystalline silicon layer (8), 5i (h oxidation 1i+
71. Si3N+ *film (4) and 5i02 oxide film (
3) is sequentially selectively etched to form a polycrystalline silicon layer (8).
Gate electrode (9) and 5t (h oxide film (3), 5itN + thin film (4) and 5i02 oxide 11!J (71
At the same time, a gate insulating film (10) consisting of the active J* (21) is formed, and the surface area of the active J* (21) and the area other than the gate area are exposed.
その後、同図Ｇに示すように、フィールド絶縁１ｍ （
６１及びゲート電極（９）をマスクとして活性層（２）
にＰ型の不純物（１３）をイオン注入してソース領域（
１１）及びドレイン領域（１２）を形成してＰチャンネ
ル型の薄膜トランジスタを形成する。After that, as shown in figure G, field insulation 1m (
Active layer (2) using 61 and gate electrode (9) as a mask.
P-type impurity (13) is ion-implanted into the source region (
11) and a drain region (12) to form a P-channel thin film transistor.
向、上記実施例では活性１ｉＪ （２１を多結晶シリコ
ンにて形成したが、その他罪晶質シリコンで形成しても
よい。In the above embodiment, the active layer 1iJ (21) was formed of polycrystalline silicon, but it may be formed of other polycrystalline silicon.
また、上潮では５ｉ（ｂ酸化１１Ｊ ＋３１とＳｉ３Ｎ
＋股（４）と５ｉ（ｈ酸化膜（７）にてゲート絶縁膜（
１０）を構成したが、その他、第１図りの工程後、これ
らＩｌｌ （３１（４１（７）を除去して、改めて５ｉ
（ｈによるゲート絶縁膜を形成することも口Ｊ能である
。In addition, in the upper tide, 5i (b oxidation 11J +31 and Si3N
+ crotch (4) and 5i (h oxide film (7) to gate insulation film (
10), but after the process of the first drawing, these Ill (31(41(7)) were removed and 5i
(It is also possible to form a gate insulating film using H.
上述の薄膜トランジスタの形成方法によれは、多結晶シ
リコン薄膜（２）上に５ｉ０２酸化股（３）を介しζ選
択的にＳ ｉ ＝Ｎ ４薄膜（４）を形成した後、エキ
シマレーザ照射による熱処理を施すことにより、フィー
ルド絶縁層（６）を形成する選択酸化と、５ｉｚＮ＋薄
膜（４）下の活性層となる多結晶シリコン層（２）の結
晶化とが同時に行なわれる。そして、この場合、選択酸
化時の耐酸化マスクとなるＳｉ３Ｎ４のＳ膜（４）が多
結晶シリコン薄膜（２）の結晶成長の際のキャッピング
ｊ−を兼ねるので、新たにキャッピング工程を追加する
必要がない。According to the method for forming a thin film transistor described above, after forming an S i =N 4 thin film (4) selectively on the polycrystalline silicon thin film (2) via a 5i02 oxide layer (3), heat treatment is performed by excimer laser irradiation. By applying this, selective oxidation to form the field insulating layer (6) and crystallization of the polycrystalline silicon layer (2) which will become the active layer under the 5izN+ thin film (4) are performed simultaneously. In this case, the Si3N4 S film (4), which serves as an oxidation-resistant mask during selective oxidation, also serves as a capping layer during crystal growth of the polycrystalline silicon thin film (2), so it is necessary to add a new capping process. There is no.
さらにエキシマレーザ（５）の照射により、５ｉＪ４薄
欣（４）の表面が熱酸化され５ｉ（ｈ酸化膜（７）を形
成することができ、ゲート絶縁膜（１０） （或は他
の合縁を構成する場合の誘電物質）とし”ζ５ｉＯ２−
Ｓｉ）Ｎ４Ｓｉ（ｈのサンドイッチ構造を同時に形成す
ることができる。従って、薄膜トランジスタの製造上程
の簡略化を図ることができる。Further, by irradiation with the excimer laser (5), the surface of the 5iJ4 thin film (4) is thermally oxidized to form a 5i(h oxide film (7)), and a gate insulating film (10) (or other bonding film) can be formed. ζ5iO2−
A sandwich structure of Si)N4Si(h) can be formed at the same time. Therefore, the manufacturing process of the thin film transistor can be simplified.
一方、選択酸化によってフィールド絶縁層（６）を形成
する際に、従来の１１００℃、長時間の熱酸化とは異な
り、エキシマレーザ照射による高温、短時間の熱処理で
行なわれ、且つしかもエキシマレーザ（５）は直進して
照射されその照射された部分（２Ａ）のみが熱酸化され
るためにバーズビークの発生が抑制され、バースビーク
のないフィールド絶縁層（６）を形成することができ、
素子の高密度化を図ることができる。On the other hand, when forming the field insulating layer (6) by selective oxidation, unlike the conventional thermal oxidation at 1100°C for a long time, heat treatment is performed at a high temperature and for a short time by excimer laser irradiation. 5) is irradiated straight ahead and only the irradiated portion (2A) is thermally oxidized, so the generation of bird's beak is suppressed and a field insulating layer (6) without bird's beak can be formed;
It is possible to increase the density of elements.
本発明に係る清秋半導体装置の形成方法は、絶縁性基板
上に非単結晶薄膜半導体層を形成し、該半導体１舗上に
選択的に耐酸化膜を形成する。その後、酸化性雰囲気中
で全面にエネルギービームを照射して露出している半導
体を−を酸化すると共に、耐酸化股下の半導体層を熱処
理するようにしたので、素子分１ｉＳｌｉ領域となる選
択酸化１−の形成と、耐酸化股下の活性層となる半導体
層の結晶改善を同時に行なうことができ、また選択酸化
時におけるバーズビーク現象の発生を抑制できると共に
、ビーム照射の際のｌｉ性層へのキャッピング工程を省
（ことができる。従って、製造」二枚を簡略化すること
ができると共に、半導体素子の高集積化を図ることがで
きる。In the method for forming a semiconductor device according to the present invention, a non-single crystal thin film semiconductor layer is formed on an insulating substrate, and an oxidation-resistant film is selectively formed on the semiconductor layer. After that, we irradiated the entire surface with an energy beam in an oxidizing atmosphere to oxidize the exposed semiconductor, and also heat-treated the semiconductor layer under the oxidation-resistant crotch, so that the selective oxidation 1 which becomes the 1iSli region for each element - can be formed at the same time as the crystalline improvement of the semiconductor layer which becomes the active layer of the oxidation-resistant crotch, and can suppress the occurrence of bird's beak phenomenon during selective oxidation, as well as capping the lithium layer during beam irradiation. Therefore, the manufacturing process can be simplified, and the semiconductor device can be highly integrated.
第１図は、本実施例に係る薄膜半導体装置の形成方法を
示す土程図である。
（１）は５ｉ０２絶縁物、（２）は多結晶シリコン層（
活性層） 、ｆ３）ハＳ＋０２ｖ化膜、！４） ハＳ
ｉ、＋Ｎ ４薄膜、（５）はエキシマレーザ、（６）は
フィールド絶縁層、（７）は５ｉ（ｈ酸化膜、（８）は
多結晶シリコン層、（９）はゲート電極、（１０）はゲ
ート絶縁膜、（１１）はソース領域、（１２）はドレイ
ン領域である。FIG. 1 is a stage diagram showing a method for forming a thin film semiconductor device according to this embodiment. (1) is a 5i02 insulator, (2) is a polycrystalline silicon layer (
Active layer), f3) HaS+02v film,! 4) HaS
i, +N 4 thin films, (5) is excimer laser, (6) is field insulating layer, (7) is 5i (h oxide film, (8) is polycrystalline silicon layer, (9) is gate electrode, (10) is a gate insulating film, (11) is a source region, and (12) is a drain region.
Claims (1)
出している上記半導体層を酸化すると共に、耐酸化膜下
の上記半導体層を熱処理する工程とを有する薄膜半導体
層の形成方法。[Claims] A step of forming a non-single crystal thin film semiconductor layer on an insulating substrate, a step of selectively forming an oxidation-resistant film on the semiconductor layer, and a step of irradiating the entire surface with an energy beam in an oxidizing atmosphere. A method for forming a thin film semiconductor layer, comprising the steps of oxidizing the exposed semiconductor layer and heat-treating the semiconductor layer under the oxidation-resistant film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18606188A JP2718074B2 (en) | 1988-07-26 | 1988-07-26 | Method of forming thin film semiconductor layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18606188A JP2718074B2 (en) | 1988-07-26 | 1988-07-26 | Method of forming thin film semiconductor layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0235710A true JPH0235710A (en) | 1990-02-06 |
| JP2718074B2 JP2718074B2 (en) | 1998-02-25 |
Family
ID=16181707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18606188A Expired - Fee Related JP2718074B2 (en) | 1988-07-26 | 1988-07-26 | Method of forming thin film semiconductor layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2718074B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5175123A (en) * | 1990-11-13 | 1992-12-29 | Motorola, Inc. | High-pressure polysilicon encapsulated localized oxidation of silicon |
| US5580815A (en) * | 1993-08-12 | 1996-12-03 | Motorola Inc. | Process for forming field isolation and a structure over a semiconductor substrate |
| US6083810A (en) * | 1993-11-15 | 2000-07-04 | Lucent Technologies | Integrated circuit fabrication process |
| US7259053B2 (en) * | 2003-09-22 | 2007-08-21 | Dongbu Electronics Co., Ltd. | Methods for forming a device isolation structure in a semiconductor device |
-
1988
- 1988-07-26 JP JP18606188A patent/JP2718074B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5175123A (en) * | 1990-11-13 | 1992-12-29 | Motorola, Inc. | High-pressure polysilicon encapsulated localized oxidation of silicon |
| USRE35294E (en) * | 1990-11-13 | 1996-07-09 | Motorola, Inc. | Polysilicon encapsulated localized oxidation of silicon |
| US5580815A (en) * | 1993-08-12 | 1996-12-03 | Motorola Inc. | Process for forming field isolation and a structure over a semiconductor substrate |
| US5707889A (en) * | 1993-08-12 | 1998-01-13 | Motorola Inc. | Process for forming field isolation |
| US6083810A (en) * | 1993-11-15 | 2000-07-04 | Lucent Technologies | Integrated circuit fabrication process |
| US7259053B2 (en) * | 2003-09-22 | 2007-08-21 | Dongbu Electronics Co., Ltd. | Methods for forming a device isolation structure in a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2718074B2 (en) | 1998-02-25 |
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