JPS62134945A - Molded transistor - Google Patents

Molded transistor

Info

Publication number
JPS62134945A
JPS62134945A JP60275632A JP27563285A JPS62134945A JP S62134945 A JPS62134945 A JP S62134945A JP 60275632 A JP60275632 A JP 60275632A JP 27563285 A JP27563285 A JP 27563285A JP S62134945 A JPS62134945 A JP S62134945A
Authority
JP
Japan
Prior art keywords
transistor
electrodes
electrode
molded
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60275632A
Other languages
Japanese (ja)
Other versions
JPH0783074B2 (en
Inventor
Tatsuo Hakuta
伯田　達夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP60275632A priority Critical patent/JPH0783074B2/en
Publication of JPS62134945A publication Critical patent/JPS62134945A/en
Publication of JPH0783074B2 publication Critical patent/JPH0783074B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce in size a transistor by so forming at least part of electrodes connected with a device as to become substantially the same surface as the outer surface of a sheath composed by molding, and exposing the electrode on the outer surface of the sheath. CONSTITUTION:Three electrodes 11, 12, 13 are so provided as to expose on the bottom of a sheath 19. The electrodes 11, 12, 13 are all formed in straight shape, and so exposed on the bottom of the sheath 19 that the bottoms of the electrodes become the same surface as the bottom of the sheath 19. This transistor is mounted on a circuit substrate 22. That is, the transistor is so mounted on the substrate 22 that the bottom in which the electrodes 11, 12, 13 are exposed is opposed to the substrate 22, and the electrodes 11, 12, 13 are connected by solders 24 with a conductive pattern 23 made of a copper foil to form a predetermined circuit.

Description

【発明の詳細な説明】[Detailed description of the invention]

「産業上の利用分野】 本発明はモールドトランジスタに係り、特にトランジス
タ本体を構成するデバイスをモールドして封入するよう
にしたモールドトランジスタに関する。TECHNICAL FIELD The present invention relates to a molded transistor, and more particularly to a molded transistor in which a device constituting a transistor body is molded and encapsulated.

【発明の概要】[Summary of the invention]

本発明は、デバイスと接続された電極の少な（とも一部
がモールドによって構成されている外装体の外表面とほ
ぼ同一表面となるように構成し、電極が外装体の外表面
に露出されるようにしたちのであって、これによってト
ランジシスタをより小型化するようにしたものである。 に従来の技術］ 回路基板上にマウントされるようになっているチップ状
のトランジスタとして、従来よりモールドトランジスタ
が用いられている。モールドトランジスタはデバイスを
モールドによって封入するようにしたものであって、デ
バイスと接続された電極が外装体の外部に突出するよう
になっており、この電極を回路基板上の配線パターンと
接続して所定の回路を形成するようにしている。このよ
うな場合における電極は、モールドの外装体の外側部に
突出するようになるとともに、屈曲された形状を有して
おり、その先端部が回路基板上の銅箔と接触するように
なっている。 ｒ発明が解決しようとする問題点】 従来のこのようなモールドトランジスタによれば、その
大きさを余り小さくすることができず、小型化が阻害さ
れている。また電極が屈曲した形状になっているために
、あらかじめ曲げ加工をしてデバイスと接続しなければ
ならず、これによってコス１−が上昇する欠点がある。 さらにこのような従来のモールドトランジスタは、電極
の面積が小さいために、自装間によるマウントを行なう
場合にお１プる許容誤差が小さくなるという問題がある
。さらに従来のモールドトランジスタは、放熱性が悪く
、温度が上昇し易い欠点があった。 本発明はこのような問題点に鑑みてなされたものであっ
て、より小型化することが可能で、必ずしも電極をあら
かじめ曲げ加工する必要がなく、さらには自装機による
マウントの許容誤差が比較的大きくなり、さらには放熱
し易いｍ造を有するモールドトランジスタを提供するこ
とを目的とするものである。。 Ｋ問題点を解決するための手段】 本発明は、トランジスタ本体を構成するデバイスをモー
ルドして封入するようにしたトランジスタにおいて、前
記デバイスと接続された電極を設けるとともに、この電
極の少なくとも一部がモールドによって構成されている
外装体の外表面とほぼ同一平面になるように構成され、
前記外装体の外表面に露出されるようにしたものである
。In the present invention, the electrodes connected to the device are configured so that the outer surface thereof is almost the same as the outer surface of the outer case, a part of which is formed by a mold, and the electrodes are exposed on the outer surface of the outer case. Conventional technology] Molded transistors are conventionally used as chip-shaped transistors that are mounted on circuit boards. A molded transistor is a device in which the device is enclosed in a mold, and the electrode connected to the device protrudes from the exterior of the case, and this electrode is connected to the circuit board. The electrode is connected to the wiring pattern to form a predetermined circuit.In such a case, the electrode protrudes to the outside of the exterior body of the mold and has a bent shape. The tip of the transistor comes into contact with the copper foil on the circuit board.Problems to be Solved by the Invention According to the conventional molded transistor, its size cannot be made very small. First, miniaturization is hindered.Furthermore, since the electrodes have a bent shape, they must be bent in advance to be connected to a device, which has the disadvantage of increasing cost. Furthermore, due to the small electrode area of such conventional molded transistors, there is a problem in that the tolerance for mounting is small when mounting by self-mounting.Furthermore, conventional molded transistors have The present invention was made in view of these problems, and allows for further miniaturization and does not necessarily require bending the electrodes in advance. Furthermore, it is an object of the present invention to provide a molded transistor having a structure in which the tolerance of mounting by a self-mounting machine is relatively large, and furthermore, it is easy to dissipate heat.Means for solving the problem K. The present invention provides a transistor in which a device constituting a transistor main body is molded and enclosed, and an electrode connected to the device is provided, and at least a part of the electrode is formed of an exterior body formed by molding. configured to be approximately flush with the outer surface,
It is configured to be exposed on the outer surface of the exterior body.

【作用】[Effect]

従って本発明によれば、電極を外装体の外側の必ずしも
突設することが必要でなく、外装体の底面に露出するよ
うに設けることが可能になり、これによってモールドト
ランジスタの小型化を図ることができる。また電極をス
ｉ・レートな形状とすることにより、あらかじめ曲げ加
工を行なう必要がなくなる。さらに外装体の外表面に露
出する電極の面積を大きくすることが可能になり、自装
機によるマウントの許容誤差を大きくすることが可能に
なる。また比較的大きな面積を有する電極を通して回路
基板に熱が逃げる構造にすることが可能になるために、
放熱性にすぐれたモールドトランジスタを得ることが可
能になる。Therefore, according to the present invention, it is not necessary for the electrode to be provided protrudingly on the outside of the exterior body, but it is possible to provide the electrode so as to be exposed on the bottom surface of the exterior body, thereby reducing the size of the molded transistor. I can do it. Furthermore, by forming the electrode into a slate shape, there is no need to perform bending in advance. Furthermore, it becomes possible to increase the area of the electrode exposed on the outer surface of the exterior body, and it becomes possible to increase the tolerance for mounting by the self-mounting machine. In addition, it is possible to create a structure in which heat can escape to the circuit board through electrodes with a relatively large area.
It becomes possible to obtain a molded transistor with excellent heat dissipation.

【実施例】【Example】

以下本発明を図示の〜実施例につき説明する。 本実施例に係るモールドトランジスタを作成する場合に
は、帯状の電極材１０を用いる。この電極材１０は真鍮
や黄銅等の導電性材料を用いる。そしてこのような帯状
の電極材１０を第３図に示すように打扱き、コレクタ電
極１１、ベース電極１２、およびエミッタ電極１３をそ
れぞれ形成する。 これらの１を極１１．１２．１３は電極材１０の両側の
連結部１４から延出されるように形成される。 また両側の連結部１４を適当に連結するために、横方向
の連結部材１５を所定のピッチで設けるようにしている
。また両側のベース電極１２とエミッタ電極１３とには
それぞれ側方に突出するように突部１６が形成されてお
り、これによって後述する外装体との間の接触面積を広
くし、電極１２．１３の接合強度を高めるようにしてい
る。 このような電極材１０のコレクタ電極１１上には、第４
図に示すように、ベレットからなるペアチップ１７がマ
ウントされる。このペアチップ１７がトランジスタ本体
を構成することになる。そしてこのペアチップ１７のコ
レクタはｉｌｌコレクタ電極１１に接触するようになっ
ており、これに対してペアチップ１７のベースおよびエ
ミッタはボンディング用ワイヤ１８を介してベース電極
１２およびエミッタ電極１３にそれぞれ接続されるよう
になっている。このようにしてワイヤボンディングを行
なったならば、つぎに第５図において鎖線１９で示すよ
うに、モールドによって外装体１９を成形し、コレクタ
電極１１上のペアチップ１７を封入する。この後に鎖１
！１１１９に沿って電極１１．１２．１３の延出部をそ
れぞれ力ツティングするとともに、外装体１つのパリ取
りを行なう。 これによってモールドトランジスタが得られることにな
る。 第１図および第２図はこのようにして１ｑられたモール
ドトランジスタを示すものであって、このトランジスタ
の特徴は、外装体１９の底面に露出するように３つの電
極１１．１２．１３がそれぞれ設けられていることであ
る。すなわち電極１１．１２．１３はともにストレート
な形状をなしており、しかもそれらの底面が外装体１９
の底面と同一平面となるように外装体１９の底面に露出
されるようになっている。そしてこのようなトランジス
タは、第６図に示すように、回路基板２２上にマウント
されるようになっている。すなわちトランジスタは電極
１１．１２．１３が露出する底面が回路基板２２と対向
するように回路基板２２上にマウントするようになって
おり、電極１．１２．１３はそれぞれ鋼箔からなる導電
性パターン２３と半田２４によって接続されるようにな
っており、これによって所定の回路を形成するようにし
ている。 このような本実施例に係るモールド１−ランジスタによ
れば、外装体１９の両側に電極１１．１２．１３がそれ
ぞれ出偏ることがなく、このためにトランジスタを小型
化することが可能になる。さらにストレートな形状の電
極１１．１２．１３を漏えるようになっているために、
あらかじめ電極１１．１２．１３をそれぞれ曲げ加工す
る必要がなくなり、このためにトランジスタのコストダ
ウンを図ることが可能になる。また外装体１つの底面が
平坦に構成されるとともに、この平坦な底面に３つの電
極１１．１２．１３がそれぞれ露出するようになってい
るために、自装機によるマウン］へが容易になるととも
に、許容さ机る精度を低くしても確実に接続を行なうこ
とが可能になる。さらにトランジスタの平坦な底面が回
路基板２２と接触する構造になるために回路基板２２を
通して放熱が行なわれ、温度上昇が少ないトランジスタ
を提供することが可能にな゛る。またこのようなトラン
ジスタは、その底面に電極１１．１２．１３が露出され
るようになっているために、異方性導電膜でも十分な接
合抵抗をとることができるようになる。ざらに電極１２
．１３の側部に突部１６が形成されているために、外装
体を構成するモールド１９との間の接合強度を高くする
ことが可能になり、ストレスに強いトランジスタとなる
。またこのようなトランジスタは、不良の場合に容易に
交換することが可能になる。 以上本発明を図示の一実施例につき述べたが、本発明は
上記実施例によって限定されることなく、本発明の技術
的思想に基いて各種の変更が可能である。例えば上記実
施例に係るトランジスタにおいては、その電極１１．１
２．１３の先端部は外装体１つの外側面と同一の平面を
構成するようになっているが、電極１１．１２．１３の
先端部については、第７図および第８図に示すように、
外装体１９の両側の側面から突出するようにしてもよい
。 【発明の効果Ｘ 以上のように本発明は、トランジスタ本体を構成するデ
バイスと接続された電極の少なくとも一部がモールドに
よって構成されている外装体の外表面と同一表面となる
ように外装体の外表面に露出されるようにしたものであ
る。従ってこのような構成によれば、小型でローコスト
の１−ランジスタを提供することが可能になるとともに
、自装機によるマウントが容易で、しかも回路基板を通
して放熱が達成されるようになり、温度上界を防止する
ことが可能になる。The present invention will now be explained with reference to the illustrated embodiments. When creating the molded transistor according to this example, a strip-shaped electrode material 10 is used. This electrode material 10 uses a conductive material such as brass or brass. The strip-shaped electrode material 10 is then treated as shown in FIG. 3 to form a collector electrode 11, a base electrode 12, and an emitter electrode 13, respectively. These poles 11, 12, and 13 are formed to extend from the connecting portions 14 on both sides of the electrode material 10. Further, in order to appropriately connect the connecting portions 14 on both sides, horizontal connecting members 15 are provided at a predetermined pitch. Furthermore, protrusions 16 are formed on the base electrode 12 and the emitter electrode 13 on both sides, respectively, so as to protrude laterally. The joint strength of the parts is increased. On the collector electrode 11 of such an electrode material 10, there is a fourth
As shown in the figure, a pair of chips 17 made of a pellet is mounted. This paired chip 17 constitutes the main body of the transistor. The collector of this paired chip 17 is in contact with the ill collector electrode 11, whereas the base and emitter of the paired chip 17 are connected to the base electrode 12 and emitter electrode 13, respectively, via bonding wires 18. It looks like this. After the wire bonding has been performed in this manner, an exterior body 19 is formed by molding, as shown by the chain line 19 in FIG. 5, and the paired chip 17 on the collector electrode 11 is encapsulated therein. After this chain 1
! The extensions of the electrodes 11, 12, and 13 are each pushed along the line 1119, and one of the exterior bodies is deburred. This results in a molded transistor. FIGS. 1 and 2 show a molded transistor made in this way, and the feature of this transistor is that the three electrodes 11, 12, and 13 are exposed on the bottom surface of the exterior body 19, respectively. This is what is provided. In other words, the electrodes 11, 12, and 13 all have a straight shape, and their bottom surfaces are connected to the exterior body 19.
It is exposed on the bottom surface of the exterior body 19 so as to be flush with the bottom surface of the exterior body 19. Such a transistor is mounted on a circuit board 22, as shown in FIG. That is, the transistor is mounted on the circuit board 22 such that the bottom surface where the electrodes 11, 12, 13 are exposed faces the circuit board 22, and each of the electrodes 1, 12, 13 is a conductive pattern made of steel foil. 23 and solder 24, thereby forming a predetermined circuit. According to the mold 1-transistor according to this embodiment, the electrodes 11, 12, and 13 are not biased on both sides of the exterior body 19, and therefore the transistor can be miniaturized. Furthermore, since the straight-shaped electrodes 11, 12, and 13 leak,
There is no need to bend each of the electrodes 11, 12, 13 in advance, which makes it possible to reduce the cost of the transistor. In addition, the bottom surface of one exterior body is configured to be flat, and the three electrodes 11, 12, and 13 are exposed on this flat bottom surface, making it easy to mount using a self-mounting machine. At the same time, it is possible to reliably connect even if the permissible accuracy is lowered. Furthermore, since the flat bottom surface of the transistor is in contact with the circuit board 22, heat is radiated through the circuit board 22, making it possible to provide a transistor with less temperature rise. Furthermore, since the electrodes 11, 12, and 13 of such a transistor are exposed on the bottom surface thereof, sufficient junction resistance can be obtained even with an anisotropic conductive film. Rough electrode 12
．． Since the protrusions 16 are formed on the sides of the transistor 13, it is possible to increase the bonding strength with the mold 19 that constitutes the exterior body, resulting in a transistor that is resistant to stress. Moreover, such a transistor can be easily replaced in case of failure. Although the present invention has been described above with reference to the illustrated embodiment, the present invention is not limited to the above embodiment, and various modifications can be made based on the technical idea of the present invention. For example, in the transistor according to the above embodiment, the electrode 11.1
The tips of electrodes 11, 12, and 13 are configured to form the same plane as the outer surface of one of the exterior bodies, but the tips of electrodes 11, 12, and 13 are arranged as shown in FIGS. 7 and 8. ,
It may be made to protrude from both side surfaces of the exterior body 19. Effects of the Invention It is designed to be exposed on the outer surface. Therefore, according to such a configuration, it is possible to provide a small and low-cost 1-transistor, and it is easy to mount with a self-mounting machine, and heat dissipation is achieved through the circuit board, which reduces temperature. It becomes possible to prevent the world from occurring.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例に係るモールドトランジスタ
を示す外観斜視図、第２図は同底面図、第３図は打抜か
れた電極材の平面図、第４図はボンディングが行なわれ
た電極材の平面図、第５図はモールドの状態を示す電極
材の平面図、第６図はこのトランジスタを実装した回路
基板の断面図、第７図は変形例に係るモールド１〜ラン
ジスタの外観斜視図、第８図は同底面図である。 なお図面に用いた符号において、 １１・・・コレクタ電極 １２・・・ベース電極 １３・・・エミッタ電極 １７・・・ベアチップ（ベレット） １８・・・ボンデング用ワイヤ １つ・・・外装体（モールド） である。FIG. 1 is an external perspective view showing a molded transistor according to an embodiment of the present invention, FIG. 2 is a bottom view of the same, FIG. 3 is a plan view of a punched electrode material, and FIG. 4 is a diagram showing a molded transistor after bonding. A plan view of the electrode material, FIG. 5 is a plan view of the electrode material showing the state of the mold, FIG. 6 is a cross-sectional view of the circuit board on which this transistor is mounted, and FIG. 7 is an external appearance of mold 1 to transistor according to a modification. The perspective view and FIG. 8 are the same bottom views. In addition, in the symbols used in the drawings, 11...Collector electrode 12...Base electrode 13...Emitter electrode 17...Bare chip (bellet) 18...One wire for bonding...Exterior body (mold) ).

Claims (1)

【特許請求の範囲】[Claims] トランジスタ本体を構成するデバイスをモールドして封
入するようにしたトランジスタにおいて、前記デバイス
と接続された電極を設けるとともに、この電極の少なく
とも一部がモールドによつて構成されている外装体の外
表面とほぼ同一平面になるように構成され、前記外装体
の外表面に露出されるようにしたことを特徴とするモー
ルドトランジスタ。In a transistor in which a device constituting the transistor body is molded and encapsulated, an electrode is provided that is connected to the device, and at least a part of this electrode is connected to the outer surface of the exterior body configured by the mold. A molded transistor characterized in that the molded transistor is configured to have substantially the same plane and is exposed on the outer surface of the exterior body.
JP60275632A 1985-12-06 1985-12-06 Mold transistor Expired - Lifetime JPH0783074B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60275632A JPH0783074B2 (en) 1985-12-06 1985-12-06 Mold transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60275632A JPH0783074B2 (en) 1985-12-06 1985-12-06 Mold transistor

Publications (2)

Publication Number Publication Date
JPS62134945A true JPS62134945A (en) 1987-06-18
JPH0783074B2 JPH0783074B2 (en) 1995-09-06

Family

ID=17558162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60275632A Expired - Lifetime JPH0783074B2 (en) 1985-12-06 1985-12-06 Mold transistor

Country Status (1)

Country Link
JP (1) JPH0783074B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0369149A (en) * 1989-08-08 1991-03-25 Mitsubishi Electric Corp High output transistor
US5512781A (en) * 1992-12-01 1996-04-30 Kabushiki Kaisha Toshiba Semiconductor package device for super high-frequency band
US5631809A (en) * 1993-09-17 1997-05-20 Kabushiki Kaisha Toshiba Semiconductor device for ultrahigh frequency band and semiconductor apparatus including the semiconductor device
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
US6252306B1 (en) 1998-05-12 2001-06-26 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device and configuration thereof, and lead frame used in said method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121862A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Resin-sealed semiconductor device
JPS6033452U (en) * 1983-08-10 1985-03-07 日本電気株式会社 Resin-encapsulated semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121862A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Resin-sealed semiconductor device
JPS6033452U (en) * 1983-08-10 1985-03-07 日本電気株式会社 Resin-encapsulated semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0369149A (en) * 1989-08-08 1991-03-25 Mitsubishi Electric Corp High output transistor
US5512781A (en) * 1992-12-01 1996-04-30 Kabushiki Kaisha Toshiba Semiconductor package device for super high-frequency band
US5631809A (en) * 1993-09-17 1997-05-20 Kabushiki Kaisha Toshiba Semiconductor device for ultrahigh frequency band and semiconductor apparatus including the semiconductor device
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
EP0895287A3 (en) * 1997-07-31 2006-04-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and lead frame for the same
US6252306B1 (en) 1998-05-12 2001-06-26 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device and configuration thereof, and lead frame used in said method

Also Published As

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JPH0783074B2 (en) 1995-09-06

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