JPH06204385A - Semiconductor device mounted pin grid array package substrate - Google Patents
Semiconductor device mounted pin grid array package substrateInfo
- Publication number
- JPH06204385A JPH06204385A JP4339621A JP33962192A JPH06204385A JP H06204385 A JPH06204385 A JP H06204385A JP 4339621 A JP4339621 A JP 4339621A JP 33962192 A JP33962192 A JP 33962192A JP H06204385 A JPH06204385 A JP H06204385A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- pin
- semiconductor element
- substrate
- grid array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子搭載ピング
リッドアレイパッケージ基板に関し、コンピューター等
の各種回路基板の実装等に利用される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounted pin grid array package board, which is used for mounting various circuit boards such as computers.
【０００２】[0002]
【従来の技術】従来、半導体素子のパッケージとして
は、デュアルインラインパッケージ、フラットパッケー
ジ、チップキャリア、ピングリッドアレイ等があり、こ
れらパッケージを構成する材質はプラスチックス又はセ
ラミックスである。これらのパッケージの中でピングリ
ッドアレイは、最近の高集積化された半導体素子の搭載
に非常に適しており、コンピューターをはじめ各種の用
途に使用されている。このピングリッドアレイにおいて
は、通常、セラミックス基板に導体回路を形成後、当該
基板に入出力用の導体ピンを装着する際、約８００℃と
いう比較的高温で溶融する銀ロウを用いて基板上の回路
と導体ピンを固着し、電気的に接続していた。2. Description of the Related Art Conventionally, as a package of a semiconductor device, there are a dual in-line package, a flat package, a chip carrier, a pin grid array, etc., and the material forming these packages is plastics or ceramics. Among these packages, the pin grid array is very suitable for mounting recent highly integrated semiconductor devices and is used in various applications including computers. In this pin grid array, when a conductor circuit is formed on a ceramic substrate and then a conductor pin for input / output is mounted on the substrate, a silver solder that melts at a relatively high temperature of about 800 ° C. is usually used on the substrate. The circuit and the conductor pin were fixed and electrically connected.
【０００３】[0003]
【発明が解決しようとする課題】しかし、これらセラミ
ックス基板から成るピングリッドアレイは、複雑な工程
を経て、導体回路が形成され、また高価な銀ロウを用い
て約８００℃という比較的高温で導体ピンを接合するた
めコスト高となること及び高温に耐え且つ加工精度の良
い治工具を必要とすること等の欠点を有していた。更
に、印刷配線基板（有機系樹脂製）と、この印刷配線基
板の複数個の孔に打ち込まれ基板上のパターンと接続さ
れる複数本のリード用ピンとを有する半導体ステムであ
って、このピンは大径部及び鍔部を有する構造からなる
ものが知られている（特開昭５９−８２７５７号公
報）。また、導体ピンとして大径部及び鍔部を有するも
のを用いたプラグインパッケージ基板も知られている
（実開昭６１−１３９３８号公報）。However, in the pin grid array made of these ceramic substrates, a conductor circuit is formed through complicated steps, and the conductor is formed at a relatively high temperature of about 800 ° C. using an expensive silver solder. Since the pins are joined, there are drawbacks such as high cost and the need for jigs and tools that can withstand high temperatures and have high processing accuracy. Furthermore, a semiconductor stem having a printed wiring board (made of organic resin) and a plurality of lead pins which are driven into a plurality of holes of the printed wiring board and are connected to a pattern on the substrate, wherein the pins are A structure having a large diameter portion and a collar portion is known (Japanese Patent Laid-Open No. 59-82757). Also, a plug-in package substrate using a conductor pin having a large diameter portion and a flange portion is known (Japanese Utility Model Laid-Open No. 61-13938).
【０００４】しかし、この両者ともに、導電パターンを
有する印刷配線基板に直接、導体ピンを嵌入させ、その
ため導体ピンの大径部がこの配線基板内に埋設されるこ
ととなる。従って、この配線基板はある程度厚みが必要
であるとともに、導体ピンの支持と導体回路に対する接
続を同一の配線基板によって行っている。そのため、導
体ピンの無理な嵌入によりスルーホール若しくは配線基
板自体が変形、破損することがあり、この場合は電気的
接続の信頼性に欠けることとなる。本発明は、従来のセ
ラミックス基板及び樹脂基板のピングリッドアレイの有
する欠点を改善するものであり、配線基板自体の変形、
破損がなく、電気的接続の信頼性に優れ、導体ピンの固
着性に優れ、且つ配線基板の取り外し又は取り替えが容
易な半導体素子搭載ピングリッドアレイパッケージ基板
を提供することを目的とする。However, in both of these, the conductor pin is directly fitted into the printed wiring board having the conductive pattern, so that the large diameter portion of the conductor pin is embedded in the wiring board. Therefore, this wiring board needs to have a certain thickness, and the same wiring board is used for supporting the conductor pins and for connecting to the conductor circuit. Therefore, the through-hole or the wiring board itself may be deformed or damaged due to the excessive fitting of the conductor pin, and in this case, the reliability of the electrical connection is lacking. The present invention is intended to improve the drawbacks of conventional pin grid arrays of ceramic substrates and resin substrates.
An object of the present invention is to provide a semiconductor element-mounted pin grid array package board which is not damaged, has excellent reliability of electrical connection, excellent adherence of conductor pins, and can easily remove or replace a wiring board.
【０００５】[0005]
【課題を解決するための手段】第１発明の半導体素子搭
載ピングリッドアレイパッケージ基板（以下、単にパッ
ケージ基板という。）は、半導体素子を搭載し且つ該半
導体素子に接続される所定の導体回路を有する樹脂製フ
ィルム状プリント配線基板（以下、配線基板ともい
う。）と、所定位置に嵌入固着される複数の導体ピンを
有する有機系樹脂基板（以下、樹脂基板ともいう。）と
から成り、更に前記導体回路と前記導体ピンとははんだ
により電気的に接続されているピングリッドアレイパッ
ケージ基板であって、前記導体ピンは中間部に大径部が
形成され、該導体ピンの大径部より内径の小さい貫通孔
に嵌入固着され、且つ前記大径部は前記樹脂基板内に埋
設され、更に、該各導体ピンの頂部が前記樹脂基板の表
面から突出し、また、前記配線基板及び前記導体回路の
うちの少なくとも該配線基板には、前記各導体ピンの頂
部に対応する位置に導体ピン接続用開口部を有し、且つ
該各導体ピンの頂部と該接続用開口部とは嵌め合わされ
ていることを特徴とする。A semiconductor element mounting pin grid array package substrate (hereinafter, simply referred to as a package substrate) of a first aspect of the present invention includes a predetermined conductor circuit on which a semiconductor element is mounted and which is connected to the semiconductor element. And a resin film-shaped printed wiring board (hereinafter also referred to as a wiring board) and an organic resin board (hereinafter also referred to as a resin board) having a plurality of conductor pins fitted and fixed at predetermined positions. A pin grid array package substrate in which the conductor circuit and the conductor pin are electrically connected by solder, wherein the conductor pin has a large diameter portion formed in an intermediate portion, and the conductor pin has an inner diameter larger than that of the large diameter portion. The large diameter portion is fitted and fixed in a small through hole, and the large diameter portion is embedded in the resin substrate, and the top portions of the conductor pins protrude from the surface of the resin substrate, and At least the wiring board of the wiring board and the conductor circuit has a conductor pin connection opening at a position corresponding to the top of each conductor pin, and the top of each conductor pin and the connection opening. It is characterized in that the part is fitted.
【０００６】第２発明のパッケージ基板は、半導体素子
を搭載し且つ該半導体素子に接続される所定の導体回路
を有する樹脂製フィルム状プリント配線基板と、所定位
置に嵌入固着される複数の導体ピンを有する有機系樹脂
基板とから成り、更に前記導体回路と前記導体ピンとは
はんだにより電気的に接続されているピングリッドアレ
イパッケージ基板であって、前記導体ピンは中間部に大
径部が形成され、該導体ピンの大径部より内径の小さい
貫通孔に嵌入固着され、且つ前記大径部は前記樹脂基板
内に埋設され、更に、前記各導体ピンの頂部が前記樹脂
基板の表面と同一面又は該表面よりも低い面になるよう
にし、また、前記配線基板と前記導体回路との間に形成
される空間にはんだが充填されており、該はんだにより
前記導体回路と前記導体ピンとを電気的に接続している
ことを特徴とする。A package substrate of the second invention is a resin film-shaped printed wiring board having a semiconductor element mounted thereon and having a predetermined conductor circuit connected to the semiconductor element, and a plurality of conductor pins fitted and fixed at predetermined positions. Is a pin grid array package substrate in which the conductor circuit and the conductor pin are electrically connected by solder, and the conductor pin has a large-diameter portion formed in an intermediate portion. , Fitted and fixed in a through hole having an inner diameter smaller than the large diameter portion of the conductor pin, and the large diameter portion is embedded in the resin substrate, and the tops of the conductor pins are flush with the surface of the resin substrate. Alternatively, the space formed between the wiring board and the conductor circuit is filled with solder so that the surface of the conductor circuit is lower than the surface of the conductor circuit. Characterized in that electrically connects the conductor pin.
【０００７】上記第２発明にて行われるハンダ付け接合
は、通常、前記導体ピン上に形成された金属バンプ又は
前記導体回路の裏面側に形成された金属バンプを加熱溶
融させて行う。この金属バンプは、その溶融・固化によ
り、配線基板の導体回路と導体ピンとを電気的に接続す
るのみならず、その溶融前の形状により配線基板を樹脂
基板上に搭載する際の、位置合わせや仮止めの役割を果
たすものである。The soldering and joining performed in the second aspect of the invention is usually performed by heating and melting a metal bump formed on the conductor pin or a metal bump formed on the back side of the conductor circuit. This metal bump not only electrically connects the conductor circuit and the conductor pin of the wiring board by melting and solidifying the metal bump, but also adjusts the position when mounting the wiring board on the resin substrate due to the shape before melting. It serves as a temporary stop.
【０００８】また、上記第１及び第２発明において、上
記「導体ピン接続用開口部」は、配線基板のみならず導
体回路部分をも貫通し、全体として貫通孔形状（図５、
図６）であってもよいし、この導体回路部分は貫通され
ず配線基板部分のみが開孔され全体として凹部形状（図
４）となってもよい。尚、金属パンプが導体回路側に形
成される場合は、前記導体ピンの頂部（頂面）が樹脂基
板の表面よりもやや低い面になるように配設され、その
ため導体ピン接続用開口部は、この樹脂基板に囲まれる
ように各導体ピンの頂部上に形成される凹部からなる。
このようにすることにより、配線基板の位置決め、仮止
めができる。In the first and second inventions, the "conductor pin connecting opening" penetrates not only the wiring board but also the conductor circuit portion, and has a through-hole shape as a whole (FIG. 5, FIG. 5).
6), or the conductor circuit portion may not be penetrated and only the wiring board portion may be opened to form a concave shape (FIG. 4) as a whole. When the metal pump is formed on the conductor circuit side, the conductor pins are arranged so that the tops (top faces) thereof are slightly lower than the surface of the resin substrate, and therefore the conductor pin connection openings are formed. , A recess formed on the top of each conductor pin so as to be surrounded by this resin substrate.
By doing so, the wiring board can be positioned and temporarily fixed.
【０００９】前記「有機系樹脂基板」には、前記半導体
素子の一方の面に当接するように、周囲に凸部を有する
金属板又はセラミックス板（以下、金属板等という。）
が埋設されており、更に、前記金属板等の前記半導体と
の当接面と反対側の面が外表面に露出されているものと
することができる。更に、前記「有機系樹脂基板」は、
前記導体ピン及び前記金属板等を所定の型内の所定位置
に配設し、該型内の他の空間内に所定樹脂を充填して、
一体成形することにより製造されるものとすることがで
きる。The "organic resin substrate" has a metal plate or a ceramic plate (hereinafter referred to as a metal plate or the like) having a convex portion on its periphery so as to come into contact with one surface of the semiconductor element.
Can be embedded, and the surface of the metal plate or the like opposite to the contact surface with the semiconductor can be exposed on the outer surface. Furthermore, the “organic resin substrate” is
The conductor pin, the metal plate, etc. are arranged at predetermined positions in a predetermined mold, and a predetermined resin is filled in another space in the mold,
It can be manufactured by being integrally molded.
【００１０】[0010]
【作用】本発明においては、導体ピンの大径部より内径
の小さい貫通孔に導体ピンが嵌入により固着されている
ので、この導体ピンの樹脂基板に対する固着状態は強固
なものとなり、抜けにくくなる。また、本発明におい
て、導体ピンの支持は、樹脂基板にて行うとともに、導
体回路はこれと別体のプリント配線基板に形成されてい
るので、この導体ピンの嵌入によって、この樹脂基板の
変形、破損が生じても、導体回路に実質上悪影響がな
い。従って、たとえ破損が生じても導体回路と導体ピン
との電気的接合の信頼性に欠けることもないか又は著し
く少ない。更に、本発明において、導体ピンと配線基板
の導体回路との接続は、はんだ付けにより行われるの
で、非常に信頼性の高い電気的接合が可能となる。ま
た、第１発明のように、導体ピンを突出させた構成の場
合は、この突出部が樹脂基板とプリント基板との横スベ
リを防止するので、両者の脱落の危険が更に少なくな
る。更に、本発明においては、低融点のはんだ接合を解
除すれば配線基板と樹脂基板とは分離するので、もし何
らかの事情により両者を分離したい場合は、容易に取り
外しができるとともに、他基板との取り替えも容易にで
きる。In the present invention, since the conductor pin is fixed to the through hole having the inner diameter smaller than that of the large diameter portion of the conductor pin by fitting, the fixing state of the conductor pin to the resin substrate becomes strong and it is difficult to pull it out. . Further, in the present invention, the support of the conductor pin is performed by the resin substrate, and since the conductor circuit is formed on the printed wiring board which is a separate body from this, the deformation of the resin substrate by the fitting of the conductor pin, Even if damage occurs, the conductor circuit is not substantially adversely affected. Therefore, even if damage occurs, the reliability of the electrical connection between the conductor circuit and the conductor pin is not deteriorated or is extremely small. Further, in the present invention, since the connection between the conductor pin and the conductor circuit of the wiring board is performed by soldering, very reliable electrical connection can be achieved. Further, in the case of the structure in which the conductor pin is projected as in the first aspect of the present invention, this projecting portion prevents lateral slippage between the resin substrate and the printed circuit board, so that the risk of both falling off is further reduced. Further, in the present invention, the wiring board and the resin board are separated by releasing the low-melting point solder joint, so if for some reason they are to be separated, they can be easily removed and replaced with another board. Can be done easily.
【００１１】[0011]
【実施例】以下、実施例により本発明を具体的に説明す
る。本発明のピングリッドアレイパッケージ基板の一実
施例を図１の斜視図に示す。図１において、 (1)は有機
系樹脂基板（以下ベース基板という。）であり、例えば
エポキシ樹脂、ポリイミド樹脂、トリアジン樹脂等から
成る。 (2)はベース基板 (1)に嵌入固着された入出力用
の導体ピンである。 (3)は有機系樹脂素材からなるフィ
ルム状配線基板であり、例えばガラスエポキシ基板、ガ
ラスポリイミド基板、ガラストリアジン基板、ポリイミ
ド基板等を用いる。 (4)は配線基板 (3)に形成された半
導体素子搭載用開口部であり、 (5)は導体ピン接続用開
口部である。それぞれの開口部(4)(5)はパンチング加工
等により形成される。 (6)は配線基板 (3)表面に、開口
部(4)(5)に導体部が露出するように形成された導体回路
である。 (7)は配線基板 (3)に搭載された半導体素子で
あり、導体回路 (6)と熱圧着ボンディングにより接続さ
れている。EXAMPLES The present invention will be specifically described below with reference to examples. One embodiment of the pin grid array package substrate of the present invention is shown in the perspective view of FIG. In FIG. 1, (1) is an organic resin substrate (hereinafter referred to as a base substrate), which is made of, for example, an epoxy resin, a polyimide resin, a triazine resin, or the like. Reference numeral (2) is an input / output conductor pin fitted and fixed to the base substrate (1). (3) is a film-like wiring substrate made of an organic resin material, and for example, a glass epoxy substrate, a glass polyimide substrate, a glass triazine substrate, a polyimide substrate or the like is used. (4) is a semiconductor element mounting opening formed in the wiring board (3), and (5) is a conductor pin connecting opening. The openings (4) and (5) are formed by punching or the like. Reference numeral (6) is a conductor circuit formed on the surface of the wiring board (3) such that the conductor portion is exposed in the openings (4) and (5). A semiconductor element (7) is mounted on the wiring board (3) and is connected to the conductor circuit (6) by thermocompression bonding.
【００１２】図２及び図３は、ベース基板 (1)とそれに
嵌入固着された導体ピン (2)の縦断面図である。図２に
おいて、 (8)は、導体ピン (2)の大径部であり導体ピン
(2)の中間部に形成される。大径部 (8)を有する導体ピ
ン (2)は、金属線からプレス加工されるものであり、金
属線の材質としては鉄、鉄系合金、銅、銅系合金等が好
ましく、例えば４２アロイ、コバール、リン青銅等があ
る。金属線からプレス加工された導体ピン (2)表面に
は、金、白金、銀、スズ、はんだ等の金属メッキを施す
ことにより、金属線の腐蝕を防止することが可能であ
る。 (9)は導体ピン(2)の頂部であり、ベース基板 (1)
の半導体素子搭載面側に突出しており、配線基板 (3)の
導体回路 (6)と接続する際の位置合わせや仮止めの役割
を果たすものである。ベース基板 (1)は、有機系樹脂素
材のトランスファーモールド等により形成される。その
後、大径部 (8)より内径の小さい貫通孔(16)をドリル加
工により形成し、大径部 (8)を貫通孔(16)に嵌入するこ
とにより、導体ピン (2)はベース基板 (1)に固着され
る。大径部 (8)は、ベース基板 (1)と導体ピン (2)との
固着強度を増す役割を果たすものである。（10) は半導
体素子 (7)が搭載される部分を示し、成形により凹部と
なるよう形成することもできる。2 and 3 are vertical sectional views of the base substrate (1) and the conductor pins (2) fitted and fixed thereto. In Fig. 2, (8) is a large diameter part of the conductor pin (2)
It is formed in the middle part of (2). The conductor pin (2) having the large diameter portion (8) is pressed from a metal wire, and the material of the metal wire is preferably iron, iron-based alloy, copper, copper-based alloy or the like, for example, 42 alloy. , Kovar, phosphor bronze, etc. Corrosion of the metal wire can be prevented by plating the surface of the conductor pin (2) pressed from the metal wire with a metal such as gold, platinum, silver, tin, or solder. (9) is the top of the conductor pin (2) and the base substrate (1)
It protrudes to the semiconductor element mounting surface side and plays a role of alignment and temporary fixing when connecting to the conductor circuit (6) of the wiring board (3). The base substrate (1) is formed by transfer molding or the like of an organic resin material. After that, a through hole (16) having an inner diameter smaller than that of the large diameter portion (8) is formed by drilling, and the large diameter portion (8) is fitted into the through hole (16), so that the conductor pin (2) becomes a base substrate. It is fixed to (1). The large diameter portion (8) plays a role of increasing the bonding strength between the base substrate (1) and the conductor pin (2). Reference numeral (10) denotes a portion on which the semiconductor element (7) is mounted, and it can be formed into a recess by molding.
【００１３】図３において、(11)は導体ピン (2)の頂部
に形成された金属バンプであり、材質としてははんだ等
がある。導体ピン (2)は埋設によりベース基板 (1)に固
着されるが、導体ピン (2)の頂部はベース基板 (1)の半
導体素子搭載面側には突出せず、同一面に形成される。
そして、導体ピン (2)の頂部に形成された金属バンプ(1
1)は、配線基板 (3)の導体回路 (6)と導体ピン (2)の電
気的接続のみならず、接続する際の位置合わせや仮止め
の役割を果たすものである。次に、本発明のピングリッ
ドアレイパッケージ基板におけるベース基板 (1)と、配
線基板 (3)の接続について説明する。図４及び図５は、
ベース基板 (1)に配線基板 (3)が接続された状態の縦断
面図である。In FIG. 3, (11) is a metal bump formed on the top of the conductor pin (2), and the material thereof is solder or the like. The conductor pin (2) is fixed to the base substrate (1) by embedding, but the top of the conductor pin (2) does not protrude to the semiconductor element mounting surface side of the base substrate (1) but is formed on the same surface. .
Then, the metal bumps (1
1) not only serves to electrically connect the conductor circuit (6) of the wiring board (3) and the conductor pin (2), but also serves as alignment and temporary fixing at the time of connection. Next, the connection between the base substrate (1) and the wiring substrate (3) in the pin grid array package substrate of the present invention will be described. 4 and 5 show
FIG. 3 is a vertical cross-sectional view showing a state where the wiring board (3) is connected to the base board (1).
【００１４】図４において、半導体素子 (7)が搭載され
た配線基板 (3)は、ベース基板 (1)に固着された導体ピ
ン (2)の頂部に半導体素子 (7)搭載面側に突出するよう
に形成された金属バンプ(11)と、各導体ピン (2)に対応
する配線基板 (3)の導体ピン接続用開口部 (5)とにより
整合位置決めされ仮固定される。そして導体回路 (6)の
導体ピン接続用開口部 (5)の付近に超音波、又は熱を与
えることにより、導体回路 (6)と金属バンプ(11)は電気
的及び機械的に接続される。これにより、配線基板 (3)
はベース基板 (1)に固着され、半導体素子 (7)と各導体
ピン (2)は電気的に接続される。In FIG. 4, the wiring board (3) on which the semiconductor element (7) is mounted protrudes toward the semiconductor element (7) mounting surface side from the top of the conductor pin (2) fixed to the base board (1). The metal bumps (11) thus formed and the conductor pin connection openings (5) of the wiring board (3) corresponding to the conductor pins (2) are aligned and temporarily fixed. The conductor circuit (6) and the metal bumps (11) are electrically and mechanically connected by applying ultrasonic waves or heat to the vicinity of the conductor pin connection opening (5) of the conductor circuit (6). . This allows wiring boards (3)
Is fixed to the base substrate (1), and the semiconductor element (7) and each conductor pin (2) are electrically connected.
【００１５】尚、金属バンプ(11)の形成される位置は、
ベース基板 (1)に固着された導体ピン (2)の頂部のみに
限られるものではなく、各導体ピン (2)に対応するよう
に導体回路 (6)の導体ピン (2)接合面側に突出するよう
に形成してもよい。この場合は、導体ピンを嵌入する
際、各導体ピンの頂部が樹脂基板の表面よりもやや低く
なるようにして、各導体ピンの頂部上に導体ピン接続用
開口部（凹部）が形成されることとなる。この場合も、
半導体素子 (7)が搭載された配線基板 (3)は導体回路
(6)に形成された金属バンプと、各導体ピン (2)に対応
する配線基板 (3)の導体ピン接続用開口部 (5)とにより
整合位置決めされ仮固定される。The position where the metal bump (11) is formed is
It is not limited to only the tops of the conductor pins (2) fixed to the base board (1), but to the conductor pin (2) joint surface side of the conductor circuit (6) so as to correspond to each conductor pin (2). You may form so that it may protrude. In this case, when the conductor pins are fitted, the conductor pin connection openings (recesses) are formed on the tops of the conductor pins such that the tops of the conductor pins are slightly lower than the surface of the resin substrate. It will be. Also in this case,
The wiring board (3) on which the semiconductor element (7) is mounted is a conductor circuit.
The metal bumps formed on (6) and the conductor pin connection openings (5) of the wiring board (3) corresponding to each conductor pin (2) are aligned and temporarily fixed.
【００１６】図５において、半導体素子 (7)が搭載され
た配線基板 (3)は、各導体ピン (2)に対応する位置に導
体ピン接続用開口部（本例では貫通孔形状） (5)が形成
され、導体ピン接続用開口部 (5)の周囲にも半導体素子
(7)と接続する導体回路 (6)が形成されている。そし
て、この配線基板 (3)は、ベース基板 (1)に嵌入固着さ
れた導体ピン (2)の半導体素子 (7)搭載面側に突出した
頂部 (9)と半導体ピン接続用開口部 (5)により、整合位
置決めされ仮固定される。そして導体回路 (6)と頂部
(9)は、はんだ(12)により接続され、配線基板 (3)はベ
ース基板 (1)に固着され、半導体素子(7)と各導体ピン
(2)は電気的に接続される。このようにして接続された
導体ピン (2)と導体回路 (6)の導通性、及び接続信頼性
は非常に高く、また導体ピン (2)はベース基板 (1)に確
実に固着されているため、振動や衝撃によって脱落した
り、接合が緩んだりすることはない。尚、ここでいうは
んだ(12)による接続は、仮固定の後、別途用意したはん
だ(12)により行うもののみをいうのではなく、はんだ(1
2)により形成される金属バンプを予め各導体ピン (2)の
頂部、又は各導体ピン (2)に対応するように導体回路
(6)の導体ピン (2)接合面側に突出するように設けて接
続を行うものをも含んでいる。In FIG. 5, the wiring board (3) on which the semiconductor element (7) is mounted is provided with conductor pin connection openings (through holes in this example) at positions corresponding to the conductor pins (2). ) Is formed, and the semiconductor element is also formed around the conductor pin connection opening (5).
A conductor circuit (6) connected to (7) is formed. The wiring board (3) has a top (9) protruding toward the semiconductor element (7) mounting surface side of the conductor pin (2) fitted and fixed to the base board (1) and a semiconductor pin connection opening (5). ), It is aligned and temporarily fixed. And the conductor circuit (6) and the top
(9) is connected by solder (12), wiring board (3) is fixed to base board (1), semiconductor element (7) and each conductor pin
(2) is electrically connected. The conductor pin (2) and the conductor circuit (6) connected in this way have very high conductivity and connection reliability, and the conductor pin (2) is securely fixed to the base substrate (1). Therefore, it will not fall off or the joint will not loosen due to vibration or shock. Incidentally, the connection with the solder (12) here does not mean only the solder (12) separately prepared after temporary fixing, but the solder (1
The metal bumps formed by 2) are previously placed on the conductor circuits so that they correspond to the tops of the conductor pins (2) or the conductor pins (2).
(6) Conductor pins (2) Also include those that are provided so as to project to the joint surface side for connection.
【００１７】図６は本発明の特徴の一つである金属板又
はセラミックスの板を装着した状態のピングリッドアレ
イパッケージ基板の縦断面図である。図６において、(1
3)は放熱板であり、(14)は放熱板(13)の周囲に形成され
た凸部であり、材質としては金属、セラミックス等の熱
放散性の高いものが好ましい。放熱板(13)の一方の面
は、半導体素子 (7)の一部（本例では下面）に当接し、
且つその反対面は外表面に露出するように、凸部(14)が
ベース基板 (1)に埋め込まれている。加熱板(13)はベー
ス基板 (1)の形成の際、治工具によって導体ピン (2)と
共に一体成型することにより、ベース基板 (1)中に埋設
される。凸部（14) は放熱板(13)とベース基板 (1)との
固着強度を増す役割を果たすもので、固着後、振動や衝
撃によって放熱板(13)が脱落したり、固着が緩んだりす
ることを防ぐ。このように放熱板(13)が装着されたピン
グリッドアレイパッケージ基板は、格段に熱放散性が向
上し、セラミックス基板とほぼ同等の熱放散性となり、
高出力、大消費電力の半導体素子 (7)の搭載に適合す
る。FIG. 6 is a vertical sectional view of a pin grid array package substrate in which a metal plate or a ceramic plate, which is one of the features of the present invention, is mounted. In FIG. 6, (1
3) is a heat radiating plate, (14) is a convex portion formed around the heat radiating plate (13), and the material is preferably metal, ceramics or the like having a high heat dissipation property. One surface of the heat sink (13) contacts a part of the semiconductor element (7) (lower surface in this example),
Moreover, the convex portion (14) is embedded in the base substrate (1) so that the opposite surface is exposed to the outer surface. When the base plate (1) is formed, the heating plate (13) is embedded in the base plate (1) by integrally molding it with the conductor pins (2) using a jig. The convex part (14) plays a role of increasing the fixing strength between the heat sink (13) and the base substrate (1). Prevent doing. In this way, the pin grid array package substrate with the heat sink (13) mounted has significantly improved heat dissipation, and has a heat dissipation almost equal to that of the ceramics substrate.
Suitable for mounting high power, high power semiconductor devices (7).
【００１８】図７は、本発明に係るピングリッドアレイ
パッケージ基板に樹脂封止した状態の該基板の縦断面図
である。図７において、(15)は封止用樹脂である。ベー
ス基板 (1)に配線基板 (3)を接続した。ピングリッドア
レイパッケージ基板の入出力用導体ピン (2)の突出する
面、すなわちマザーボード実装面以外の全面について、
トランスファモールド、又はキャスティングにより封止
する。これによりベース基板 (1)と配線基板 (3)は完全
に固着され、搭載された半導体素子 (7)を外界雰囲気と
完全に遮断することができ、高耐水性のピングリッドア
レイパッケージ基板を得ることができる。FIG. 7 is a vertical cross-sectional view of the pin grid array package substrate according to the present invention in a resin-sealed state. In FIG. 7, (15) is a sealing resin. The wiring board (3) was connected to the base board (1). Regarding the protruding surface of the input / output conductor pins (2) of the pin grid array package board, that is, the entire surface other than the motherboard mounting surface,
It is sealed by transfer molding or casting. As a result, the base substrate (1) and the wiring substrate (3) are completely fixed, the mounted semiconductor element (7) can be completely shielded from the external atmosphere, and a highly water resistant pin grid array package substrate is obtained. be able to.
【００１９】[0019]
【発明の効果】本発明のパッケージ基板においては、導
体ピンが抜けにくくなり、また、この導体ピンの嵌入に
よって、たとえ変形、破損が生じても導体回路と導体ピ
ンとの電気的接合の信頼性に欠けることもないか又は著
しく少なく、また樹脂基板とプリント基板との接合にも
優れる。更に、本パッケージ基板においては、配線基板
と樹脂基板とを容易に取り外しができるとともに、他基
板との取り替えも容易にできる。更に、貫通孔にはメッ
キが施されていないものの、確実な導通ができ、安価な
ものとすることができる。また、前記樹脂基板には、前
記半導体素子の一方の面に当接するように、周囲に凸部
を有する金属板等が埋設されており、更に、前記金属板
又は前記セラミック板の前記半導体との当接面と反対側
の面が外表面に露出されているものとする場合は、熱放
散性に優れるとともに、放熱板の脱落がない。In the package substrate of the present invention, the conductor pin is less likely to come off, and the fitting of the conductor pin makes it possible to improve the reliability of the electrical connection between the conductor circuit and the conductor pin even if the conductor pin is deformed or damaged. It is not chipped or extremely small, and it is also excellent in joining a resin substrate and a printed circuit board. Further, in this package board, the wiring board and the resin board can be easily removed and replaced with another board. Further, although the through hole is not plated, reliable conduction can be achieved and the cost can be reduced. Further, a metal plate or the like having a convex portion on the periphery thereof is embedded in the resin substrate so as to come into contact with one surface of the semiconductor element, and further, the metal plate or the ceramic plate with the semiconductor is embedded. When the surface opposite to the contact surface is exposed to the outer surface, the heat dissipation is excellent and the heat dissipation plate does not fall off.
【００２０】更に、導体ピン及び金属板等を有する樹脂
基板を一体成形してなるパッケージ基板においては、こ
の凸部を有する金属板等を無理に嵌入する必要がないの
で、熱放散性に優れるとともに、この樹脂基板の変形が
なく、更にこのような有用な多ピン構造のパッケージ基
板が容易に製造される。Further, in a package substrate formed by integrally molding a resin substrate having conductor pins and a metal plate or the like, it is not necessary to forcefully insert the metal plate or the like having the convex portion, so that it is excellent in heat dissipation. The resin substrate is not deformed, and such a useful package substrate having a multi-pin structure can be easily manufactured.
【図１】本発明に係る半導体素子搭載ピングリッドアレ
イパッケージ基板の斜視図である。FIG. 1 is a perspective view of a semiconductor element mounted pin grid array package substrate according to the present invention.
【図２】ベース基板に導体ピンが嵌入固着された状態の
縦断面図である。FIG. 2 is a vertical cross-sectional view showing a state in which conductor pins are fitted and fixed to a base substrate.
【図３】ベース基板に嵌入固着された導体ピンの頂部に
金属バンプが形成された状態の縦断面図である。FIG. 3 is a vertical cross-sectional view showing a state in which a metal bump is formed on the top of a conductor pin fitted and fixed to a base substrate.
【図４】半導体素子搭載フィルム状配線基板とベース基
板の接続方法の一例を示す縦断面図である。FIG. 4 is a vertical cross-sectional view showing an example of a method for connecting a semiconductor element-mounted film-like wiring board and a base board.
【図５】半導体素子搭載フィルム状配線基板とベース基
板の接続方法の他例を示す縦断面図である。FIG. 5 is a vertical cross-sectional view showing another example of a method for connecting a semiconductor element-mounted film-like wiring board and a base board.
【図６】放熱構造を有する半導体素子搭載ピングリッド
アレイパッケージ基板の縦断面図である。FIG. 6 is a vertical cross-sectional view of a semiconductor element mounted pin grid array package substrate having a heat dissipation structure.
【図７】半導体素子搭載ピングリッドアレイパッケージ
基板に樹脂封止した状態の縦断面図である。FIG. 7 is a vertical cross-sectional view showing a state in which a semiconductor element mounted pin grid array package substrate is resin-sealed.
１；ベース基板、２；導体ピン、３；フィルム状配線基
板、４；半導体素子搭載用開口部、５；導体ピン接続用
開口部、６；導体回路、７；半導体素子、８；大径部、
９；頂部、１０；凹部、１１；金属バンプ、１２；はん
だ、１３；放熱板、１４；凸部、１５；封止用樹脂、１
６；貫通孔。DESCRIPTION OF SYMBOLS 1; Base board, 2; Conductor pin, 3; Film wiring board, 4; Opening part for semiconductor element mounting, 5; Opening part for connecting conductor pin, 6; Conductor circuit, 7; Semiconductor element, 8; Large diameter part ,
9; top part, 10; concave part, 11; metal bump, 12; solder, 13; heat sink, 14; convex part, 15; sealing resin, 1
6; through hole.
Claims (4)
接続される所定の導体回路を有する樹脂製フィルム状プ
リント配線基板と、所定位置に嵌入固着される複数の導
体ピンを有する有機系樹脂基板とから成り、更に前記導
体回路と前記導体ピンとははんだにより電気的に接続さ
れている半導体素子搭載ピングリッドアレイパッケージ
基板であって、 前記導体ピンは中間部に大径部が形成され、該導体ピン
の大径部より内径の小さい貫通孔に嵌入固着され、且つ
前記大径部は前記有機系樹脂基板内に埋設され、更に、
該各導体ピンの頂部が前記有機系樹脂基板の表面から突
出し、 また、前記プリント配線基板及び前記導体回路のうちの
少なくとも該プリント配線基板には、前記各導体ピンの
頂部に対応する位置に導体ピン接続用開口部を有し、且
つ該各導体ピンの頂部と該接続用開口部とは嵌め合わさ
れていることを特徴とする半導体素子搭載ピングリッド
アレイパッケージ基板。1. A resin film-shaped printed wiring board having a predetermined conductor circuit for mounting a semiconductor element and connected to the semiconductor element, and an organic resin board having a plurality of conductor pins fitted and fixed at predetermined positions. A semiconductor element mounting pin grid array package substrate in which the conductor circuit and the conductor pin are electrically connected by soldering, wherein the conductor pin has a large diameter portion formed at an intermediate portion, The pin is fitted and fixed in a through hole having an inner diameter smaller than that of the large diameter portion, and the large diameter portion is embedded in the organic resin substrate.
The tops of the conductor pins project from the surface of the organic resin substrate, and at least the printed wiring board and the conductor circuit have conductors at positions corresponding to the tops of the conductor pins. 2. A semiconductor element mounting pin grid array package board having pin connection openings, wherein the tops of the conductor pins and the connection openings are fitted together.
接続される所定の導体回路を有する樹脂製フィルム状プ
リント配線基板と、所定位置に嵌入固着される複数の導
体ピンを有する有機系樹脂基板とから成り、更に前記導
体回路と前記導体ピンとははんだにより電気的に接続さ
れている半導体素子搭載ピングリッドアレイパッケージ
基板であって、 前記導体ピンは中間部に大径部が形成され、該導体ピン
の大径部より内径の小さい貫通孔に嵌入固着され、且つ
前記大径部は前記有機系樹脂基板内に埋設され、更に、
前記各導体ピンの頂部が前記有機系樹脂基板の表面と同
一面又は該表面よりも低い面になるようにし、 また、前記プリント配線基板と前記導体回路との間に形
成される空間にはんだが充填されており、該はんだによ
り前記導体回路と前記導体ピンとを電気的に接続してい
ることを特徴とする半導体素子搭載ピングリッドアレイ
パッケージ基板。2. A resin film-shaped printed wiring board having a predetermined conductor circuit mounted on the semiconductor element and connected to the semiconductor element, and an organic resin board having a plurality of conductor pins fitted and fixed at predetermined positions. A semiconductor element mounting pin grid array package substrate in which the conductor circuit and the conductor pin are electrically connected by soldering, wherein the conductor pin has a large diameter portion formed at an intermediate portion, The pin is fitted and fixed in a through hole having an inner diameter smaller than that of the large diameter portion, and the large diameter portion is embedded in the organic resin substrate.
The tops of the conductor pins are on the same surface as the surface of the organic resin substrate or a surface lower than the surface, and solder is placed in the space formed between the printed wiring board and the conductor circuit. A pin grid array package substrate mounted with a semiconductor element, which is filled and electrically connects the conductor circuit and the conductor pin by the solder.
子の一方の面に当接するように、周囲に凸部を有する金
属板又はセラミックス板が埋設されており、更に、該金
属板又は該セラミック板の前記半導体との当接面と反対
側の面が外表面に露出されていることを特徴とする請求
項１又は２記載の半導体素子搭載ピングリッドアレイパ
ッケージ基板。3. The organic resin substrate is embedded with a metal plate or a ceramic plate having a convex portion on its periphery so as to be in contact with one surface of the semiconductor element. 3. The semiconductor element mounted pin grid array package substrate according to claim 1, wherein a surface of the ceramic plate opposite to the contact surface with the semiconductor is exposed on the outer surface.
び前記金属板若しくは前記セラミック板を所定の型内の
所定位置に配設し、該型内の他の空間内に所定樹脂を充
填して、一体成形することにより製造されたものである
請求項第３項記載の半導体素子搭載ピングリッドアレイ
パッケージ基板。4. The organic resin substrate has the conductor pin and the metal plate or the ceramic plate arranged at a predetermined position in a predetermined mold, and the other space in the mold is filled with a predetermined resin. The semiconductor device mounted pin grid array package substrate according to claim 3, which is manufactured by integrally molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4339621A JPH0812895B2 (en) | 1992-11-26 | 1992-11-26 | Semiconductor device mounted pin grid array package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4339621A JPH0812895B2 (en) | 1992-11-26 | 1992-11-26 | Semiconductor device mounted pin grid array package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06204385A true JPH06204385A (en) | 1994-07-22 |
| JPH0812895B2 JPH0812895B2 (en) | 1996-02-07 |
Family
ID=18329233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4339621A Expired - Lifetime JPH0812895B2 (en) | 1992-11-26 | 1992-11-26 | Semiconductor device mounted pin grid array package substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812895B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001035459A1 (en) * | 1999-11-10 | 2001-05-17 | Ibiden Co., Ltd. | Ceramic substrate |
| JP2001284420A (en) * | 2000-02-14 | 2001-10-12 | Advantest Corp | Contact structure and its manufacturing method |
| KR100481424B1 (en) * | 1998-05-29 | 2005-06-08 | 삼성전자주식회사 | Method for manufacturing chip scale package |
| JP2010129646A (en) * | 2008-11-26 | 2010-06-10 | Seiko Instruments Inc | Package member and electronic component package |
| CN108417552A (en) * | 2018-02-05 | 2018-08-17 | 安徽双威微电子有限公司 | A kind of microcard super high power device |
| CN113380756A (en) * | 2021-07-07 | 2021-09-10 | 广东汇芯半导体有限公司 | Semiconductor circuit and method for manufacturing the same |
| CN115298814A (en) * | 2021-03-03 | 2022-11-04 | 香港应用科技研究院有限公司 | Electronic module with groove for anchoring terminal pin |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62242348A (en) * | 1986-04-14 | 1987-10-22 | Matsushita Electric Works Ltd | Pin grid array |
-
1992
- 1992-11-26 JP JP4339621A patent/JPH0812895B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62242348A (en) * | 1986-04-14 | 1987-10-22 | Matsushita Electric Works Ltd | Pin grid array |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100481424B1 (en) * | 1998-05-29 | 2005-06-08 | 삼성전자주식회사 | Method for manufacturing chip scale package |
| WO2001035459A1 (en) * | 1999-11-10 | 2001-05-17 | Ibiden Co., Ltd. | Ceramic substrate |
| US6632512B1 (en) | 1999-11-10 | 2003-10-14 | Ibiden Co., Ltd. | Ceramic substrate |
| US6919124B2 (en) | 1999-11-10 | 2005-07-19 | Ibiden Co., Ltd. | Ceramic substrate |
| JP2001284420A (en) * | 2000-02-14 | 2001-10-12 | Advantest Corp | Contact structure and its manufacturing method |
| JP2010129646A (en) * | 2008-11-26 | 2010-06-10 | Seiko Instruments Inc | Package member and electronic component package |
| CN108417552A (en) * | 2018-02-05 | 2018-08-17 | 安徽双威微电子有限公司 | A kind of microcard super high power device |
| CN115298814A (en) * | 2021-03-03 | 2022-11-04 | 香港应用科技研究院有限公司 | Electronic module with groove for anchoring terminal pin |
| CN113380756A (en) * | 2021-07-07 | 2021-09-10 | 广东汇芯半导体有限公司 | Semiconductor circuit and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0812895B2 (en) | 1996-02-07 |
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