JPS6135695B2 - - Google Patents
Info
- Publication number
- JPS6135695B2 JPS6135695B2 JP12732778A JP12732778A JPS6135695B2 JP S6135695 B2 JPS6135695 B2 JP S6135695B2 JP 12732778 A JP12732778 A JP 12732778A JP 12732778 A JP12732778 A JP 12732778A JP S6135695 B2 JPS6135695 B2 JP S6135695B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- electrode
- plasma
- insulating cover
- convex portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 27
- 239000000463 material Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036470 plasma concentration Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明はウエハにプラズマ処理を施す装置、例
えば、Ga,Asのウエハに絶縁膜を形成すべくプ
ラズマ陽極酸化処理を施す装置における電極装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode device in an apparatus that performs plasma processing on a wafer, for example, an apparatus that performs plasma anodic oxidation processing to form an insulating film on a Ga or As wafer.
従来この種装置として、電極の上面にウエハを
載置してこれにプラズマ処理を施す式のものは知
られるが、この場合プラズマ処理の進行によれば
該ウエハは膜形成により漸次電気低抗を増大さ
れ、したがつて該ウエハに流れる有効電流が漸次
減少し、かくて該電極の上面に直接流れる電流が
漸次増大する傾向となり、膜形成の進行が損われ
る不都合を伴う。かゝる不都合を無くすべく、該
電極の上面に、該ウエハの載置個所を透窓に残し
て、絶縁カバを施すことは考えられるが、かゝる
ものでは、該ウエハに多少とも寸法誤差が存する
とき、これに良好に適合しない。 Conventionally, this type of apparatus is known in which a wafer is placed on the top surface of an electrode and subjected to plasma treatment, but in this case, as the plasma treatment progresses, the wafer gradually loses electrical resistance due to film formation. The effective current flowing through the wafer is increased and therefore the effective current flowing through the wafer gradually decreases, and thus the current flowing directly onto the top surface of the electrode tends to gradually increase, with the disadvantage that the progress of film formation is impaired. In order to eliminate such inconvenience, it is conceivable to cover the upper surface of the electrode with an insulating cover, leaving the place where the wafer is placed in the transparent window, but in such a case, there is some dimensional error in the wafer. does not fit well when present.
即ち、該ウエハが比較的大きいときは、該透窓
内に嵌合せず、かくて該電極の上面と接触しない
と共に、該ウエハが比較的小さいときは該透窓内
に外周の隙間を生じ、これにプラズマの集中その
他を生じ易い。 That is, when the wafer is relatively large, it does not fit into the transparent window and thus does not come into contact with the top surface of the electrode, and when the wafer is relatively small, a gap is created at the outer periphery within the transparent window, This tends to cause plasma concentration and other problems.
本発明はかゝる不都合のない装置を得ることを
その目的としたもので、電極の上面にウエハを載
置してこれにプラズマ処理を施す式のものにおい
て、該電極の上面を、該ウエハの載置個所におい
て上方に突出する凸部に形成させると共にその残
部に石英その他の絶縁カバを施して成る。 The object of the present invention is to obtain an apparatus free of such inconveniences, and in a type in which a wafer is placed on the upper surface of an electrode and subjected to plasma processing, the upper surface of the electrode is placed on the wafer. A convex portion protruding upward is formed at the mounting location, and the remaining portion is covered with an insulating cover made of quartz or other material.
本発明実施の1例を別紙図面に付説明する。 An example of implementing the present invention will be explained with reference to the attached drawings.
図面で1はアルミ電極その他の電極を示し、該
電極1はこれに外部の電源から正のバイアス電圧
を印加されるようにした。該電極1の上面にウエ
ハ2を載置してこれにプラズマ処理を施すべきも
ので、該電極1の上面を該ウエハ2の載置個所に
おいて上方に突出する凸部3に形成させると共に
その残部に石英その他の絶縁カバ4を施す。図示
のものでは、該凸物3をアルミその他のデイスク
で構成させ、これを該上記に予め形成される凹筐
5内に嵌合して結着するようにした。更に該凸部
3は図示のように必要に応じその複数個を配致し
てウエハ2の複数枚に備えるようにし、更に該凸
部3はこれに載置される該ウエハ2に対し少しく
小面積に作るが一般である。図示のものではウエ
ハ2を略扇形とし、凸部3をこれに略内接する円
形とした。絶縁カバ4は前記したように石英その
他から成りその残部を被包して施されるもので、
その肉厚を比較的減少させて凸部3の突出高さを
こえないものとし、換言すれば凸部3は該カバ4
の上面をこえて少しく上方に突出するが一般であ
る。 In the drawings, reference numeral 1 indicates an aluminum electrode or other electrode, and a positive bias voltage is applied to the electrode 1 from an external power source. A wafer 2 is placed on the upper surface of the electrode 1 and subjected to plasma treatment, and the upper surface of the electrode 1 is formed into a convex portion 3 that protrudes upward at the location where the wafer 2 is placed, and the remaining portion is An insulating cover 4 made of quartz or other material is applied to the surface. In the illustrated embodiment, the protrusion 3 is made of a disk made of aluminum or other material, and is fitted and bonded into the concave casing 5 previously formed above. Furthermore, as shown in the figure, a plurality of convex portions 3 are arranged as necessary to provide for a plurality of wafers 2, and furthermore, the convex portions 3 have a slightly smaller area than the wafer 2 placed thereon. It is common to make it. In the illustrated embodiment, the wafer 2 has a substantially sector-shaped shape, and the convex portion 3 has a circular shape substantially inscribed therein. As mentioned above, the insulating cover 4 is made of quartz or other material and is applied by covering the remaining part of the insulating cover 4.
Its wall thickness is relatively reduced so that it does not exceed the protruding height of the convex part 3, in other words, the convex part 3 covers the cover 4.
Generally, it protrudes slightly upwards beyond the upper surface of the.
図面で6は該電極1の内部の水冷用のジヤケツ
ト、7は外周の筒状のシールドを示す。尚前記し
た凸部3と絶縁カバ4とは予め別個に用意するこ
となく、夫々蒸着、スパツタリングその他の膜形
成手段により該電極1の上面にこれと一体型に作
ることも可能である。 In the drawings, reference numeral 6 indicates a jacket for water cooling inside the electrode 1, and reference numeral 7 indicates a cylindrical shield on the outer periphery. Note that the convex portion 3 and the insulating cover 4 described above do not have to be prepared separately in advance, but can be formed integrally with the upper surface of the electrode 1 by vapor deposition, sputtering, or other film forming means.
その作動を説明するに、ウエハ2を凸部3上に
載置してこれと接触させればプラズマは該ウエハ
2に集中して作用してこれに例えば酸化絶縁被膜
を作るもので、この間該電極1の上面の残部はカ
バ4が存してプラズマの作用がなく、更にこの際
該ウエハ2は該凸部3で支承されて該カバ4の上
方に露出した状態に存し、かくてこれに全面に亘
り良好なプラズマ処理を与え得られると共に該ウ
エハ2が多少とも寸法誤差を有する場合もこれに
良好に適合される。 To explain its operation, when the wafer 2 is placed on the convex part 3 and brought into contact with it, the plasma concentrates on the wafer 2 and forms an oxide insulating film thereon. The remaining part of the upper surface of the electrode 1 is covered with a cover 4 and is not affected by plasma, and furthermore, at this time, the wafer 2 is supported by the protrusion 3 and exposed above the cover 4. It is possible to provide good plasma processing over the entire surface of the wafer 2, and even if the wafer 2 has some dimensional error, it can be well adapted to this.
即ち比較的大きい場合も比較的小さい場合も、
凸部3上にそのまゝ載置されてそれと良好に接触
し、前記した透窓式のものにおける不都合を生じ
ない。 In other words, whether it is relatively large or relatively small,
It is placed directly on the convex portion 3 and makes good contact with it, and does not cause the disadvantages of the transparent window type described above.
このように本発明によるときはプラズマはウエ
ハに集中して作用し、電流の流れる経路が一定し
電流密度が均一にとれるもので、電極上面に直接
電流が流れる従来のものの前記した不都合を無く
し得られ更に該凸部は該ウエハを該カバの上方に
露出状態に保持してこれに良好な処理を与えると
共に該ウエハの寸法誤差にも良好に適合する等の
効果を有する。 In this way, according to the present invention, the plasma acts concentratedly on the wafer, the path through which the current flows is constant, and the current density can be maintained uniformly, thereby eliminating the above-mentioned disadvantages of the conventional method in which the current flows directly on the upper surface of the electrode. Moreover, the convex portion has the effect of holding the wafer in an exposed state above the cover to provide good processing to the wafer, and also being able to accommodate dimensional errors of the wafer.
第1図は本発明装置の1例の截断側面図、第2
図はその上面図である。
1……電極、2……ウエハ、3……凸部、4…
…絶縁カバ。
Fig. 1 is a cutaway side view of one example of the device of the present invention;
The figure is a top view. 1... Electrode, 2... Wafer, 3... Convex part, 4...
...Insulating cover.
Claims (1)
マ処理を施す式のものにおいて、該電極の上面
を、該ウエハの載置個始において上方に突出する
凸部に形成させると共にその残部に石英その他の
絶縁カバを施して成るプラズマ処理装置における
電極装置。1. In a type in which a wafer is placed on the top surface of an electrode and subjected to plasma treatment, the top surface of the electrode is formed into a convex portion that protrudes upward at the beginning of the placement of the wafer, and the remainder is covered with quartz. An electrode device in a plasma processing apparatus provided with another insulating cover.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12732778A JPS5555530A (en) | 1978-10-18 | 1978-10-18 | Electrode device for plasma processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12732778A JPS5555530A (en) | 1978-10-18 | 1978-10-18 | Electrode device for plasma processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5555530A JPS5555530A (en) | 1980-04-23 |
JPS6135695B2 true JPS6135695B2 (en) | 1986-08-14 |
Family
ID=14957180
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12732778A Granted JPS5555530A (en) | 1978-10-18 | 1978-10-18 | Electrode device for plasma processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5555530A (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5758320A (en) * | 1980-09-24 | 1982-04-08 | Hitachi Ltd | Work mounting stage in plasma asher device |
JPS57167630A (en) * | 1981-03-13 | 1982-10-15 | Fujitsu Ltd | Plasma vapor-phase growing device |
JPS60201632A (en) * | 1984-03-27 | 1985-10-12 | Anelva Corp | Dry etching apparatus |
US4776389A (en) * | 1986-02-03 | 1988-10-11 | Hughes Aircraft Company | Method and apparatus for evacuating and filling heat pipes and similar closed vessels |
JP2548164B2 (en) * | 1987-01-19 | 1996-10-30 | 松下電器産業株式会社 | Dry etching method |
US4872172A (en) * | 1987-11-30 | 1989-10-03 | Tandem Computers Incorporated | Parity regeneration self-checking |
JPH03181128A (en) * | 1989-12-11 | 1991-08-07 | Tokyo Electron Ltd | Plasma device |
JP2553256B2 (en) * | 1991-02-12 | 1996-11-13 | 富士通株式会社 | Plasma vapor deposition method |
JP2758755B2 (en) * | 1991-12-11 | 1998-05-28 | 松下電器産業株式会社 | Dry etching apparatus and method |
-
1978
- 1978-10-18 JP JP12732778A patent/JPS5555530A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5555530A (en) | 1980-04-23 |
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