JPS61139998A - Data writing device for writable rom - Google Patents

Abstract

PURPOSE:To improve the efficiency of writing on ROMs for an 8-bit and a 16-bit microcomputer by providing a circuit which judges whether the address signal of data read out of a RAM is even or odd. CONSTITUTION:When data is written on a ROM for an 8-bit microcomputer, a selection switch 14 is placed at the side of the 8-bit microcomputer and then an inhibiting signal is applied from an IC unit 10 for signal switching to the control terminal of one of IC sockets 7 and 8 to write the data on only one ROM. When data is written on two ROMs for a 16-bit microcomputer, the switch 14 is placed at the side of the 16-bit microcomputer and then data read out of the RAM6 is passed through even-odd switching circuits 10-13 to write data whose address signal is even in, for example, the 1st ROM and data whose address signal is even in the 2nd ROM.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data writing device for a writable ROM incorporated in a microcomputer, and particularly relates to a data writing device for a ROM for an 8-bit microcomputer. Easy ROM for 16-bit microcomputer
The present invention relates to a data writing device for a writable ROM that can also write data to a writable ROM.

[Prior art] A microcomputer stores data (
EP that can be electrically written by the user (bit contents) and erased by ultraviolet irradiation.

ROM (erasable, programmable, readable.

There are some that incorporate memory. For example, a data writing device shown in FIG. 3 is used to write data such as control programs into such a writable ROM.

Figure 3 shows a ROM built into an 8-bit microcomputer.
The IC socket 1 is used to write data into the IC socket 1, and various terminals such as a data terminal of the ROM to which data is to be written, an address terminal, and a chip select terminal are inserted into the IC socket 1. Then, each address terminal (A
O-AN) and each data terminal (DO to D7) connect to this R
RAM that stores data to be written to OM (random).

Access, memory) 2 address terminals (AO to AN1
) and each data terminal (DO-D7"). Also, each address terminal (AO-ANl) of RAM2
And each data terminal (Do-D7) is connected to each address terminal (AO to AN2-) and data terminal (Do to
07).

In the data writing device configured in this way, the CPU
3 sequentially reads each data stored in each address of the RAM 2 and sequentially writes it into each address area of the ROM inserted into the IC socket 1. Therefore, the data stored in the RAM 2 is written directly to the ROM. [Problems to be Solved by the Invention]- However, the above-described data writing device still has the following problems that must be solved. That is, although 16-bit microcomputers have been used in recent years, the R
A data storage device for OM cannot directly write data to a writable ROM built into a 16-bit microcomputer.

Therefore, we created an RO for two 8-bit microcomputers.
Write data corresponding to even addresses into one ROM using the data writing device shown in FIG.
Data corresponding to odd addresses is written into the other ROM. Then, the two ROMs are incorporated into a 16-bit microcomputer. However, in order to write data to a ROM for a 16-bit microcomputer, it is necessary to divide the data into RAM 2 and store it into even address and odd address data.

The task of dividing and storing a series of data into those for even addresses and those for odd addresses is very complicated.

In addition, write operations for even number ROM and odd number RO
It is necessary to perform two operations, one for M and the other for writing. Therefore, there is a problem that the efficiency of writing into the ROM is reduced.

The present invention has been made based on the above-mentioned circumstances, and its purpose is to provide an even/odd number switching circuit that determines whether the address signal of the data read from the RAM is even or odd. In addition to being able to write to the ROM for computers, it is also possible to easily write to the ROM of a 16-bit microcomputer.
It is an object of the present invention to provide a data writing device for a writable ROM that can also write data and improve the efficiency of writing work.

[Means for Solving the Problems] A data writing device for a writable ROM of the present invention has first and second writable ROMs connectable to each 8-bit microcomputer. 2
A RAM that stores data for writing each data terminal and each address of the IC socket into the first and second ROMs.
A CPU that is connected in parallel to each data terminal and each address terminal of the RAM and writes data read from this RAM to each ROM.
is provided, and when the 8-bit microcomputer is selected by the selection switch that selects whether to write to the ROM for an 8-bit microcomputer or the ROM for a 16-bit microcomputer, the first and first When a write inhibit signal is applied to the control terminal corresponding to the ROM write control terminal of one of the two IC sockets, and the selection switch selects the 16-bit microcomputer, the even/odd switching circuit applying a write inhibit signal to the control terminal of either one of the first and second IC sockets in response to an even number address signal of data read from the RAM; the other IC
A write inhibit signal is applied to the control terminal of the socket.

[Operation] A data writing device for a writable ROM configured as described above can be used as an R for an 8-bit microcomputer.
When writing data to the OM, if the selection switch is set to 8-bit microcomputer, a write inhibit signal is sent to the control terminal of either the first or second IC socket to which the ROM to be written is connected. Since the voltage is applied, data is written to only one ROM.

Also, two ROs for 16-bit microcomputer
When writing data to M, when the selection switch is set to 16-bit microcomputer, the even/odd number switching circuit selects data whose address signal is even number out of the data read from the RAM, for example, from the first ROM1. :
data with an odd address signal is stored in the second ROM.
written to.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a data writing device for a writable ROM according to an embodiment. In the figure, 4 is a CPU that reads data stored in the RAM and stores it in the writable ROM, and each address terminal A of this CPU 4 is
O-AN2 is connected to each address terminal A1 to AN1 of RAM6 via address bus 5, and also connects address terminals, data terminals, and control terminals of the first ROM and second ROM into which data is to be written. 1st and ff into which each terminal such as the O8 (chip select) terminal as an @ terminal is inserted.
112 (7) I CV, 7.8 (D@71'li
7'1m' Connected to one child A1 to AN.

Further, each data terminal Do-D7 of the CPIJ4 is connected to each data terminal DO-D7 of the RAM 6 via a data bus 9.
It is also connected to each data terminal Do to D7 of the first and second IC sockets 7.8.

The address terminal AO of the least significant digit of the CPU 4 is connected to the RAM 6.
It is connected to the least significant digit address terminal AO of the second IC socket 8 and the least significant digit address terminal AO of the second IC socket 8, and is also connected to the 1B and 2A input terminals of the signal switching IC unit 10. Further, the address terminals A1 of the CPU 4 and the RAM 6 are connected to the 18 input terminals of the signal switching tC unit 10. The output terminal 1Y of this signal switching IC unit is connected to the address terminal AO of the first IC socket 7, and the output terminal 2Y is connected to one input terminal of the first AND gate 11 of negative logic, and the inverter 12 through the negative logic second AND gate 13
is connected to one input terminal of the

Furthermore, the control input terminal G of the signal switching IC unit 10
is connected to a common terminal C of a selection switch 14 for selecting whether to write to a ROM for an 8-bit microcomputer or a ROM for a 16-bit microcomputer. One open terminal a of this selection switch 14 is grounded, and the other open terminal a is connected to a +5■ control power supply terminal.

Said signal switching IC unit (SN74LS157) 1
0, when the signal level of control input terminal G is L level, input terminals IA and 2A become output terminals 1Y and 2, respectively.
When the signal level of the control input terminal G becomes H level, each input terminal 1B and '2B becomes the output terminal I.
Connected to Y and 2Y.

The write permission signal C8 for each ROM from CP and U4 is input to the other input terminal of the first and second AND gates 11, 1'3, and each output terminal is connected to the first and second AND gates.
It is connected to the C8 terminal of each IC socket 7°8 of the ROM.

Note that the signal switching IC unit 10, the inverter 12, and the second AND gate 13 constitute a write inhibit circuit for the second ROM, and the signal switching IC unit 10, the first . Second AND gate 11.13 and inverter 1
2 constitutes an even/odd switching circuit.

In the data writing device for the writable ROM configured as described above, the R
When writing to the OM, a ROM into which data is to be written is inserted into the first IC socket 7. Then, the selection switch 14 is turned on to the +5V open terminal side. Then, as described above, the input terminal 1B of the signal switching unit 10 is connected to the output terminal 1Y, and the input terminal 2B is connected to the output terminal 2Y. Since the input terminal 2B is grounded, the output terminal 2B is connected via the inverter 12.
Since the signal level of one input terminal of the negative logic second AND gate 11 connected to the CPU 4 becomes H level, the output signal of the second AND gate 13 is equal to the write enable signal C8 from the CPU 4. It becomes H level regardless of the signal level. Therefore, since an H-level write inhibit signal is always applied to the σ terminal of the second socket 8, this second
Even if the second ROM is inserted into the IC socket 8 of the second ROM, data will not be written to the second ROM.

On the other hand, since one input terminal of the negative logic first AND gate 11 is always at L level, this first ? The signal level of the output terminal of the node gate 11, that is, the terminal of the first IC socket 7 into which the first ROM is inserted, is CP.
It changes in response to a change in the level of the write enable signal (■) from U4. Therefore, the first ROM inserted into the first IC socket 7 becomes ready for data writing by the CPU 4.

Thus, the CPU 4 sequentially reads data stored in each address area of the RAM 6 and writes it to each address area of the first ROM inserted into the first IC socket 7 via the address bus 5 and data bus 9. It's crowded.

Next, when writing data to a ROM for a 16-bit microcomputer, insert the first and second ROMs for two 8-bit microcomputers into the first and second IC sockets 7°8. Insert. Then, the selection switch 14 is turned on to the grounded open terminal a side. Then, as described above, the input terminal 1A of the signal switching IC unit 10 is connected to the output terminal 1Y, and the input terminal 2A is connected to the output terminal 2Y. As a result, if the address signal of the data read out by the CPU 4 and stored in the RAM 6 is an even number, the input terminal 2A becomes the L level.
The first ROM inserted into the second IC socket 7 becomes ready for writing, and if the address signal is an odd number, the input terminal 2A goes to H level. ROM 2 becomes writable.

Therefore, data read from the RAM 6 is divided and written into the first and second ROMs depending on whether the address signal is even or odd.

In this way, RO for 16-bit microcomputer
When writing data to M, the operator writes two ROMs for an 8-bit microcomputer into the first and second I
By simply inserting it into the C socket 7.8 and turning the selection switch 14 to the open terminal a side, the data stored in the RAM 6 is automatically sorted and written into each ROM according to even and odd addresses. Therefore, unlike the conventional device, R
There is no need to divide data into AM6 and store data for even addresses and odd addresses. Also, there is no need to perform the write operation twice. Therefore, the efficiency of writing into the ROM can be improved.

In addition, by operating the selection switch 14,
Data can be easily written to either RO or M of an 8-bit microcomputer ROM or a 16-bit microcomputer ROM.

Note that the present invention is not limited to the embodiments described above. In the embodiment, a signal switching IC unit 10 was used, but instead of this signal switching IC unit 10, as shown in FIG. 3, a relay 17 having two switching contacts 15 and 16 was used. Good too.

In this case, address signals AI and AO are input to the normally closed terminal and normally open terminal of contact 15, respectively, and the common terminal is connected to the first IC.
Connect to address terminal AO of socket 7. Further, the address signal AO is input to the normally closed terminal of the switching contact 16, the normally open terminal is grounded, and the common terminal is connected to one input terminal of the first AND gate 11. Further, one end of the drive coil 18 of this relay 17 is connected to a control power source 5), and the end of the coil is grounded through the collector-emitter of the switching transistor 19. And switching transistor 1
9 is connected to the common terminal of the selection switch 14.

Even with the data writing device configured in this way, the relay 17 can be changed by switching the selection switch 14.
Since this operates in the same manner as the signal switching IC unit 10 described above, the same effects as in the previously described embodiment can be obtained.

EFFECT OF THE INVENTION] As described above, according to the present invention, an even/odd number switching circuit is provided that determines whether the address signal of the data read from the RAM is even or odd. Therefore, it is possible to write to a ROM for an 8-bit microcomputer, and it is also possible to easily write to a ROM for a 16-bit microcomputer.
Data can also be written to the OM, and the efficiency of writing work can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data writing device for a writable ROM according to one embodiment of the present invention, and FIG. 2 shows a data writing device for a writable ROM according to another embodiment of the present invention. Block diagram, Figure 3 is a conventional writable RO
FIG. 2 is a block diagram showing a data writing device for M. 4...CPU, 5...Address bus, 6...RA
M. 7... First [C socket, 8... Second IC socket, 9... Data bus, 10... Signal switching IC
Unit, 11...1st AND gate, 12...
Inverter, 13...Second AND gate, 14...
・Selection switch, 15.16...Switching contact, 17...
・Relay 1.18... Drive coil, 19... Switching transistor. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] First and second IC sockets to which first and second writable ROMs for use in an 8-bit microcomputer can be connected, respectively, and respective data of the first and second IC sockets are connected to data terminals and address terminals. terminal and each address terminal are respectively connected in parallel, and the first
and a RAM that stores data to be written in a second ROM, a CPU that writes the data read from this RAM into each ROM, and an R for an 8-bit microcomputer.
a selection switch for selecting whether to write to OM or ROM for a 16-bit microcomputer, and one of the first and second IC sockets when an 8-bit microcomputer is selected with this selection switch. a write inhibit circuit that applies a write inhibit signal to a control terminal corresponding to the write control terminal of the ROM of the IC socket; and a write inhibit circuit that applies a write inhibit signal to a control terminal corresponding to the write control terminal of the ROM; in response to an even number address signal of the data.
an even/odd number switching circuit which applies a write inhibit signal to the control terminal of one of the IC sockets and applies a write inhibit signal to the control terminal of the other IC socket in response to an odd address signal; A data writing device for a writable ROM, comprising: