JPS6013311B2 - Semiconductor controlled rectifier - Google Patents
Semiconductor controlled rectifierInfo
- Publication number
- JPS6013311B2 JPS6013311B2 JP12752779A JP12752779A JPS6013311B2 JP S6013311 B2 JPS6013311 B2 JP S6013311B2 JP 12752779 A JP12752779 A JP 12752779A JP 12752779 A JP12752779 A JP 12752779A JP S6013311 B2 JPS6013311 B2 JP S6013311B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- base layer
- layer
- type base
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明は半導体制御整流装置、特にサイリス夕に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor controlled rectifiers, and more particularly to thyristors.
従釆、一般に周知のサィリスタの構造を第1図に示して
説明すると、同図において、1は比較的濃度の低いn−
導燈形のベース層、2は前記ベース層1の一方の面に設
けられたp+導電形のアノード層、3は前記ベース層の
他方の面に設けられたp導電形のベース層、4はこのp
導電形ベース層3上に選択的に設けられたn十導電形の
カソード層である。The structure of a generally known thyristor will be explained with reference to FIG. 1. In the figure, 1 is a relatively low concentration n
2 is a p+ conductivity type anode layer provided on one surface of the base layer 1; 3 is a p conductivity type base layer provided on the other surface of the base layer; 4 is a conductive light-type base layer; This p
This is a cathode layer of n+ conductivity type selectively provided on the conductivity type base layer 3.
そして、5はアノード層2にオーム性接触をなすアノー
ド電極、6はカソード層4にオーム性接触をなすカソー
ド電極、7はp導電形のベース層3にオーム性接触をな
すゲート電極である。このような構造を有するサィリス
タの動作の概要を説明する。Reference numeral 5 designates an anode electrode that makes ohmic contact with the anode layer 2, 6 a cathode electrode that makes ohmic contact with the cathode layer 4, and 7 a gate electrode that makes ohmic contact with the base layer 3 of the p conductivity type. An overview of the operation of a thyristor having such a structure will be explained.
主電流を通電するときにはカソード電極6に負バイアス
、アノード電極5に正バイアスを印加する。このときア
ノード層2とn導電形ベース層1の接合J,およびカソ
ード層4とp導電形ベース層3の間の接合J3は順方向
にバイアスされるが、n導電形ベース層1とp導電形ベ
ース層3の間の接合J2は逆方向バイアスになる。ゲー
ト電極7から正孔が注入され、カソード電極6からカソ
ード層4を経て電子がp導電形ベース層3に注入される
。注入された電子は接合J2を通ってn導軍形ベース層
1に集められる。このときアノード層2からn導電形ベ
ース層1に正孔が注入され、ベース層1を通ってp導電
形ベース層3に集められる。この正孔によって再びカソ
ード層4から接合J3を通って電子がp導電形ベース層
3に注入される。この過程を繰り返すことにより接合J
2の両側ベース層に正孔および電子が蓄積されることに
よって接合J2が逆バイアスから順バイアスに転換して
導適状態となる。この導適状態に移る過程をターンオン
と称し、その速さはゲート電極Tから注入された正孔が
カソード層4に入る速度、カソード層4からp導電形ベ
ース層3に注入された電子がn導電形ベース層1に伝達
する速さ、アノード層2からn導電形ベース層1に注入
された正孔がp導電形ベース層3に到達する速さなどに
よってさまる。また、逆バイアス電圧をカソード電極6
とアノード電極5の間に印加して鰭流を遮断した際に導
適状態から阻止状態に移る過程をターンオフと称し「
これは接合J2近傍に残留している正孔、電子が消失し
完全に順阻止状態を回復する速さでさまる。しかしなが
ら、上記した構造の従来のサィリス夕では、大電力の制
御能力はすぐれているが、その制御速度が小さく、高速
でかつ高耐圧のスイッチング装置が得うれなかった。When the main current is applied, a negative bias is applied to the cathode electrode 6 and a positive bias is applied to the anode electrode 5. At this time, the junction J between the anode layer 2 and the n-conductivity type base layer 1 and the junction J3 between the cathode layer 4 and the p-conductivity type base layer 3 are biased in the forward direction; The junction J2 between the shaped base layers 3 is reverse biased. Holes are injected from the gate electrode 7 , and electrons are injected from the cathode electrode 6 through the cathode layer 4 into the p-conductivity type base layer 3 . The injected electrons are collected in the n-type base layer 1 through the junction J2. At this time, holes are injected from the anode layer 2 into the n-conductivity type base layer 1, pass through the base layer 1, and are collected in the p-conductivity type base layer 3. These holes cause electrons to be injected from the cathode layer 4 into the p-conductivity type base layer 3 through the junction J3 again. By repeating this process, the joint J
By accumulating holes and electrons in the base layers on both sides of J2, the junction J2 changes from reverse bias to forward bias and becomes conductive. The process of transitioning to this conductive state is called turn-on, and its speed is determined by the speed at which holes injected from the gate electrode T enter the cathode layer 4, and the speed at which electrons injected from the cathode layer 4 into the p-conductivity type base layer 3 It depends on the speed of transmission to the conductivity type base layer 1, the speed at which holes injected from the anode layer 2 to the n conductivity type base layer 1 reach the p conductivity type base layer 3, etc. In addition, the reverse bias voltage is applied to the cathode electrode 6.
The process of changing from the conductive state to the blocking state when the fin flow is interrupted by applying between the anode electrode 5 and the anode electrode 5 is called turn-off.
This is limited to the speed at which the holes and electrons remaining in the vicinity of the junction J2 disappear and the forward blocking state is completely restored. However, although the conventional sirolith switch having the above-described structure has an excellent ability to control large electric power, its control speed is low, and a switching device with high speed and high withstand voltage cannot be obtained.
本発明はこのような点に鑑みでなされたもので「その目
的は制御速度を大きくするとともに高速動作に対するd
i/dtおよびdv/dtの耐量を大きくすることによ
り、高速でかつ高耐圧化を可能にした半導体制御整流装
置を提供することにある。The present invention was made in view of these points, and its purpose is to increase the control speed and increase the d for high-speed operation.
The object of the present invention is to provide a semiconductor-controlled rectifier that can operate at high speed and withstand high voltage by increasing the i/dt and dv/dt withstand capacities.
この目的を達成するために、本発明は、n導蚤形のベー
ス層と、このベース層の両面に設けられたp導電形のア
ノード層およびベース層と〜 このp導電形のベース層
上に設けられたn導電形のカソード層とからなる半導体
制御整流装置において、前記n導電形のベース層に前記
p導蟹形べ−ス層と隣接して所定のパターンで形成され
た該p導電形ベース層より高い不純物濃度を有するp導
電形のゲート領域を設け、かつ前記n導電形ベース層と
前記アノード層との間に該ベース層より高い不純物濃度
を有する高濃度ベース領域を設け「前記ゲート領域の相
互間隔を2aト前記p導電形ベース層の厚みおよび不純
物濃度をそれぞれW8およびNa、前記n導電形ベース
層の不純物濃度をNdとしたとき、Nd・a2<Na・
WB2 になるようにしたことを特徴としている。以下
、図面を用いて本発明の実施例を説明する。第2図は本
発明の一実施例を示すサィリスタの要部断面図であり、
第1図と同一又は相当部分は同一番号を用いてある。To achieve this object, the present invention comprises an n-conductivity type base layer, a p-conductivity type anode layer and a base layer provided on both sides of this base layer, and ~ on this p-conductivity type base layer. In a semiconductor controlled rectifier comprising an n-conductivity type cathode layer provided, the p-conductivity type base layer is formed in a predetermined pattern adjacent to the p-conductivity crab-shaped base layer. A p conductivity type gate region having a higher impurity concentration than the base layer is provided, and a high concentration base region having a higher impurity concentration than the base layer is provided between the n conductivity type base layer and the anode layer. When the mutual spacing between the regions is 2a, the thickness and impurity concentration of the p-conductivity type base layer are W8 and Na, and the impurity concentration of the n-conductivity type base layer is Nd, Nd・a2<Na・
It is characterized by being made to be WB2. Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a sectional view of a main part of a thyristor showing an embodiment of the present invention,
The same numbers are used for the same or corresponding parts as in FIG. 1.
ここで第1図のサィリスタ構造と異なる点は、n導電形
ベース層1上にp導電形ベース層3aと隣接して縦横に
細かいパターンで櫛の歯状またはメッシュ状に形成され
たp十導電形のゲート領域8を設け、かつn導電形ベー
ス層竃とp+導電形アノード層2との間にこのベース層
翼よりも高濃度の不純物を含むn十導電形のベース層領
域9を設けたことである。この場合、p導電形ベース層
3aは第1図におけるp導電形べ−ス層3よりも十分薄
く形成されており、その厚みは耐圧を同一に保つときは
従来構造のIJIの壁度に形成できる。そして「 p導
電形ベース層38の厚みWBは、ゲート領域8の相互間
隔2aとp導電形ベース層3aの不純物濃度Naしn導
電形ベース層富の不純物濃度Ndとの間において「Nd
。Here, the difference from the thyristor structure in FIG. 1 is that a p-conductor is formed on the n-conductor base layer 1 adjacent to the p-conductor base layer 3a in a comb-like or mesh shape in a fine pattern vertically and horizontally. A gate region 8 of the shape of a conductivity type is provided, and an n+ conductivity type base layer region 9 containing impurities at a higher concentration than the base layer wing is provided between the n conductivity type base layer layer and the p+ conductivity type anode layer 2. That's true. In this case, the p-conductivity type base layer 3a is formed sufficiently thinner than the p-conductivity type base layer 3 in FIG. can. The thickness WB of the p-conductivity type base layer 38 is defined as "Nd" between the mutual spacing 2a of the gate regions 8 and the impurity concentration Na of the p-conductivity type base layer 3a and the impurity concentration Nd of the n-conductivity type base layer 3a.
.
a2<Na。W82の関係を満足するように決められる
。a2<Na. It is determined to satisfy the relationship W82.
なお〜 p導電形ベース層3aの厚みはゲート領域8の
相互間隔、p導電形ベース層3aの低抗率および装置の
印加電圧などにより異なってくるが「従来構造の1〜1
′5の塁度まで形成できる。上記実施例の構造のサイリ
スタによると、ターンオン時にゲート電極?から注入さ
れた正孔は、D導電形べ−ス層3aを経てカソード層亀
内に注入されようとするがtゲ−ト領域8が高不純物濃
度で構成されかつ縦横に細かいパターンで櫛の歯状また
はメッシュ状に形成されているので、ゲ−ト領域8は低
抵抗となり、このゲート領域8を通じて素子全面にすば
やく伝達する。The thickness of the p-conductivity type base layer 3a varies depending on the mutual spacing of the gate regions 8, the low resistivity of the p-conductivity type base layer 3a, the applied voltage of the device, etc.
It can be formed up to a base depth of '5. According to the thyristor having the structure of the above embodiment, when it is turned on, the gate electrode? Holes injected from the T-gate region 8 try to be injected into the cathode layer through the D conductivity type base layer 3a. Since the gate region 8 is formed in a tooth-like or mesh-like shape, the resistance is low, and the resistance is quickly transmitted through the gate region 8 to the entire surface of the device.
このためカソード層4からの電子の注入が速く起こり「
かつ注入された電子は従来構造より薄いp導電形ベース
層3a中を遠く通過してn導電形ベース層1に到達する
ことになる。この結果トアノード層2からの正孔の注入
を遠くさせ、ターンオンに要する時間を従来の1′2〜
1′10まで低下させることができる。すなわち、第1
図に示すサィリスタ構造において「 サイリスタのター
ンオン時間はp導電形ベース層3の厚みWB,およびn
導電形ベース層1の厚みWB2 に依存し、このnおよ
びp導電形べ−ス層内の少数キャリア走行時間をとする
と、夕−ンオン時間(ton)は近似的にtonニゾし
・t2となる。Therefore, electron injection from the cathode layer 4 occurs quickly.
In addition, the injected electrons reach the n-conductivity type base layer 1 after passing far through the p-conductivity type base layer 3a, which is thinner than the conventional structure. As a result, the injection of holes from the toanode layer 2 is made farther away, and the turn-on time is increased from 1'2 to
It can be reduced to 1'10. That is, the first
In the thyristor structure shown in the figure, the turn-on time of the thyristor is determined by the thickness WB of the p-conductivity type base layer 3 and the n
Depending on the thickness WB2 of the conductivity type base layer 1, and assuming the minority carrier transit time in the n and p conductivity type base layers, the evening on time (ton) is approximately equal to tonnizo-t2. Become.
ただし「Dn、Dpは前記各ベース層内での少数キャリ
アの拡散定数である。したがって、前記ベース層が厚く
なるとターンオン時間は長くなり、また、p導電形ベー
ス層3の厚みがWB,が小さくなると、サイリスタの順
阻止電圧はそのベース層のパンチスルー‐電圧VpTに
よって制御される問題が起こる。これに対して、本発明
は、p導電形ベース層3a内に空乏層の延びを抑制する
ことによりその厚みW8,を4・さくし、かつn+導電
形のベース層領域9によりn導電形ベース領域1の厚み
WB2を4・さくしようとするものであり、第2図の実
施例構造では、p導電形ベース層3a内の空乏層の延び
が第1図の構造のものに比べて近似的に1ノムになる。
ただし岬xp(号)であり、ここ側まゲ−ト領域8の間
隔、Lはその深さである。However, Dn and Dp are minority carrier diffusion constants in each of the base layers. Therefore, the thicker the base layer, the longer the turn-on time, and the smaller the thickness of the p-conductivity type base layer 3, WB, is. Then, a problem arises in that the forward blocking voltage of the thyristor is controlled by the punch-through voltage VpT of its base layer.In contrast, the present invention has a method of suppressing the extension of the depletion layer in the p-conductivity type base layer 3a. Therefore, the thickness W8, of the base layer region 9 of the n+ conductivity type is reduced by 4.0 cm, and the thickness WB2 of the n conductivity type base region 1 is reduced by 4.0 cm. The extension of the depletion layer in the conductive base layer 3a is approximately 1 nom compared to the structure shown in FIG.
However, it is the cape xp (number), the distance between the gate areas 8 on this side, and L is the depth thereof.
それ故、p導電形ベース層3aの厚み(=WB,を1/
叫こすることができ、したがって、ターンオン時間は1
ノ叫こすることができる。たとえば裏:。‐7の時には
ターンオン時間は約1/甥茎度に短くなる。また、p導
鶴形ベース層3aの厚みWB,が一定であると考えると
、第2図の構造では第1図のものに比べて山倍の電圧を
印加することできるので「順阻止電圧を仏倍にできる。
一方、電流の遮断時にカソード電極6とアノード電極5
間には逆バイアス電圧が印加されるが、このとき接合J
,およびJ3には逆バイアスが印加されるのに対し、接
合J2は反転したままで順バイアスが印加されるので、
従来の構造では、前記接合J2近傍の過剰キャリャは再
結合による自然消滅をまたねばならず、ターンオフに要
する時間が長くかかっていた。Therefore, the thickness of the p-conductivity type base layer 3a (=WB, is 1/
can be screamed and therefore the turn-on time is 1
You can scream. For example, the back:. At -7, the turn-on time is reduced to about 1/degree. Furthermore, assuming that the thickness WB of the p-conductor crane-shaped base layer 3a is constant, the structure shown in Fig. 2 can apply a voltage twice as high as that of Fig. 1. It can be doubled.
On the other hand, when the current is cut off, the cathode electrode 6 and the anode electrode 5
A reverse bias voltage is applied between the junction J
, and J3 are reverse biased, whereas junction J2 remains inverted and forward biased, so
In the conventional structure, the excess carriers near the junction J2 had to disappear naturally by recombination, and it took a long time for turn-off.
本発明では、n導電形ベース層1とアノード層2との間
に設けられたn十導電形ベース層9によりァノード層2
から前記ベース層2への正孔の注入を制御しており「で
きる限り正孔の注入量を少なくして夕−ンオンする構造
をn+導電形ベース層9の厚みおよび不純物濃度を適当
に選ぶことによって可能とすることができる。このため
、ターンオフ時に消滅するキャリャが少なくてすむこと
になり「 ターンオフ速度を早くすることができる。次
にdiノdtおよびdv/dtの耐量を第3図および第
4図を参照して説明する。In the present invention, the anode layer 2 is formed by the n+ conductivity type base layer 9 provided between the n conductivity type base layer 1 and the anode layer 2.
The injection of holes into the base layer 2 is controlled by "appropriately selecting the thickness and impurity concentration of the n+ conductivity type base layer 9 so as to reduce the amount of holes injected as much as possible and turn on the structure in the evening." Therefore, fewer carriers disappear during turn-off, and the turn-off speed can be increased. This will be explained with reference to FIG.
ここで、第3図は第1図に示す従来のサィリスタに、第
4図は第2図に示す本発明のサィリス外こそれぞれ対応
する。従来のサィリスタ構造において、サィリスタがオ
フ状態からオン状態に移る場合には第3図に示すA部分
すなわちカソード(ェミッタともいう)層4の周辺部で
ゲ−電極7に近いところに電流が集中して流れ、時間の
経過とともに、電流の流れ面積がカソード層全面に速度
vsで広がる。一方、本発明の構造では第4図に示すB
部分すなわちp+導霧形ゲート領域8の周辺部に電流が
集中し、その面積が速度vsで広がる。そのため、本発
明では実効的なェミッタ周辺長が長くなり「dv/dt
耐量が改善される。また、上記vsはn導電形ベース層
1の厚みWB2に逆比例するので、本発明ではこのvs
が大きくなり、これもdi/dt耐量の改善に寄与する
ことになる。また、n導電形カソード(ェミツタ)層4
、p導電形ベース層3およびn導電形ベース層1からな
るn−p−nトランジスタの電流増幅率Qはサィリスタ
を流れる電流の密度に依存し、一般に電流密度の増加と
ともにQが大きくなる。Here, FIG. 3 corresponds to the conventional thyristor shown in FIG. 1, and FIG. 4 corresponds to the thyristor exterior of the present invention shown in FIG. 2. In the conventional thyristor structure, when the thyristor changes from the off state to the on state, current concentrates in the area A shown in FIG. As time passes, the current flow area spreads over the entire surface of the cathode layer at a speed vs. On the other hand, in the structure of the present invention, B shown in FIG.
The current is concentrated in the peripheral portion of the p+ atomized gate region 8, and its area expands at a speed vs. Therefore, in the present invention, the effective emitter peripheral length becomes longer and "dv/dt
Tolerance is improved. Further, since the above vs is inversely proportional to the thickness WB2 of the n-conductivity type base layer 1, in the present invention, this vs
becomes larger, which also contributes to improvement of di/dt tolerance. In addition, an n-conductivity type cathode (emitter) layer 4
, a p-conductivity type base layer 3 and an n-conductivity type base layer 1, the current amplification factor Q of the npn transistor depends on the density of the current flowing through the thyristor, and generally the Q increases as the current density increases.
このQの電流密度依存性を小さくすれば、dv/dt耐
量が改善される。p導電形ベース層3aの厚みWB,が
薄くなると、n−p−nトランジスタのベース輸送効率
はキャリャの拡散によって支配されるようになり、相対
的に電界によるドリフトの影響が少なくなる。したがっ
て、本発明の構造ではQの電流依存性が小さくなり〜d
v/dt耐量が改善されることになる。以上説明したよ
うに、本発明による半導体制御整流装置によれば、n導
霞形ベース層にp導電形ベース層を隣接して所定のパタ
ーンで形成されたp導電形のゲート領域を設けて該p導
電形ベース層内の空乏層の延びを抑制することによりそ
のベース層の厚みを小さくし、かつ前記ベース層とp導
電形アノード層との間に設けた該ベース層より高い不純
物濃度を有する高濃度ベース領域により前記n導電形ベ
ース層の厚みを小さくした構造としたので、前記ゲート
領域によってp導電形べ−ス層の厚みを十分薄くしてし
かも日頃方向耐圧を大きくすることができ、高速でかつ
高耐圧の半導体制御整流装置を提供することができると
いう効果がある。By reducing the current density dependence of Q, the dv/dt withstand capability is improved. When the thickness WB of the p-conductivity type base layer 3a becomes thinner, the base transport efficiency of the npn transistor comes to be dominated by carrier diffusion, and the influence of drift due to the electric field becomes relatively smaller. Therefore, in the structure of the present invention, the current dependence of Q becomes small ~d
The v/dt tolerance will be improved. As explained above, according to the semiconductor controlled rectifier according to the present invention, a p-conductivity type gate region formed in a predetermined pattern is provided adjacent to a p-conductivity type base layer on an n-conductivity hazy base layer. The thickness of the base layer is reduced by suppressing the extension of the depletion layer within the p-conductivity type base layer, and the base layer has a higher impurity concentration than the base layer provided between the base layer and the p-conductivity type anode layer. Since the structure is such that the thickness of the n-conductivity type base layer is reduced by the high concentration base region, the thickness of the p-conductivity type base layer can be sufficiently thinned by the gate region, and the breakdown voltage in the normal direction can be increased. This has the advantage that it is possible to provide a high-speed, high-voltage semiconductor-controlled rectifier.
第1図は従来のサィリスタを示す要部断面図、第2図は
本発明の一実施例を示すサィリスタ要部断面図、第3図
および第4図はそれぞれ従釆と本発明とのdi/dLd
v/dtの耐量の説明に供する説明図である。
1…・・・n‐導電形ベース層「 2・・…・p+導電
形アノード層、3,3a・・・・・・p導電形ベース層
、4……n+導電形カソード層、5……アノード電極、
6・・・・・・カソード電極、7・・・・・・ゲート電
極、8・・・・・・p+導電形のゲート領域、9・・…
,げ導電形のべ−ス領域。
第1図
第2図
第3図
第4図FIG. 1 is a sectional view of the main part of a conventional thyristor, FIG. 2 is a sectional view of the main part of a thyristor showing an embodiment of the present invention, and FIGS. dLd
FIG. 2 is an explanatory diagram for explaining v/dt tolerance. 1...n-conductivity type base layer 2...p+ conductivity type anode layer, 3, 3a...p conductivity type base layer, 4...n+ conductivity type cathode layer, 5... anode electrode,
6...Cathode electrode, 7...Gate electrode, 8...P+ conductivity type gate region, 9...
, base area of conductive type. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
られたp導電形のアノード層およびベース層と、このp
導電形のベース層上に設けられたn導電形のカソード層
とからなる半導体制御整流装置において、前記n導電形
のベース層に前記p導電形のベース層と隣接して所定の
パターンで形成された該p導電形ベース層より高い不純
物濃度を有するp導電形ゲート領域を設け、かつ前記n
導電形ベース層と前記アノード層との間に該ベース層よ
り高い不純物濃度を有する高濃度ベース領域を設け、前
記ゲート領域の相互間隔を2a、前記p導電形ベース層
の厚みおよび不純物濃度をそれぞれW_BおよびNa、
前記導電形ベース層の不純物濃度をNdとしたとき、N
d・a^2<Na・W_B^2 になるようにしたことを特徴とする半導体制御整流装置
。[Claims] 1 A base layer of n conductivity type, an anode layer and a base layer of p conductivity type provided on both sides of this base layer, and this p conductivity type base layer.
In a semiconductor controlled rectifier comprising a cathode layer of n conductivity type provided on a base layer of conductivity type, the base layer of n conductivity type is formed in a predetermined pattern adjacent to the base layer of p conductivity type. a p-conductivity type gate region having a higher impurity concentration than the p-conductivity type base layer;
A high concentration base region having an impurity concentration higher than that of the base layer is provided between the conductivity type base layer and the anode layer, the mutual spacing of the gate regions is 2a, and the thickness and impurity concentration of the p conductivity type base layer are respectively W_B and Na,
When the impurity concentration of the conductivity type base layer is Nd, N
A semiconductor-controlled rectifier device characterized in that d・a^2<Na・W_B^2.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12752779A JPS6013311B2 (en) | 1979-10-01 | 1979-10-01 | Semiconductor controlled rectifier |
CA000361937A CA1159158A (en) | 1979-10-01 | 1980-10-01 | Semiconductor controlled rectifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12752779A JPS6013311B2 (en) | 1979-10-01 | 1979-10-01 | Semiconductor controlled rectifier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5650565A JPS5650565A (en) | 1981-05-07 |
JPS6013311B2 true JPS6013311B2 (en) | 1985-04-06 |
Family
ID=14962213
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12752779A Expired JPS6013311B2 (en) | 1979-10-01 | 1979-10-01 | Semiconductor controlled rectifier |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS6013311B2 (en) |
CA (1) | CA1159158A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IE53895B1 (en) * | 1981-11-23 | 1989-04-12 | Gen Electric | Semiconductor device having rapid removal of majority carriers from an active base region thereof at device turn-off and method of fabricating this device |
JPS60142559A (en) * | 1983-12-29 | 1985-07-27 | Fujitsu Ltd | Programmable read only memory |
GB8901342D0 (en) * | 1989-01-21 | 1989-03-15 | Lucas Ind Plc | Semiconductor device |
US7638816B2 (en) | 2007-08-28 | 2009-12-29 | Littelfuse, Inc. | Epitaxial surge protection device |
-
1979
- 1979-10-01 JP JP12752779A patent/JPS6013311B2/en not_active Expired
-
1980
- 1980-10-01 CA CA000361937A patent/CA1159158A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
CA1159158A (en) | 1983-12-20 |
JPS5650565A (en) | 1981-05-07 |
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