JPS5931050A - Resistor and forming process thereof - Google Patents

Resistor and forming process thereof

Info

Publication number
JPS5931050A
JPS5931050A JP14095482A JP14095482A JPS5931050A JP S5931050 A JPS5931050 A JP S5931050A JP 14095482 A JP14095482 A JP 14095482A JP 14095482 A JP14095482 A JP 14095482A JP S5931050 A JPS5931050 A JP S5931050A
Authority
JP
Japan
Prior art keywords
resistor
film
insulating film
forming
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14095482A
Other languages
Japanese (ja)
Inventor
Masayasu Miyake
三宅 雅保
「よし」沢 正浩
Masahiro Yoshizawa
Michiyuki Harada
宙幸 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14095482A priority Critical patent/JPS5931050A/en
Publication of JPS5931050A publication Critical patent/JPS5931050A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To form a resistor with excellent controllability and reproducibility by a method wherein a resistance controller is composed of an insulating film such as an ion implanted silicon oxide film or silicon nitride film, etc. CONSTITUTION:The arsenic dope polycrystalline silicon layers 3, 3' are deposited as an electrode of high resistor to form an opposing electrode on SiO2 film 2 by means of photoetching. A molybdenum layer 4 is deposited on the polycrystalline silicon layers 3, 3' and the SiO2 film 2. The molybdenum layer 4 on the SiO2 layer 2 between the polycrystalline silicon layers 3, 3' is removed by means of photoetching. An ion implanted layer 5 is formed on the surface of the SiO2 film 2 between said polycrystalline silicon layers 3, 3'. Finally the boron ion is implanted to remove the molybdenum layer 4.

Description

【発明の詳細な説明】 不発明は半導体乗積回路に用いられる尚抵抗体およびそ
の形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resistor used in a semiconductor multiplication circuit and a method for forming the resistor.

東&(ロ)路にあ−いて必嶽とされる抵抗体、特に10
’− 10”Ω程度の高抵抗体は、従来、CvD法等で
堆積したノンドープ多結晶シリコンにイオン注入法によ
シ、砒素、りん、硼素等の不純物を導入し、該多結晶シ
リコンの抵抗値を制御したもの音用いていた。し、がし
、この抵抗体は、次に述べるように、抵抗値の制御性、
再現性が悪く、特に広く心安とされる10’Ω相度以上
の尚抵抗を得る場合には大きな問題でめった。
Resistance elements that are required on the East & (Ro) roads, especially 10
A high resistance material of about 10"Ω has conventionally been produced by introducing impurities such as arsenic, phosphorus, boron, etc. into non-doped polycrystalline silicon deposited by CvD method or the like using an ion implantation method to increase the resistance of the polycrystalline silicon. This resistor has the ability to control the resistance value, as described below.
The reproducibility was poor, and serious problems were encountered especially when obtaining a resistance of 10'Ω phase or higher, which is widely considered safe.

第1図はシリコン酸化膜上に、CVD法で堆積した膜厚
4500大のノンドープ多結晶シリコン層に砒素k 1
50 keVの注入エネルギでイオン注入し、窒素雰囲
気で1000℃、 30分の熱処理を行った後の多結晶
シリコン層のシート抵抗のイオン注入量依存性全示すも
のである。、このように高抵抗領域では、抵抗値のイオ
ン注入量依存性、すなわち、不純物濃度依存性か非常に
強く、わずかの不純物量の変化に対しても抵抗値は大さ
く質化するので制御が困難である。さらに、多結晶シリ
コン中での不純物の拡散係数は非常に大きく、例えはイ
オン注入した砒素、りん、鎖糸等は1000℃、30分
程度の熱処理で拡散のために、膜厚方向に均一に分布す
る。このため、イオン注入量の制御性は、通常1%以内
であるが、多結晶シリコン膜厚が5%程度ばらつくので
、不純物濃度としては、5X以上ばらつく□ことになる
。従って、第1図かられかるように、シート抵抗として
は(資)%以上もはらっき、tIil制御性。
Figure 1 shows arsenic k 1 in a non-doped polycrystalline silicon layer with a thickness of 4500 nm deposited by CVD on a silicon oxide film.
This figure shows the complete dependence of the sheet resistance of the polycrystalline silicon layer on the ion implantation amount after ion implantation with an implantation energy of 50 keV and heat treatment at 1000° C. for 30 minutes in a nitrogen atmosphere. In this high-resistance region, the dependence of the resistance value on the ion implantation amount, that is, the dependence on the impurity concentration, is very strong, and even a small change in the amount of impurity can significantly change the resistance value, making it difficult to control. Have difficulty. Furthermore, the diffusion coefficient of impurities in polycrystalline silicon is extremely large; for example, ion-implanted arsenic, phosphorus, chain threads, etc. can be diffused uniformly in the film thickness direction by heat treatment at 1000°C for about 30 minutes. to be distributed. Therefore, the controllability of the ion implantation amount is usually within 1%, but since the polycrystalline silicon film thickness varies by about 5%, the impurity concentration varies by more than 5X. Therefore, as can be seen from Fig. 1, the sheet resistance is less than 1%, and the tIil controllability is low.

再現性の面で大きな問題であった。lた、尚抵抗体から
の電極取出しのために高抵抗体の両端は尚濃度に不純物
を導入することによシ低抵抗にする必袈がある。この低
抵抗層から高抵抗体部分への不純物の横方向拡散長は、
例えは1000℃、30分程度の熱処理で2〜3μmに
もなり、微細高密度集株回路製造上大きな問題でめった
This was a major problem in terms of reproducibility. Furthermore, in order to take out the electrodes from the resistor, both ends of the high-resistance element must be made low in resistance by introducing impurities in a high concentration. The lateral diffusion length of the impurity from this low resistance layer to the high resistance part is:
For example, heat treatment at 1000° C. for about 30 minutes results in a thickness of 2 to 3 μm, which is a major problem in the production of fine, high-density integrated circuits.

本発明は、従来用いられている多結晶シリコン高抵抗体
の以上のような問題点km決するために提案されたもの
で、多結晶シリコンを用いず、シリコン酸化膜等の絶縁
膜六回あるいは内部に、イオン注入によυ開側1性、再
埃性に優れた微細な高抵抗体をうること全目的とするも
のである。
The present invention was proposed to solve the above-mentioned problems of conventionally used polycrystalline silicon high-resistance elements. Another object of the present invention is to obtain, by ion implantation, a fine high-resistance material having excellent open-side uniformity and dust resistance.

(3) 前記の目的を達成するため、本発明は電極および抵抗値
制御部より成る抵抗体に2いて、イオン打込みをしたシ
リコン酸化膜あるいはシリコン窒化膜等の絶縁膜により
該抵抗値制御部を構成したこと全特徴とする抵抗体ケ発
明の要旨とするものである。
(3) In order to achieve the above object, the present invention provides a resistor consisting of an electrode and a resistance value control part, and the resistance value control part is formed by an insulating film such as an ion-implanted silicon oxide film or silicon nitride film. The gist of the invention is the resistor body having all the features of the structure.

さらに本発明はシリコン酸化膜おるいはシリコン窒化膜
等の絶縁膜上に電極を設ける工程と、該絶縁膜にイオン
注入することにより抵抗値制御部を形成する工程より成
ることを特徴とする抵抗体形成方法を発明の要旨とする
ものである。
Furthermore, the present invention provides a resistor characterized by comprising a step of providing an electrode on an insulating film such as a silicon oxide film or a silicon nitride film, and a step of forming a resistance value control portion by implanting ions into the insulating film. The gist of the invention is a method for forming a body.

次に本発明の実施例ケ添附図面について欣明する。なお
実施例は一つの例示であって、本発明の棺神を逸脱しな
い範囲内で、種々の震央あるいは改良音材いうることは
目91でもない。
Next, we will explain about the embodiments of the present invention and the attached drawings. It should be noted that the embodiments are merely illustrative, and that various epicenters or improved sound materials may be used without departing from the spirit of the present invention.

第2図は不発明による篩抵抗体形成の一実施例であって
、図に2いて、lはシリコン基板、2はシリコン酸化膜
(SiO+) 、3は不純物添加低抵抗多結晶シリコン
、4はモリブテン、5はイオン注入層でおる。第2図(
a)に示すよりにシ(4) リコン基板1上に、高抵抗体として用いるst O2膜
2を熱酸化おるいはCVD法等で形成する。
FIG. 2 shows an example of forming a sieve resistor according to the invention. Molybdenum 5 is an ion-implanted layer. Figure 2 (
As shown in a), (4) an stO2 film 2 to be used as a high resistance material is formed on a silicon substrate 1 by thermal oxidation or CVD.

この実施例ではウェット02雰囲気での熱酸化法を用い
、膜厚は5000^とした。次に、第2図(b)に示す
ように高抵抗体の電極として、砒素ドープ多結晶シリコ
ン’kcVD法等で堆積し、通常のフォトエツチングに
よp、3.3’よ構成る対向電極k St Ot Z上
に形成する。この実施例では、多結晶シリコンの膜厚は
3000λとした。次に、第2図<C)に示すように多
結晶シリコン3,3′およびSi 0.2上に、次に行
うイオン注入のマスクとして用いるためのモリブテン4
を真空蒸着法等で堆積する。このモリブテンの膜厚は次
に行うイオン注入のイオン棟、注人エネルギ、注入量を
考慮して十分イオン全阻止できる膜厚を選ぷ必費がおる
。この実施例ではモリブテン4の膜厚は5000 Aと
した。次に、堆積したモリブデンの内、対向電極3,3
′の間のSf Oalにあるモリブデンを、通常の7オ
トエツテングにょシ除去する。しかる後に、全面にイオ
ン注入全行い、対向電極3,3′の間にあるSt 02
の表面に畠抵抗体の抵抗値制御部であるイオン注入層5
を形成する。イオン神は硼素、りん、砒素、シリコン。
In this example, a thermal oxidation method in a wet 02 atmosphere was used, and the film thickness was set to 5000^. Next, as shown in FIG. 2(b), arsenic-doped polycrystalline silicon is deposited by a kcVD method as an electrode of a high resistance material, and a counter electrode of p, 3.3' is formed by normal photoetching. Formed on k St Ot Z. In this example, the film thickness of polycrystalline silicon was 3000λ. Next, as shown in FIG. 2 <C), molybdenum 4 is placed on the polycrystalline silicon 3, 3' and Si 0.2 to be used as a mask for the next ion implantation.
is deposited by vacuum evaporation method or the like. It is necessary to select a film thickness of this molybdenum that can sufficiently block all ions, taking into account the ion ridge, implanter energy, and implantation amount for the next ion implantation. In this example, the film thickness of molybdenum 4 was 5000A. Next, among the deposited molybdenum, counter electrodes 3, 3
The molybdenum present in the Sf Oal between 1 and 2 is removed by the usual 7 steps. After that, all ions are implanted into the entire surface, and St 02 between the opposing electrodes 3 and 3' is
On the surface of the ion implantation layer 5 which is the resistance value control part of the Hatake resistor.
form. The ion gods are boron, phosphorus, arsenic, and silicon.

アルコン寺の内の1糊類あるいは2桓類以上の組み合わ
せでもよい。ぼた、注入エネルキ、注入童は目的とする
尚抵抗体の抵抗値に応じて定める。この実施例では硼素
イオンy、50KeVの注入エネルギでイオン注入した
。次(・C1イオン注入時のマスクと(7で用いたモリ
ブデン4を、例えは、硫酸と過酸化水素の混合液を用い
て除去すれは第2図(d)に示すように、電極3 、3
”e2端子とする高抵抗体が形成できる。
It may be one type of archon or a combination of two or more types. The power, injection energy, and injection force are determined according to the resistance value of the intended resistor. In this example, boron ions were implanted with an implantation energy of 50 KeV. Next, as shown in FIG. 2(d), the molybdenum 4 used in (7) is removed using the mask used for C1 ion implantation, for example, using a mixture of sulfuric acid and hydrogen peroxide. 3
``A high-resistance element can be formed as an e2 terminal.

第3図は、以上のようにして形成した尚抵抗体のシート
抵抗の注入量依存性を示すものである。第3図は硼素i
 50 KeVの注入エネルギでイオン注入したときの
ものでめる。ここに示すように、杷miで必る5lOt
flaが、1016〜IQ Iフti”以上の渦磯度イ
オン注入により、電気伝導性を持つようになることがわ
かる。ここに示す例では4 X 1010l6’ 〜2
 X 101?crn−2の注入量の範囲で、10″Ω
/ロ〜107Ω/口のシート抵抗値を実現している。1
07Ω/ロ程度以」二の高抵抗ヶ得る場合に、本発明に
よる抵抗体を用いれは、第1図と第3図を比較すると明
らかなように、本発明による抵抗体は従来の抵抗体に比
べると、格段に抵抗値の注入量依存性が小さい、すなわ
ち抵抗値の制御性、沓現性がよいという利点がるる。ま
た、本発明による抵抗体ではイオン注入法によシ、51
02膜の表面に近い部分のみ音導電層化しでいるので5
102膜厚のばらつきは抵抗値に影響企及はさず、開側
1性、再現性に優れている。さらに本発明によれは、従
来の多結晶シリコンを用いた場合のような横拡が9がな
いので、微細化でさる等の利点がある。
FIG. 3 shows the dependence of the sheet resistance of the resistor formed as described above on the implantation amount. Figure 3 shows boron i
The ions were implanted with an implantation energy of 50 KeV. As shown here, 5lOt required for loquat
It can be seen that fla becomes electrically conductive by ion implantation with a vorticity of 1016 to IQ Ifti'' or higher.In the example shown here, 4 x 1010l6' to 2
X 101? 10″Ω for a range of crn-2 injection volumes.
A sheet resistance value of 107 ohms/low has been achieved. 1
When obtaining a high resistance of about 0.07Ω/Ω or more, the resistor according to the present invention can be used.As is clear from a comparison of FIG. 1 and FIG. In comparison, it has the advantage that the dependence of the resistance value on the injection amount is much smaller, that is, the resistance value is better controllable and easier to develop. Further, in the resistor according to the present invention, the ion implantation method is used.
02 Because only the part near the surface of the membrane is made into a sound conductive layer, 5
Variations in the 102 film thickness do not affect the resistance value, and it has excellent open side uniformity and reproducibility. Further, according to the present invention, since there is no lateral expansion unlike in the case of using conventional polycrystalline silicon, there are advantages such as miniaturization.

以上は5102膜にイオン注入4行う場合を述べたが、
シリコン窒化膜あるいはアルミナ、サファイヤ等の絶縁
膜にイオン注入を行っても同様の効果が期待される。ま
た、電極は対向電極の場合を述べたが、例えは 同心円
状の電極音用いてもよいことはいう丑でもない。
The above describes the case of performing 4 ion implantations into the 5102 film, but
A similar effect is expected when ions are implanted into a silicon nitride film or an insulating film such as alumina or sapphire. Furthermore, although we have described the case where the electrodes are opposite electrodes, it goes without saying that concentric electrodes may also be used.

(7) また、この実施例では電極全般りた後、S10□膜にイ
オン注入する場合を述べたか、先にイオン注入時行い、
その後電極を設りても、同様の効果が期待されるもので
ある。
(7) In addition, in this example, after the electrodes have been completely removed, ions are implanted into the S10□ film.
Similar effects can be expected even if electrodes are provided afterwards.

第4図は本発明の他の実施例であって、高エネルギでイ
オン注入することによp1埋め込み型の抵抗体を形成し
たものである。第4図(a)。
FIG. 4 shows another embodiment of the present invention, in which a p1 buried type resistor is formed by high-energy ion implantation. Figure 4(a).

(b)に示すように、シリコン基板1上に形成した5i
OJ2上に、イオン注入のマスクとして用いるモリブデ
ン4を第1の実施例と同様な方法で形成し、次に、5I
O2膜中に例えばホウ素のイオン注入を行う。ここで、
ホウ素の注入エネルギを例えB 150 KeVと尚エ
ネルギにすると、5i02膜の表面ではなく 、810
2膜中に導電層5が形成される。次に、第4図(C)に
示すようeこ、イオン注入のマスクとして用いたモリブ
テンを除去した後、電極取出しかでさる深さまで、51
02験2にスルーホール6を通常の7オトエツテングに
よυ開ける。次に、第4図(d)に示すように、スルー
ホール上に金Nf4あるいは低抵抗多結晶シリ(8) コン叫の電極7を形成することにより、導電層がsto
、st中にある抵抗体を形成することができる。この実
施例においても、第1の実施例の場合と同様の効果がる
り、抵抗値の制御性、杓現性のよい微細な抵抗体の形成
を可能にするものでおる。
As shown in (b), 5i formed on the silicon substrate 1
Molybdenum 4, which is used as an ion implantation mask, is formed on OJ2 in the same manner as in the first embodiment, and then 5I
For example, boron ions are implanted into the O2 film. here,
For example, if the boron implantation energy is B 150 KeV, the surface of the 5i02 film is not 810
A conductive layer 5 is formed in the two films. Next, as shown in FIG. 4(C), after removing the molybdenum used as a mask for ion implantation,
02 Experiment 2: Open the through hole 6 using the normal 7-tightening process. Next, as shown in FIG. 4(d), by forming an electrode 7 of gold Nf4 or low resistance polycrystalline silicon (8) on the through hole, the conductive layer becomes stoichiometric.
, st. In this embodiment as well, the same effects as in the first embodiment can be obtained, and it is possible to form a fine resistor with good resistance value controllability and ladleability.

第5図は本発明の他の実施例であって、抵抗体の′11
1極および導電層とも埋め込み型の場合でおる。第5図
(a)に示すように、シリコン基板上に形成したSiO
,1llk2上に、低抵抗多結晶シリコン:(’、3’
より成る′fIL極を設け、次KCVD法等によk) 
Sin、験8を堆積する。この実施例においてはSi 
O,膜8の膜厚は5000 Aとした。第5図(b>に
示すようにモリブテン4をマスクとして、電極3,3′
間の5i02膜8および2中に、辿択的にホウ素を例え
は、200Ke■の注入エネルギでイオン注入する。2
00 KeVのホウ素の8102中での侵入深さはSi
 02膜8の膜厚でおる5000^よすも大きいので、
第5図中)に示すように5in2膜82よび2にまたか
つて導電層5を形成することができる。次に、第5図(
C)に示すように、イオン注入のマスクとして用いたモ
リブテンを除去すれは、電極3,3′寂よひ導電層5よ
り成る抵抗体全形成することかでさる。乗積回路製造に
L=いては多結晶シリコン3 、3”i配線として用い
れは、配?tM3−3′間にFir望の抵抗値を持つ抵
抗体を接続した集積回路を製造できる。この実施?りに
よる抵抗体形成力法は、第1の実施例で述べたのと同様
に、抵抗値の制御性、41it性に潰れた微細な抵抗体
形成を可能にするものである。
FIG. 5 shows another embodiment of the present invention, in which a resistor '11
Both the single pole and the conductive layer are of the buried type. As shown in FIG. 5(a), SiO formed on a silicon substrate
, 1llk2, low resistance polycrystalline silicon: (', 3'
A 'fIL pole consisting of
Sin, test 8 is deposited. In this example, Si
The thickness of the film 8 was 5000A. As shown in Fig. 5 (b), using molybdenum 4 as a mask, electrodes 3, 3'
Boron ions are selectively implanted into the 5i02 films 8 and 2 between them, for example, at an implantation energy of 200 Ke. 2
The penetration depth of boron in 8102 at 00 KeV is
The thickness of 02 film 8 is 5000 yos, so
As shown in FIG. 5), a conductive layer 5 can also be formed on the 5in2 films 82 and 2. Next, see Figure 5 (
As shown in C), the molybdenum used as a mask for ion implantation can be removed by forming the entire resistor consisting of the electrodes 3, 3' and the conductive layer 5. If L = 3,3'' is used as the i wiring in multiplication circuit manufacturing, it is possible to manufacture an integrated circuit in which a resistor having a desired resistance value is connected between the wirings tM3 and 3'. The resistor forming force method using the method enables the controllability of the resistance value and the formation of a fine resistor with a 41-it property, as described in the first embodiment.

第6図は本発明の他の実施例であって、縦方向に抵抗体
全形成する場合でおる。第6図(a、lに示すように、
シリコン基板上の5IU21iL 2上に、抵抗体の一
ト部軍極となる、低抵抗多結晶シリコン等3盆、CVD
法等により増株し、δらに、その上に、Cvl)法寺に
よりSto、膜8を堆積する。
FIG. 6 shows another embodiment of the present invention, in which the resistor is entirely formed in the vertical direction. Figure 6 (as shown in a, l)
On the 5IU21iL 2 silicon substrate, 3 trays of low-resistance polycrystalline silicon, etc., which will become the poles of the resistor, and CVD
The stock is multiplied by a method, etc., and a film 8 is deposited thereon by Cvl) method.

この実施例ではsi 02膜8の膜厚は500Aとした
。な逅・、この5j02膜は、1都′亀惟として多結晶
シリコン基板いた場合には、該多結晶シリコンの一部を
熱酸化することにより得ることもできる。次に、第6図
(b)に丁すように、モリブデン4をマスクとして選択
的に5tO21i!1%8にイオン注入し、導電層5を
形成する。このときの注入エネルギは、5fOJi! 
8の深さ方向にわたって、全て導電層化されるように選
ぶ必要がある。この実施例ではAsイオンを80 Ke
Vで注入した。注入量は得ようとする抵抗値に応じて決
定する。
In this example, the thickness of the Si02 film 8 was 500A. Alternatively, if a polycrystalline silicon substrate is used, this 5J02 film can also be obtained by thermally oxidizing a part of the polycrystalline silicon. Next, as shown in FIG. 6(b), using molybdenum 4 as a mask, 5tO21i! Ions are implanted to 1% 8 to form a conductive layer 5. The implantation energy at this time is 5fOJi!
It is necessary to select a conductive layer so that the conductive layer is formed entirely over the depth direction of 8. In this example, the As ion is 80 Ke
Injected at V. The injection amount is determined depending on the resistance value to be obtained.

次に、第6図<a>に示すように、モリブデンを除去し
た後、導電JWi 5上にM等の金属を熱情して上部電
極7を形成すれは、3,7を電極とする縦型構造の抵抗
体を形成することができる。
Next, as shown in FIG. 6 <a>, after removing the molybdenum, a metal such as M is applied on the conductive JWi 5 to form an upper electrode 7. A resistor of a structure can be formed.

この実施例による方法は、これ1で述べてきた実施例と
同様に、副側1性、杓現性に優れた、微細な抵抗体の形
成′?cβJ能にする。特に、この実施例によれば、縦
型構造の抵抗体を形成できるので、より微細な抵抗体の
形成′に可能にするものである。
Similar to the embodiment described in Section 1, the method according to this embodiment is used to form a fine resistor with excellent secondary uniformity and spreadability. cβJ function. In particular, according to this embodiment, since a resistor having a vertical structure can be formed, it is possible to form a finer resistor.

以上説明したように、本発明によれは抵抗体は絶縁膜へ
のイオン注入を用いて形成している(11) ので、特に107Ω/1]程度以上の高抵抗値を制御性
、再現性よく実現でき、絶縁膜厚のばらつきの抵抗値へ
の影響もなく、さらに不純物の拡散による横波がりもな
いため、微細化ができる等の利点かあり、烏密度来槓回
路の製造全司能にするものである。
As explained above, according to the present invention, the resistor is formed using ion implantation into the insulating film (11), so that high resistance values of about 107Ω/1 or higher can be achieved with good controllability and reproducibility. It has the advantage of being able to be miniaturized because there is no effect on the resistance value due to variations in insulation film thickness, and there is no transverse wave caused by diffusion of impurities. It is something.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の多結晶シリコンを用いて形成した抵抗体
のシート抵抗のイオン注入量依存性をボす図、第2図(
a)〜(d)は本発明による抵抗体形成の一実施例を示
す図、第3図は本発明により形成した抵抗体のシート抵
抗のイオン注入量依存性を示す図、第4図(a) 〜(
d) 、第5図(a) 〜(C) 。 第6図(a)〜(e)は夫々本発明による抵抗体形成の
他の実施例ケ示す。 1・・・・・・シリコン基板、2・・・・・・シリコン
酸化膜(熱酸化aa)、3,3′・・・・・・低抵抗多
結晶シリコン、4・・・・・・モリブテン、5・・・・
・・イオン注入層、6・・・・・・スルーホール、7・
・・・・・金属あるいは低抵抗多結晶シリコン、8・・
・・・・シリコン酸化膜(C(12) VD酸化険) 特許出願人 日本電侶寛帖公社 第1図 5モ大量(cm−2) 第3図 シエ入量 (C酢り 第2図 第4図
Figure 1 shows the ion implantation dose dependence of the sheet resistance of a resistor formed using conventional polycrystalline silicon, and Figure 2 (
a) to (d) are diagrams showing an example of forming a resistor according to the present invention, FIG. ) ~(
d), Figures 5(a) to (C). 6(a) to 6(e) respectively show other embodiments of forming a resistor according to the present invention. 1...Silicon substrate, 2...Silicon oxide film (thermal oxidation aa), 3,3'...Low resistance polycrystalline silicon, 4...Molybdenum , 5...
...Ion implantation layer, 6...Through hole, 7.
...Metal or low resistance polycrystalline silicon, 8...
・・・・Silicon oxide film (C(12) VD oxide film) Patent applicant Nippon Denso Kancho Corporation Figure 1 5Mo amount (cm-2) Figure 3 Silicone amount (C vinegar Figure 2 Figure 4

Claims (5)

【特許請求の範囲】[Claims] (1)電極および抵抗値制御部より成る抵抗体に2いて
、イオン打込み會したシリコン酸化膜めるいはシリコン
窒化膜等の絶縁膜により該抵抗値制御部會構成したこと
を特徴とする抵抗体。
(1) A resistor comprising an electrode and a resistance control section, and the resistance control section is formed of an ion-implanted insulating film such as a silicon oxide film or a silicon nitride film. .
(2)シリコン酸化膜あるいはシリコン窒化膜等の絶縁
膜上に電極全般ける工程と、該絶縁膜にイオン注入する
ことにより抵抗値制御部全形成する工程より成ることe
%徴とする抵抗体形成方法。
(2) It consists of a step of placing all the electrodes on an insulating film such as a silicon oxide film or a silicon nitride film, and a step of forming the entire resistance value control part by implanting ions into the insulating film.
Method of forming a resistor with % characteristics.
(3)シリコン酸化膜あるいはシリコン窒化膜等の絶縁
膜にイオン注入することにより抵抗値制御部を形成する
工程と、該絶縁膜に電極取出し用の穴を開り′る工程と
、該電極取出し用の穴および該絶縁膜上に電極を設ける
工程より成ること?特徴とする%肝請求の範囲第2項記
載の抵抗体形成力法。
(3) A step of forming a resistance value control section by implanting ions into an insulating film such as a silicon oxide film or a silicon nitride film, a step of making a hole for taking out an electrode in the insulating film, and a step of making a hole for taking out the electrode. The method consists of a step of providing a hole for the purpose and an electrode on the insulating film? The resistor forming force method according to claim 2, characterized by % liver.
(4)シリコン酸化膜あるいはシリコン窒化膜等の第一
の絶縁膜上に電極を形成する工程と、前記の電極及び第
一の絶縁膜上に第二の絶縁@葡形戟する工程と、前記の
第二の絶祿膜紮通過して第一の絶縁膜中にイオンを注入
することにより抵抗値制御Sを形成する工程とよりなる
ことを特徴とする請求 形成方法。
(4) a step of forming an electrode on a first insulating film such as a silicon oxide film or a silicon nitride film; a step of forming a second insulating film on the electrode and the first insulating film; A method for forming a claim comprising the step of forming a resistance value control S by passing through a second insulating film and implanting ions into the first insulating film.
(5)抵抗体の1都電極を設ける工程と、該下部電極上
にシリコン酸化[6るいはシリコン窒化膜等の絶縁膜を
設ける工程と、咳絶縁膜にイオン注入することにより抵
抗値制御部を形成する工程と、該抵抗値制御部上に上部
電極を設ける工程より成ることr%徴とする特許請求の
範囲第2狽配載の抵抗体形成方法。
(5) A step of providing one electrode of the resistor, a step of providing an insulating film such as a silicon oxide film or a silicon nitride film on the lower electrode, and a resistance value control section by implanting ions into the insulating film. A method for forming a resistor according to claim 2, comprising a step of forming a resistor and a step of providing an upper electrode on the resistance value control portion.
JP14095482A 1982-08-16 1982-08-16 Resistor and forming process thereof Pending JPS5931050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14095482A JPS5931050A (en) 1982-08-16 1982-08-16 Resistor and forming process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14095482A JPS5931050A (en) 1982-08-16 1982-08-16 Resistor and forming process thereof

Publications (1)

Publication Number Publication Date
JPS5931050A true JPS5931050A (en) 1984-02-18

Family

ID=15280674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14095482A Pending JPS5931050A (en) 1982-08-16 1982-08-16 Resistor and forming process thereof

Country Status (1)

Country Link
JP (1) JPS5931050A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61120462A (en) * 1984-11-16 1986-06-07 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JPS6323328A (en) * 1985-12-02 1988-01-30 Texas Instr Japan Ltd Silicon oxide film and formation thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61120462A (en) * 1984-11-16 1986-06-07 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JPS6323328A (en) * 1985-12-02 1988-01-30 Texas Instr Japan Ltd Silicon oxide film and formation thereof

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