JPS5926689Y2 - Binary discrimination device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binary discrimination device for converting analog signals corresponding to two colors such as black and white of a transmitted document into digital signals of 1 and 0 in a facsimile transmission device or the like.

In facsimile transmission devices, etc., devices that convert black, which has a low level among whites, and white, which has a high level among blacks, into digital signals of 1 and 0 among analog signals corresponding to black and white on the screen have conventionally been used. There are many more ways to think about it.

For example, an example is shown in Japanese Patent Publication No. 49-33202. According to this, the analog signal is Schmitted in a plurality of Schmitt circuits, and the output waveform of one Schmitt circuit is used as a reference, and the output waveform of the other Schmitt circuits is used as a reference. Mark and space portions of a certain width or less are detected in the output waveform of the Schmitt circuit, and these waveforms and the reference output waveform of the Schmitt circuit are combined and converted into a digital signal of 1 and 0.

However, this type of device has the following drawbacks.

In other words, when there is high-level white in black, if the length of the first half of the black is less than the above-mentioned certain width, the white will be collapsed and become black in the above-mentioned synthesized waveform. It is.

An object of the present invention is to provide a binary discriminating device for black and white, etc., which eliminates the above-mentioned drawbacks.

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram of a device according to the present invention, and FIG. 2 is a waveform diagram of the circuit diagram of FIG. 1.

First, the image signal A obtained by scanning the transmission document by the reading device of the facsimile transmitting device is transmitted to the image signal input terminal 1.
is input to one input terminal of comparators 3 and 4.

In addition, a voltage at a certain level is supplied to the power supply terminal 2, and the voltage is dropped by the resistor 13 and the variable resistor 14. When comparing the voltage applied to other input terminals, a>b is always
The variable resistors 14 and 15 are adjusted so that the relationship is as follows.

The comparator 3 sets the output signal port to 1 only when the voltage level of the image signal A is higher than the comparison voltage a.

Similarly, the comparator 4 sets the output signal C to 1 only when the voltage level of the image signal A is higher than the comparison voltage S.

The output signals 3 and 4 from the comparators 3 and 4 are operated on by an exclusive OR circuit (hereinafter referred to as FOR) 5 to output a signal 2.

The output signal 2 consists of a resistor 6 and a capacitor 7
It is delayed by the R time constant circuit and inverted by the inverter 8 to obtain the signal E.

Note that the delay of signal 2 in this CR time constant circuit is caused by a JK flip-flop (hereinafter referred to as JKFF), which will be described later.
This is to ensure the switching of the output of 11.

This signal E is input to the clock terminal of JKFFII.

In addition, the J and 2 terminals of JKFFll have power supply terminal 1.
Since a voltage is always input from 0, the output signal is switched by the signal H input to the clock terminal.

Further, the output signal of the comparator 3 is inverted by the inverter 9 and inputted to the preset terminal (PR8) of the JKFFII.

Similarly, the output signal C of the comparator 4 is input to the clear terminal (CLR) of JKFFII.

The output signal of JKFFll is normally switched by the signal H input to the clock terminal, but when the output signal port from the comparator 3 is l, the output signal is kept in the 1 state by the signal port. be done.

Further, when the output signal C from the comparator 4 is 0, the output signal is held in the O state by this signal.

Therefore, the output signal would normally be switched to the output signal in complete synchronization with the signal input to the clock terminal.
For example, when the output signal port from comparator 3 becomes 1, if the output signal is O, it switches to 1, and the output signal becomes 1.
In the case of , the state of 1 is maintained as it is, and the state is switched to the state of O at the next falling edge of the signal E.

Similarly, when the output signal from the comparator 4 becomes 0, if the output signal is 1, it switches to 0, and if the output signal is O, it remains at 0, and the signal It switches to the state of 1 at the next falling edge of E.

The output signal thus obtained is a digital signal capable of faithfully reproducing the input image signal A, and is output from the output terminal 12.

Here, the purpose of delaying signal E by the above-mentioned CR time constant circuit will be briefly explained.

As mentioned above, the output signal of JKFFll is connected to the comparator 3.
Alternatively, it is switched by the output signal from the comparator 4 or the output signal C.

It can also be switched by the signal H input to the clock terminal.

Therefore, in order to clarify which signal is controlling the output signal, the CR time constant circuit delays signal E by a certain period of time, and when switching to the output signal of JKFF 11 is performed, the above-mentioned Switching is always performed by one of the three signals, ie, signal E, signal port, and signal.

As described above, according to the present invention, the drawbacks of conventional black-and-white binary discriminating devices, such as the inability to reproduce narrow whites in black, can be overcome with a simple device, and input image signals can be faithfully reproduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of the circuit diagram shown in FIG. 1... Image signal input terminal, 3, 4... Comparator, 5... Exclusive OR circuit, 6...
・Resistance, 7... Capacitor, 8.9...
・Inverter, 11...JK flip-flop.

Claims (2)

[Scope of utility model registration request] (1) two comparators that respectively compare the analog image signal and the voltage level with comparison voltages of two different levels;
an exclusive OR circuit that receives the output of the comparator as input and performs an exclusive OR operation; a delay circuit that delays the output of the exclusive OR circuit; 1. A binary discrimination device comprising: a flip-flop circuit whose state can be switched by at least one of the signals. (2) When the output of the comparator with the higher comparison voltage among the two comparators is 1, the output of the flip-flop circuit is always 1, and the output of the comparator with the lower comparison voltage among the two comparators is 2. The binary discrimination device according to claim 1, wherein the output of the flip-flop circuit is always O when the output of the flip-flop circuit is O.