JP2675079B2 - Binarization processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binarization processing circuit suitable for application to the case where an image signal is binarized, such as a facsimile machine.

BACKGROUND OF THE INVENTION In a facsimile apparatus, image information of a conveyed document is optically read and converted into an electric signal (image signal), and the photoelectrically changed image signal is
For example, signal processing means for converting into binary information of black and white is adopted.

A black and white binary image signal that has undergone such signal processing is transmitted to the other party using a line.

By the way, since the density of the image information of the original to be read varies, there is a considerable difference in the density level. If the density difference of the character part is large with respect to the background level,
When converted into a monochrome binary signal based on the image signal, it can be converted into a monochrome binary signal suitable for the input image information.

However, in the usual case, there are many documents in which there is not much difference in density level. Therefore, if the input image signal is simply binarized, it may not be possible to obtain a monochrome binary signal that matches the input image information. Many.

Therefore, in such a facsimile machine,
By using the binarization processing circuit as shown in FIG. 3, the binarization processing is performed on the basis of the resulting edge-enhanced image signal.

Based on the edge-enhanced image signal, 2
If converted into a value signal, even if the density level difference of the input image information is small, it can be converted into a binary signal suitable for the input image information.

Now, FIG. 3 is an example of the above-mentioned conventional binarization processing circuit 1, in which an image signal S is supplied to a terminal 2 and this is an inverting input of a comparator 3 which is composed of a black and white binary operational amplifier. Supplied to the terminal.

Further, a predetermined reference voltage is applied to the terminal 4, and the image signal S and this reference voltage are divided by the resistors 5 and 6, and are composed of the resistors 5 and 6 and the capacitor 7. It is supplied to the integrating circuit 8 to form a predetermined reference signal REF.

Reference signal formed on the basis of such an image signal S
REF is supplied to the non-inverting input terminal of the comparator 3, and the terminal 2
The binarization of the image signal S supplied to is executed. Therefore, a binary output corresponding to a monochrome image is obtained at the terminal 9.

The level of the reference signal REF differs depending on the magnitude of the time constant of the integrating circuit 8. FIG. 4A is a waveform diagram showing the relationship between the image signal S and the reference signal REF when the time constant of the integrating circuit 8 is increased. Similarly, the relationship between the image signal S and the reference signal REF when the time constant of the integrating circuit 8 is small is shown in FIG. 4C.

As a result, a binarized output as shown in FIG.

[Problems to be Solved by the Invention] By the way, when the binarization processing circuit 1 as shown in FIG. 3 is used, the level of the reference signal REF is blunt with respect to the image signal S. When compared, each edge portion of the image signal S is equivalent to the emphasized state. That is, if the reference signal REF thus modulated according to the image signal is used, it is equivalent to comparison with the input image signal with edge enhancement.

Now, as shown in FIG. 4, especially as image information,
When image information such as a checkered pattern or a vertical stripe pattern is entered, the waveform of the binarized signal output changes greatly depending on the magnitude of the integration time constant.

Especially, when the integration time constant is increased, it looks like a checkerboard pattern.
For image information with low MTF, signal collapse occurs,
It has a drawback that the binarization processing according to the image information cannot be reliably performed (FIG. 4B).

Further, if the integration time constant is made too small, there is a drawback that a binary output that is faithful to the image cannot be obtained, such as being output as a white signal even when it should be processed as a black portion (FIG. 2). D).

In view of this, the present invention proposes a binarization processing circuit capable of faithfully performing binarization conversion processing according to input image information.

[Means for Solving the Problems] In order to solve the above-mentioned problems, in the present invention, an edge detection unit that outputs a control signal indicating detection of a rising edge, detection of a falling edge, and non-detection of an edge, and an edge Based on the control signal from the detection means, one of the change pixels when a rising edge is detected or when a falling edge is detected is set as a black pixel and the other is output as a white pixel. Based on the control signal from the means, the non-changed pixel when the edge is not detected is output as a black pixel or a white pixel based on the comparison result of the signal level of the non-changed pixel and the binarization threshold value. And means.

[Operation] The image signal S is the edge signal EG in the differentiating circuit 12.
(FIG. 2D) is formed.

The image signal S is further supplied to the signal generating means 1B.
This signal generating means 1B includes first and second comparators 17, 18
And multiplexer 16. Further, a binarizing means 1C for binarizing the non-changed pixel of the pixels and selecting the binarized pixel based on the edge detection information is provided.

The binarizing means 1C includes a third comparator 19 and a multiplexer.
It consists of 16.

The multiplexer 16 is supplied with a control signal CTL (FIG. 2E) corresponding to the edge output formed based on the edge detection signal EG. The control signal CTL is a signal corresponding to a rising edge, a falling edge, and an intermediate level between them.

In addition to the image signal Sd, the first comparator 17 is supplied with the image signal Sd and the first reference signal Sa formed by the clamp potential, whereby a white level signal is always formed. (Fig. 2C).

Similarly, in addition to the image signal Sd, the second comparator 18 is supplied with the second reference signal Sc formed on the basis of the image signal Sd and the shading signal, and the second comparator 18 outputs the second reference signal Sc. , A black signal is always formed (FIG. 2C).

As the reference signal Sb of the third comparator 19, a signal formed on the basis of the clamp potential and the shading waveform is supplied. As a result, the third comparator 19 outputs a monochrome binary value corresponding to the image signal Sd. Signal is formed. These white, black, and monochrome binary signals are selected based on the edge detection information.

That is, when the edge signal EG has a rising edge, the comparison output of the first comparator 17 is selected,
At the falling edge, the second comparison output is selected, and at other times, the third comparison output is selected.

By doing so, in the case of a pixel that changes from white to black, a black pixel is output, in a change pixel that changes from black to white, a white pixel is output, and in a non-change pixel, a binary signal is output. When the image signal Sd as shown in FIG. 2C is input, a binarized output signal as shown in FIG. 2G is obtained.

As a result, a binary output signal corresponding to the edge can be formed regardless of the value of the image information level.

[Example] Next, a case where an example of the binarization processing circuit according to the present invention is applied to the signal processing system of the above-mentioned facsimile apparatus will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a connection diagram showing an example of the binarization processing circuit 1 according to the present invention. The binarization processing circuit 1 detects the rising edge, the falling edge, and the edge of the image signal S. Based on the control signal from the edge detection means that outputs a control signal indicating detection, one of the change pixels when a rising edge is detected or when a falling edge is detected is defined as a black pixel and the other Based on the control signal from the edge detecting means and the signal generating means for outputting as a white pixel, the non-changed pixel whose edge is not detected is based on the comparison result between the signal level of this non-changed pixel and the binarization threshold value. It is composed of binarizing means for outputting as black pixels or white pixels.

Here, the edge detection means is differentiating circuit 12 and A / D converter 1
Composed of three. The signal generating means is composed of at least the first and second comparators 17 and 18 and the multiplexer 16, and the binarizing means is the third comparator 19 and the multiplexer.
It consists of 16.

A specific example of the binarization processing circuit 1 will be described in more detail.

First, the image signal S supplied to the terminal 2 is transferred to the capacitor 10
After the DC component is cut off by the DC signal, it is supplied to the sampling and holding circuit 11, and the image signal as shown in FIG.
Made with Sd. This image signal Sd is supplied to the CR differentiating circuit 12 to form an edge signal EG corresponding to the image signal Sd (FIG. 2D).

The edge signal EG is supplied to the A / D converter 13, and, for example,
A / D conversion processing is performed in which the rising edge is output “2”, the falling edge is output “0”, and the intermediate level is “1”. The A / D conversion output is used as a control signal CTL for the multiplexer 16 described later (FIG. 2E).

Here, as the reference signal for A / D conversion supplied to the A / D converter 13, the clamp potential applied to the terminals 14 and 15,
Since the signal formed based on the shading signal is used, accurate edge information can be obtained without being affected by shading distortion or the like.

The image signal Sd is further supplied to the first to third comparators 17 to 19. Describing from the first comparator 17, the divided voltage output of the image signal Sd and the clamp potential supplied to the terminal 14 is used as the reference signal Sa for the first comparator 17.

Therefore, the image signal Sd that has passed through the amplifier 21 is divided by the clamp potential and the resistors 22 and 23, and the first comparator 1
Supplied to 7 non-inverting input terminals.

Therefore, the reference signal Sa has a constantly high level in relation to the image signal Sd and is always obtained as a high-level comparison output. Therefore, the first comparison output is an output corresponding to the white signal.

The image signal Sd is further supplied to the inverting input terminal of the second comparator 18, and the divided output of the image signal Sd and the shading signal supplied to the terminal 15 is the second reference signal.
It is supplied to the non-inverting input terminal as Sc.

Thus, the second reference signal Sc is a voltage-divided output of the image signal Sd and the shading signal. Therefore, as is apparent from FIG. 2C, the second reference signal Sc is the image signal Sd.
Input is always at a lower level.

As a result, the second comparator 18 can obtain the second comparison output corresponding to the black level.

In addition, 25 is an amplifier and 26 and 27 are resistors for voltage division. Three
0 is an analog switch that is normally used in the off state.

The image signal Sd is further supplied to the non-inverting input terminal of the third comparator 19, and the inverting input terminal thereof is supplied with the third reference signal Sb formed based on the clamp potential and the shading signal. .

The third reference signal Sb has a level as shown in FIG. 2C, and the comparator 19 outputs a third value of "1" or "0" binary corresponding to the level of the image signal Sd. A comparison output is obtained.

 Reference numeral 24 is a voltage dividing resistor.

The above-described first to third comparison outputs are respectively supplied to the multiplexer 16, and any one of the comparison outputs is selectively output in the multiplexer 16 based on the control signal CTL related to the edge detection information. The timing to select is the clock pulse CLK supplied to it (see Fig. 2A).
It is performed in synchronization with.

In the embodiment, the first comparison output is selected at the rising edge of the edge signal EG, the second comparison output is selected at the falling edge, and the third comparison output is selected at other times. Is configured as follows.

As a result, when the image signal Sd as shown in FIG. 2C is input, the control signal CTL becomes as shown in FIG. E, and the output selected by this is as shown in G in FIG. Become. The respective reference signals at that time are shown in FIG.
This means that the reference signal shown in is selected.

In this way, when the pixel changes from white to black, the comparison output corresponding to the black pixel is output, and when the pixel changes from black to white, the comparison output corresponding to the white pixel is output. Further, the non-change pixels are binarized by another binarization threshold value (equivalent to the third reference signal Sb).

Therefore, when the color changes from white to black, the black level is always "0", and when the color changes from black to white, the white level is "1". Therefore, the input image signal Sd is fine as in the interval of α in FIG. Even in a checkered pattern or a vertical stripe pattern, a monochrome binary output signal corresponding to the image information can be obtained.

Further, as shown by the section of β in FIG. 2, even in a section in which the gray level of the input image information varies, this section β is output from the third comparator 19 as a comparison output “white”. Since "1" is obtained, the white output is always selected in this section.

As a result, even if there is a slight change in the image information, it can be converted into predetermined binarized information without following it.

[Effects of the Invention] As described above, according to the present invention, when a pixel changes from white to black according to the edge detection information of an image signal, a black pixel is output and a change pixel changing from black to white. In the range, the pixel is configured to be output as a white pixel, and in the section of the non-changed pixel, binarization is performed based on another binarization reference signal.

As a result, like checkered patterns and vertical stripes,
An image signal associated with fine image information can be converted into a monochrome binary signal corresponding to the image information, and the image quality can be greatly improved.

Therefore, the binarization processing circuit according to the present invention is extremely suitable when applied to the signal processing system of the above-mentioned facsimile apparatus.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing an example of a binarization processing circuit according to the present invention, FIG. 2 is a waveform diagram used to explain its operation, and FIG. 3 is a connection diagram showing an example of a conventional binarization processing circuit. FIG. 4 is a waveform diagram for explaining the operation. 1 ... Binarization processing circuit 12 ... Differentiation circuit 13 ... A / D converter 16 ... Multiplexer 17-19 ... First to third comparators Sa-Sc ... Reference signal Sd ... Image signal

Claims (1)

(57) [Claims] 1. A rising edge is detected based on a control signal from the edge detecting means, which outputs a control signal indicating detection of a rising edge of the image signal, detection of a falling edge and detection of no edge. Signal is generated when one of the change pixels when a falling edge is detected or when a falling edge is detected is output as a black pixel and the other is output as a white pixel, and an edge is not detected based on a control signal from the edge detection means. The non-changing pixel at a certain time has a binarizing means for outputting as a black pixel or a white pixel based on the comparison result of the signal level of the non-changing pixel and the binarization threshold Processing circuit.