JPS5856464A - Manufacture of mos semiconductor device - Google Patents

Manufacture of mos semiconductor device

Info

Publication number
JPS5856464A
JPS5856464A JP15518081A JP15518081A JPS5856464A JP S5856464 A JPS5856464 A JP S5856464A JP 15518081 A JP15518081 A JP 15518081A JP 15518081 A JP15518081 A JP 15518081A JP S5856464 A JPS5856464 A JP S5856464A
Authority
JP
Japan
Prior art keywords
gate
semiconductor substrate
impurity
region
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15518081A
Other languages
Japanese (ja)
Inventor
Osamu Nishikuro
西黒 修
Kiichi Futai
二井 喜一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15518081A priority Critical patent/JPS5856464A/en
Publication of JPS5856464A publication Critical patent/JPS5856464A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To obtain a semiconductor element having excellent element characteristics by holding a gate forming region in the state that an impurity of the prescribed density of the same conductive type as a semiconductor substrate is injected. CONSTITUTION:An oxidized film 5 is newly formed by a heat treatment on the surface of a semiconductor substrate 1, windows 8a, 9a are opened at the portions corresponding to regions to be formed with its source 8 and its drain 9, an impurity of reverse conductive type as a semiconductor substrate 1 is introduced, thereby forming a high density source region 8a and a high density drain region 9a. Then, a new oxidized film is formed on a semiconductor substrate 1, a polycrystalline silicon layer is formed thereon, and is patterned as prescribed, thereby forming a gate electrode 6. Further, with the electrode 6 as a mask an oxidized film 5 is selectively etched to allow a gate oxidized film 7 to remain directly under the mask. With the electrode 6 as a mask the reverse conductive type impurity to the substrate 1 is injected, thereby forming the source 8 and the drain 9 to obtain a semiconductor device 10.

Description

【発明の詳細な説明】 本発明は、MOg型半導体装置の製造方法(=関する。[Detailed description of the invention] The present invention relates to a method for manufacturing an MOg type semiconductor device.

一般に電解効果トランジスタからなるMOa型半導体装
置は、1チツプ内に保護ダイオードが設けられている。
Generally, an MOa type semiconductor device consisting of a field effect transistor is provided with a protection diode within one chip.

このためこの保護ダイオードを形成する際(:、MOg
型牛型体導体素子成予定領域が不純物C二よって汚染さ
れ謳い、而して、高周波用のMOa型半導体装置では、
高周波帯域で損失の少ない低出力移置4;するために通
常基板抵抗が数十オームの半導体基板が使用されておシ
、その不純物濃度は低濃産に設定されている。しかしな
がら、前述の保護ダイオードの形成工程やMO8型半導
体素子を構成するソース、ドレインの形成工程の酸化処
理や不純物処理の際1:、半導体基板と反対#電型の不
純物が半導体基板のゲート形成予定領域に外部拡散によ
って導入される。(第1図参照)この不純物の導入深さ
は、通常数ミクロンに達し、ゲート酸化膜の形成後にイ
オン注入法等によって半導体基数内(=これを打消すた
め(二不純物を注入しても表面近傍の不純物11に匿し
か制御できず、所定の集子特性を有するMO8型半導体
装置が得られない欠点があった。
Therefore, when forming this protection diode (:, MOg
The region where the conductor element is to be formed is contaminated with impurity C2, and therefore, in the MOa type semiconductor device for high frequency use,
In order to achieve low power transfer with little loss in a high frequency band (4), a semiconductor substrate with a substrate resistance of several tens of ohms is normally used, and its impurity concentration is set to be low. However, during the oxidation treatment and impurity treatment in the above-mentioned protective diode formation process and the source/drain formation process of the MO8 type semiconductor element, impurities of the opposite #electronic type to the semiconductor substrate may be used to form the gate of the semiconductor substrate. introduced into the region by external diffusion. (See Figure 1) The depth of introduction of this impurity usually reaches several microns, and after the formation of the gate oxide film, ion implantation, etc. This has the disadvantage that it is only possible to control the impurities 11 in the vicinity and that it is not possible to obtain an MO8 type semiconductor device having predetermined collector characteristics.

本発明は、かかる点に鑑みてなされたもので、ゲート形
成予定領域を半導体基板と同一4′4を型の所定濃度の
不純物が導入された状態(二保持して、優れた素子特性
を有する半導体菓子を容易に形成することができるMO
a型半導体装置の製造方法を見出したものである。
The present invention has been made in view of the above points, and has excellent device characteristics by keeping the region where the gate is to be formed identical to the semiconductor substrate and having a predetermined concentration of impurities introduced therein. MO that can easily form semiconductor confectionery
A method for manufacturing an A-type semiconductor device has been discovered.

以下、本発明の実施例について説明する。Examples of the present invention will be described below.

第2図(At(二示す如く、所定導電型の半導体基板1
の表面に酸化Ml!!2を形成する0次いで、この酸化
Ps2のゲート形成予定領域3に対応する領域を周知の
与真蝕刻法にて開口する1次いで、開口部31が形成さ
れた酸化膜2をマスク5二してゲート形成予定領域3(
二、半導体基板1と同じ導電型の不純物を導入して所定
濃度の不純物領域4を形成する。
FIG. 2 (At(2) As shown in FIG.
Oxidized Ml on the surface of! ! Next, a region of the oxidized Ps2 corresponding to the gate formation region 3 is opened using a well-known etching method. Gate formation area 3 (
2. An impurity of the same conductivity type as the semiconductor substrate 1 is introduced to form an impurity region 4 of a predetermined concentration.

ここで、ゲート形成予定領域3に導入する不純物濃度は
%第3図の曲線(I)で示す如く。
Here, the impurity concentration introduced into the gate formation region 3 is as shown by curve (I) in % of FIG.

後述するソース8.ドレイン9の形成工程尋の後の熱処
理の除C二外部拡散6二よってソース8、ドレイン9等
からゲート形成予定領域3に導入される半導体基板1と
は反対導電型の不純物の濃If(同図中、曲線(I[)
で図示)よシも高濃度(:設定し、この不純物領域4の
拡散深さは曲1(U)で示す外部拡散(二よる不純物の
導入深さよりも深く設定しておく。
Source 8, which will be described later. After the step of forming the drain 9, the heat treatment removes C2 and externally diffuses the source 8, drain 9, etc. into the region 3 where the gate is to be formed. In the figure, the curve (I[)
The diffusion depth of this impurity region 4 is set to be deeper than the depth of introduction of the impurity in external diffusion (2) shown in curve 1 (U).

次に、同図IBIに示す如く、熱処理(;よ)半導体基
板1の表面に新しく酸化膜5を形成する。
Next, as shown in IBI of the figure, a new oxide film 5 is formed on the surface of the heat-treated semiconductor substrate 1.

次いで、同図101に示す如く、酸化膜5のソース8、
ドレイン9の形成予定領域に対応する部分に、写真蝕刻
法により窓8m、9mを開口し、半導体基板1と反対導
電型の不純物を導入して高濃度ソース8m、高濃度ドレ
イン9mの領域を形成する。
Next, as shown in FIG. 101, the source 8 of the oxide film 5,
Windows 8m and 9m are opened by photolithography in a portion corresponding to the region where the drain 9 is to be formed, and impurities of the opposite conductivity type to the semiconductor substrate 1 are introduced to form regions of a high concentration source 8m and a high concentration drain 9m. do.

次に、半導体基板1上4=新しい酸化膜を形成してこの
酸化膜上1ニゲート電極6を形成するための多結晶シリ
コン層を形成し、この多結晶シリコン層に所定のパター
ンニングを施してゲート電極6とする。
Next, a new oxide film is formed on the semiconductor substrate 1, and a polycrystalline silicon layer for forming the gate electrode 6 is formed on this oxide film, and this polycrystalline silicon layer is subjected to predetermined patterning. This is referred to as gate electrode 6.

次に、このゲート電極6をマスクシニしてその直下にゲ
ート酸化Byが残存するように酸化膜5を選択的にエツ
チングする。然る後、同図()に示す如く、ゲー)m&
6をマスク(二手導体基板1と反対導電型の不純物を尋
人してソース8、ドレイン9を形成し、半導体装置10
を得る。
Next, the gate electrode 6 is masked and the oxide film 5 is selectively etched so that the gate oxide By remains directly below it. After that, as shown in the same figure (), game) m&
6 as a mask (conducting impurities of the opposite conductivity type to the two-handed conductor substrate 1 to form a source 8 and a drain 9, and forming a semiconductor device 10).
get.

このよう(=シて製造された半導体装置10は、予めゲ
ート形成予定領域3(二手導体基板1と同じ導電型の不
純物が所定の拡散深さで導入されているので、ソース8
、ドレイン9の形成後の熱処理の、際(=、特(=高濃
度ソースsb、高?1度ドレイン9bから外部拡散によ
ってゲート形成予定領域3(二導入される半導体基板1
と反対導′磁型の不純物を補償してゲート領域を所定の
不純物濃度C二保持することができる。
In the semiconductor device 10 manufactured in this way, impurities of the same conductivity type as the gate formation region 3 (the second conductor substrate 1) are introduced in advance at a predetermined diffusion depth, so that the source 8
During the heat treatment after forming the drain 9, the semiconductor substrate 1 is introduced into the gate formation region 3 (2) by external diffusion from the drain 9b.
It is possible to maintain a predetermined impurity concentration C2 in the gate region by compensating for impurities of opposite magnetic type.

その結果、高周波帯域で使用しても損失の少ない所謂低
出力容量のMOa型半型半導体金子ることができ、極め
て優れた素子特性を有する半導体装置10を実現するこ
とができる。
As a result, a so-called low output capacitance MOa type half-type semiconductor metal piece with little loss even when used in a high frequency band can be obtained, and a semiconductor device 10 having extremely excellent device characteristics can be realized.

尚、実施例では、ソース8、ドレイン9の外部拡散を防
止する場合について説明したが、この他にも半導体基板
1(二形成する保護ダイオードからの外部拡散(=よっ
てゲート形成予定領域3か汚染される場合にも本発明方
法を適用できることは勿論であり、この場合には、保護
ダイオードの形成工程紡(=ゲート形成予定領域3(二
上述の不純物領域4を形成しておけば良い。
In the embodiment, a case has been explained in which external diffusion of the source 8 and drain 9 is prevented. Of course, the method of the present invention can also be applied to the case where the protective diode formation process (= gate formation area 3 (2) and the above-mentioned impurity area 4 may be formed.

以上説明した如く1本発明C:係るMOa型半導体装置
の製造方法によれば、ゲート形成予定領域を半導体基板
と同一導電型の所定濃度の不純物が導入された状態に保
持したので、優れた素子特性を有する半導体素子を容易
(=形成できる等顧著な効果を有するものである。
As explained above, 1. Invention C: According to the method for manufacturing an MOa type semiconductor device, the region where the gate is to be formed is maintained in a state where impurities of a predetermined concentration of the same conductivity type as the semiconductor substrate are introduced, resulting in an excellent device. It has remarkable effects such as being able to easily form a semiconductor element having specific characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の方法で製造されたMOB型半導体装置
のゲート領域の不純物濃度と基板の深さ方向との関係を
示す説明図、第2図(4)乃至同図IDIは、本発明の
実施例を工程Jll C二示す説明図、第3図は1本発
明方法C二て製造されたMOa型半導体装置のゲート領
域の不純物濃度と基板の深さ方向との関係を示す説明図
である。 1・・・半導体基板、2,6・・・酸化膜、3・・・ゲ
ート形成予定領域、Ja・・・開口部、4・・・不純−
動領域、6・・・ゲート′lIL極、7・・・ゲート酸
化膜、8・・・ン−7,,Jb・・・高濃度ソース、9
・・・トレイン、9b・・・高#度ドレイン、10・・
・MO8型半導体装置。 出願人代理人 弁理士 鈴 江 武 彦第1Fl!J 第3図
FIG. 1 is an explanatory diagram showing the relationship between the impurity concentration in the gate region of a MOB type semiconductor device manufactured by a conventional method and the depth direction of the substrate. FIG. 3 is an explanatory diagram showing the relationship between the impurity concentration of the gate region of the MOa type semiconductor device manufactured by the method C2 of the present invention and the depth direction of the substrate. be. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2, 6... Oxide film, 3... Gate formation area, Ja... Opening, 4... Impurity -
Dynamic region, 6... Gate 'lIL pole, 7... Gate oxide film, 8... N-7,, Jb... High concentration source, 9
...Train, 9b...High degree drain, 10...
・MO8 type semiconductor device. Applicant's representative Patent attorney Takehiko Suzue 1st Fl! J Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1導電型の半導体基板のゲート形成予定領域に、素子形
成工程の前に予め前記半導体基板と同一導電型の不純物
を導入する工程を具備することを特徴とするMOa型半
導体装置の製造方法。
A method for manufacturing an MOa type semiconductor device, comprising the step of introducing an impurity of the same conductivity type as that of the semiconductor substrate into a region of a semiconductor substrate of one conductivity type where a gate is to be formed, before an element formation step.
JP15518081A 1981-09-30 1981-09-30 Manufacture of mos semiconductor device Pending JPS5856464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15518081A JPS5856464A (en) 1981-09-30 1981-09-30 Manufacture of mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15518081A JPS5856464A (en) 1981-09-30 1981-09-30 Manufacture of mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5856464A true JPS5856464A (en) 1983-04-04

Family

ID=15600232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15518081A Pending JPS5856464A (en) 1981-09-30 1981-09-30 Manufacture of mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5856464A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0422136A (en) * 1990-05-17 1992-01-27 Fujitsu Ltd Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272580A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Production of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272580A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Production of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0422136A (en) * 1990-05-17 1992-01-27 Fujitsu Ltd Manufacture of semiconductor device

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