JPS5764400A - Error correction system of storage contents - Google Patents

Error correction system of storage contents

Info

Publication number
JPS5764400A
JPS5764400A JP55139176A JP13917680A JPS5764400A JP S5764400 A JPS5764400 A JP S5764400A JP 55139176 A JP55139176 A JP 55139176A JP 13917680 A JP13917680 A JP 13917680A JP S5764400 A JPS5764400 A JP S5764400A
Authority
JP
Japan
Prior art keywords
address
error
circuit
read
sent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55139176A
Other languages
Japanese (ja)
Other versions
JPS6042506B2 (en
Inventor
Isao Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55139176A priority Critical patent/JPS6042506B2/en
Publication of JPS5764400A publication Critical patent/JPS5764400A/en
Publication of JPS6042506B2 publication Critical patent/JPS6042506B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To correct an error of software exactly, by giving an address information of 1 bit error detected by a storage device, to a diagnostic processor, holding it, and giving designation of rewrite to this address, to the storage device. CONSTITUTION:A read-out instruction from an arithmetic processing device is decoded by a cntrolling circuit 9 of a storage device 21, and an instruction pulse, an address, etc. are provided to a storage part 10. When a 1 bit error is detected from a read-out data which is sent to an error correcting and detecting circuit 11 from the storage part 10, the read-out data is corrected, and is sent to the arithmetic processing device through a system control device 11. At the same time, an error address 18 and an interruption signal 17 are sent to an address register 15 and a receiving circuit 14 of a diagnostic processor 6, from an address register circuit 13 and an interruption generating circuit 12, respectively, and are held. Subsequently, a memory access control part 16 transfers one rewrite instruction to an address which has caused the 1 bit error, in the control part 9, also corrects 1 bit by the error correcting and detecting circuit 11, and executes rewrite to the same address.
JP55139176A 1980-10-03 1980-10-03 Error correction method for memory contents Expired JPS6042506B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55139176A JPS6042506B2 (en) 1980-10-03 1980-10-03 Error correction method for memory contents

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55139176A JPS6042506B2 (en) 1980-10-03 1980-10-03 Error correction method for memory contents

Publications (2)

Publication Number Publication Date
JPS5764400A true JPS5764400A (en) 1982-04-19
JPS6042506B2 JPS6042506B2 (en) 1985-09-24

Family

ID=15239334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55139176A Expired JPS6042506B2 (en) 1980-10-03 1980-10-03 Error correction method for memory contents

Country Status (1)

Country Link
JP (1) JPS6042506B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03157744A (en) * 1989-11-15 1991-07-05 Nec Field Service Ltd Error correction rewrite system
JP2006260289A (en) * 2005-03-17 2006-09-28 Fujitsu Ltd Software error correction method, memory control device and memory system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03157744A (en) * 1989-11-15 1991-07-05 Nec Field Service Ltd Error correction rewrite system
JP2006260289A (en) * 2005-03-17 2006-09-28 Fujitsu Ltd Software error correction method, memory control device and memory system

Also Published As

Publication number Publication date
JPS6042506B2 (en) 1985-09-24

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