JPS57186880A - Static picture storing and reading-out circuit - Google Patents
Static picture storing and reading-out circuitInfo
- Publication number
- JPS57186880A JPS57186880A JP56072477A JP7247781A JPS57186880A JP S57186880 A JPS57186880 A JP S57186880A JP 56072477 A JP56072477 A JP 56072477A JP 7247781 A JP7247781 A JP 7247781A JP S57186880 A JPS57186880 A JP S57186880A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gate
- line
- input line
- negative pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/04—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa
- H04N1/047—Detection, control or error compensation of scanning velocity or position
- H04N1/053—Detection, control or error compensation of scanning velocity or position in main scanning direction, e.g. synchronisation of line start or picture elements in a line
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
Abstract
PURPOSE:To eliminate jitter generated on a TV picture, by independently feedback-controlling a reset operation of a binary counting circuit by obtaining a set signal by its own timing and a feedback line. CONSTITUTION:A clock signal of prescribed frequency sent from a main oscillator 6 and a frequency-divider 8 is applied to a binary counting circuit 1 through an input line 30. In a skipping circuit 10, when a set signal of a logical value ''1'' is applied from an input line and is set, a logical value ''0'' is provided to a gate 9 of OR from an output line 31 of an opposite logical side Q, therefore, a horizontal synchronizing negative pulse provided to an output line 72 from a synchronizing signal generator 7 resets the circuit 1 through the gate 9. Subsequently, when signals of output lines 21, 22, 24, 26, 27 and 29 of the circuit 1, and a clock signal of an input line 30 are inputted to a NAND gate 5, a negative pulse is outputted to an output line 51. This negative pulse sets the circuit 1 from an input line 92 through a gate 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56072477A JPS57186880A (en) | 1981-05-14 | 1981-05-14 | Static picture storing and reading-out circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56072477A JPS57186880A (en) | 1981-05-14 | 1981-05-14 | Static picture storing and reading-out circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57186880A true JPS57186880A (en) | 1982-11-17 |
Family
ID=13490436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56072477A Pending JPS57186880A (en) | 1981-05-14 | 1981-05-14 | Static picture storing and reading-out circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57186880A (en) |
-
1981
- 1981-05-14 JP JP56072477A patent/JPS57186880A/en active Pending
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