JPS57152131A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPS57152131A
JPS57152131A JP3644981A JP3644981A JPS57152131A JP S57152131 A JPS57152131 A JP S57152131A JP 3644981 A JP3644981 A JP 3644981A JP 3644981 A JP3644981 A JP 3644981A JP S57152131 A JPS57152131 A JP S57152131A
Authority
JP
Japan
Prior art keywords
etching process
metal
pattern
electrode wiring
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3644981A
Other languages
Japanese (ja)
Inventor
Koichi Kushibiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3644981A priority Critical patent/JPS57152131A/en
Publication of JPS57152131A publication Critical patent/JPS57152131A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To reduce quantity of side etching and to obtain the forming method of a pattern having favorable precision of process by a method wherein side etching parts generated theretofore are covered with a softened photo resist in the middle of etching process. CONSTITUTION:At the progress of work to make a metal 13 for electrode wiring to form the pattern, the etching process thereof is performed dividing the process into two times. Namely, nearly the half of thickness of the metal film is etched by the first time etching process (figure a). Then the heat treatment is performed, but the treatment thereof is performed at the temperature higher than the softening point of the photo resist film 14, and accordingly the phot resist film 14 is made to be softened to cover the side etching parts 15 of the metal 13 for electrode wiring generated by the first time etching process (figure b). The second time etching process is performed in this condition, and the metal 13 for electrode wiring is patternized (figure c).
JP3644981A 1981-03-16 1981-03-16 Formation of pattern Pending JPS57152131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3644981A JPS57152131A (en) 1981-03-16 1981-03-16 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3644981A JPS57152131A (en) 1981-03-16 1981-03-16 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS57152131A true JPS57152131A (en) 1982-09-20

Family

ID=12470115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3644981A Pending JPS57152131A (en) 1981-03-16 1981-03-16 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS57152131A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61222135A (en) * 1985-03-08 1986-10-02 Sharp Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61222135A (en) * 1985-03-08 1986-10-02 Sharp Corp Manufacture of semiconductor device

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