JPH10233964A - Solid-state image pickup device for forming binary signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device for forming a binary signal by which binarization is processed at a high speed with low S/N. SOLUTION: This solid-state image pickup device 10 for forming a binary signal is provided with vertical read lines 12a, 12b provided to pixels 1 and each column of the pixels 1 a vertical scanning circuit 13 that selects a specific row of the pixels 1 arranged in a matrix and transfers an electric signal in response to an incident light to the vertical read lines 12a, 12b in a desired timing, a binarization circuit 7 provided in each of the vertical read lines 12a, 12b, and a horizontal scanning circuit 15 that applies horizontal scanning to the vertical read lines 12a, 12b sequentially to transfer the signal to a horizontal read line 13. The binarization circuit 7 compares the electric signal outputted from the pixels 1 with a reference signal via an amplifier TR QA in the pixels 1 to output a binary signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device for forming a binary signal by binarizing image data obtained by a photodetector to obtain a binary image.

[0002]

2. Description of the Related Art Heretofore, a solid-state image pickup device (binary signal) in which image data (analog signals) obtained by pixels arranged in a matrix are compared with a reference value to thereby obtain a binary image. Forming solid-state imaging devices) and image processing devices are known. FIG. 10 is a circuit diagram showing an example of a conventional solid-state imaging device 100 for forming a binary signal.

The conventional solid-state imaging device 100 for forming a binary signal shown in FIG. 1 employs an XY address system.
Are arranged in a matrix (2 × 2 in the illustrated example), and each of the pixels 101, 101 is provided with a photodiode PD, PD, an amplifying transistor QA, QA, and the photodiode. A switching MOS transistor QT for connecting / disconnecting the PD from the amplifying transistor QA, a reset MOS for supplying a voltage to a gate of the amplifying transistor QA or discharging a charge accumulated in the gate; The transistors QP are provided.

Each of the pixels 101, 101... Is connected to a common vertical read line 102a, 102b for each column, and an electric signal corresponding to incident light from the pixels 101, 101. , 102b. In addition, in the solid-state imaging device 100 for forming a binary signal, storage circuits 107 for removing fixed pattern noise caused by a dark current or the like are provided in each of the vertical read lines 102a and 102b.

More specifically, the storage circuit 107 is composed of switching MOS transistors QD and QS and capacitors CD and CS, as shown in FIG. An electric charge corresponding to an electric signal from the pixel 101 according to the incident light is accumulated in CS. Then, the stored charges are output to the horizontal readout lines 112-1 and 112-2 at a fixed timing, and the horizontal readout lines 112-1 and 112-2 are output.
In the differential amplifier 115 arranged on 12-2, noise (fixed pattern noise) due to dark current or variation in each amplifying transistor QA of each pixel 101, 101... It is removed, and only an electric signal (analog signal) corresponding to the incident light is amplified and obtained.

The amplified signal (analog signal)
Is compared with a predetermined reference value VREF by a comparator 119, and a binarized signal is output from an output terminal VO.

FIG. 11 is a timing chart showing an example of the operation of the above-described solid-state imaging device 100 for forming a binary signal. In the periods t10 to t14, the readout operation of the pixels 1 in the first row is performed in the periods t20 to t14. t24 indicates a read operation of the pixel 1 in the second row. Here, the driving pulse φTG
1, φTG2 are switching MOS transistors QT, Q
The drive pulse φRD1, φRD2 is applied to the drain of the reset MOS transistors QP, QP, and the drive pulse φRG is applied to the reset MOS transistors QP, QP.
The drive pulse φRSV is applied to the gate of the P
The driving pulses φTD and φTS are driving pulses supplied to the gates of the transistors QRSV1 and QRSV2, respectively, and are supplied to the gates of the switching MOS transistors QD and QS, respectively. The driving pulses φH1 and φH2 are M
The drive pulse and the drive pulse φRSH supplied to the gates of the OS transistors QH1 and QH2 are drive pulses supplied to the gates of the reset switch MOS transistors QRSH1 and QRSH2.

When the operation timing reaches the period t10 in FIG. 11, the drive pulse φRG goes low, and the reset MOS transistor (p-channel type) QP turns on. Then, the drive pulse φRD1 changes to the read level (V
RD; high level), the voltage VRD is supplied to the gate (control region) of the amplification transistor QA in the first row via the reset transistor QP, and the gate is biased to the read level VRD (selection). ). still,
The amplifying transistor QA in the second row has a drive pulse φR
Since D2 remains at the low level (voltage level VRS), the gate is maintained at the voltage level VRS (low level) and off (unselected).

On the other hand, the drive pulse φRSV becomes high level, the reset switch MOS transistors (n-channel type) QRSV1 and QRSV2 are turned on, and charges remaining on the vertical read lines 102a, 102a are discharged (reset). At this time, the drive pulses φTD and φTS are also at a high level, the switching MOS transistors (n-channel type) QD and QS are turned on, and the capacitors CD and CS are turned on.
The remaining charge is also released (reset).

In this period t10, since the driving pulses φTG1 and φTG2 are both held at a high level, the transfer MOS transistor (p-channel type) QT
Is off, and charges (signal charges) corresponding to incident light are generated and accumulated in each photodiode PD. In the next period t11, the drive pulse φRG becomes high level and the reset MOS transistor (p-channel type)
QP is turned off, and the amplification transistor QA in the first row is turned off.
Gate (control region) is in a floating state,
The state is maintained while the voltage of the gate is biased to the read level VRD by the parasitic capacitance of the gate of the amplification transistor QA.

Further, the driving pulse φRD1 has a voltage level VR.
S (low level), the drive pulse φRSV is inverted to low level, and the vertical read lines 102a, 102b
Is reset. Then, the driving pulse φTS becomes low level, and the switching MOS transistor (n
Channel type) QS is turned off and the vertical read line 102
a and 102b are connected to only the capacitor CD of the two types of capacitors CD and CS.

As a result, in this period t11, the period t1
The voltage (denoted as VD) corresponding to the dark current charges the capacitor CD in a state where the amplifying transistor QA of the first row selected (turned on) by 0 performs a source follower operation and is biased to the read level VRD. Will be done.
The voltage (VD) according to the dark current includes noise (fixed pattern noise) caused by the dark current and the variation of each pixel 101, 101... For each amplifying transistor QA.

Next, when the period t12 is reached, the driving pulse φ
When TD goes low, the switching MOS transistor (n-channel type) QD turns off. Instead, the driving pulse φTS goes high, turning on the switching MOS transistor (n-channel type) QS, turning on the capacitor CS. Can be charged. At this time, the voltage corresponding to the dark current remains charged in the capacitor CD.

Then, the drive pulse φTG1 is inverted to a low level to turn on the transfer MOS transistor QT of the pixel 1 in the first row, and the signal charge from the photodiode PD in the first row is changed to the first row. Is transferred to the gate (control region) of the amplification transistor QA of the pixel 1. At the end of the period t12, that is, at the start of the period t13, the drive pulse φTG1 is inverted to the high level, the transfer MOS transistor QT in the first row is turned off again, and the amplification transistor QA in the first row is turned off. Is again in a floating state, but the voltage of the gate is kept elevated by the amount of the signal charges transferred from the photodiode PD due to the parasitic capacitance of the gate of the amplifying transistor QA.

By the source follower operation of the first-row amplifying transistor QA, an electric signal corresponding to the incident light is output to the vertical read lines 102a and 102b.
A voltage (denoted as VSS) according to the electric signal is charged in the capacitor CS. In this case, the voltage VSS is the sum of a voltage (denoted as VS) corresponding to only the incident light and a voltage VD corresponding to the dark current (VSS = VS + VD).

Next, at the end of the period t13, that is, the period t1
4, the drive pulse φTS goes low first to disconnect the vertical read lines 102a and 102b from the capacitor CS. In this state, the drive pulse φR
SV goes high and the vertical read line 102
The electric charges remaining in a and 102b are discharged (reset).
Then, during the period t14, the driving pulse φH1 from the horizontal scanning circuit 13 is raised to a high level for a certain period, and the signals (analog signals) from the capacitors CD and CR on the side of the vertical read line 102a are switched at the switching timing. The signals are read to the horizontal read lines 112-1 and 112-2, respectively, and the difference is amplified by the differential amplifier 115.
Is compared with a predetermined reference voltage VREF to perform a binarization process. The signal output from the differential amplifier 115 is obtained by subtracting the signal (VD) corresponding to the dark current from the electric signal (VSS = VS + VD) including the fixed pattern noise from the pixel 101 (corresponding to the incident light). Signal VS).

Thereafter, when the drive pulse φH2 is raised to a high level for a certain period, the vertical read line 102b
The same operation is performed on the side, and a binary signal is obtained. still,
When the reset switch MOS transistor QRSH is turned on by the high-level switching of the drive pulse φRSH twice in the period t14, the horizontal read line 1
12a and 112b are reset (initialized).

The reading operation of the pixels in the first row in the periods t10 to t14 described above is performed in the subsequent periods t20 to t14.
At 24, the same is repeated for the pixels in the second row. FIG. 12 is a block diagram illustrating a configuration of an image processing apparatus 120 that binarizes image data using another method.

The image processing apparatus 120 includes a solid-state imaging device 121, an AD conversion circuit 122 for converting a signal (analog signal) representing image data obtained by the solid-state imaging device 121 into a digital signal, and an A / D conversion circuit. 1
Image memory 123 for storing digital signals from
And an image processing circuit 124 for binarizing the digital image data stored in the image memory 123.

That is, in the image processing apparatus 120, after an analog signal obtained by the solid-state imaging device 121 is converted to a digital signal by an AD conversion circuit 122 provided outside the solid-state imaging device 121, the image memory 123 Is temporarily stored in the image processing circuit 124 and is compared with a predetermined reference value to be binarized.

[0021]

However, the conventional solid-state imaging device 1 for forming a binary signal shown in FIG.
At 00, an electric signal (analog signal) corresponding to the electric charge generated and accumulated in the pixel 101 and a reference signal (analog signal) output from the vertical scanning circuit 106 via the amplifying transistor QA (amplifying means) are output. The signal must be transmitted to the comparator 115, so that the path through which the analog signal is transmitted becomes longer, and noise is more likely to be applied to these analog signals (reduction of the S / N ratio).

In particular, the influence of noise caused not only by the pixel portion but also by the column-by-column variation of peripheral circuit elements (variation in the manufacture of capacitors, MOS transistors for switches, etc.) increases. In the conventional image processing apparatus 120 shown in FIG. 12, the video signal is output from the solid-state imaging device 121 as an analog signal, converted into a digital signal, and then subjected to a binarization process. There is a disadvantage that peripheral circuits other than the imaging device 121 are complicated and the entire image processing device 120 is expensive.

Further, the effective range of the video signal obtained by the image processing device 120, that is, the dynamic range is AD
Although limited by the input of the conversion circuit 122, the input dynamic range of the AD conversion circuit 122 is generally narrower than the dynamic range of the solid-state imaging device 121. Therefore, a wide dynamic range of the solid-state imaging device 121 is effective in the binarization process. There was also a problem that it could not be used.

For example, it has been considered that the above-mentioned binarization processing is performed by separately providing an image processing circuit for each pixel of the solid-state imaging device and having a binarization function for each pixel. The structure of the pixel itself becomes complicated, causing a decrease in the aperture ratio of the solid-state imaging device and a decrease in resolution.
Further, when an image processing circuit is separately provided for each pixel as described above, there is a disadvantage that it is not possible to meet a demand for arranging pixels at high density and increasing the number of pixels.

The present invention has been made in view of the above problems, and has been described in detail in connection with the binarization processing of image data.
An object of the present invention is to provide a solid-state imaging device for forming a binarized signal capable of increasing the / N ratio.

[0026]

According to a first aspect of the present invention, there is provided a method for outputting a plurality of signal charges generated by a photodetector through an amplifying means. Pixel, a plurality of vertical read lines provided for each column of the plurality of pixels, and a specific row of the plurality of pixels, and an electric signal corresponding to a signal charge from a photodetector of the pixel. At a desired timing, vertical scanning means for transferring the signal to the vertical readout line, an electric signal provided for each of the vertical readout lines, the electric signal corresponding to the signal charge output from the pixel at the desired timing, A plurality of vertical read lines sequentially and horizontally scanned by a binarizing unit that compares a reference signal output through the amplifying unit with a timing different from a desired timing and outputs a binarized signal; 2 above It is obtained by a horizontal scanning means for transferring signal to the horizontal output line.

According to a second aspect of the present invention, the photodetector comprises a photoelectric conversion element for generating a signal charge in accordance with incident light, and the photodetector is provided in the amplifying means and in the control region of the amplifying means. A first switch for selectively supplying a signal charge from the conversion element, and a second switch for selectively supplying a desired potential from outside the pixel to a control region of the amplifier. Are connected.

According to a third aspect of the present invention, the binarizing means includes a first storage means for storing an electric signal corresponding to the signal charge generated by the photoelectric conversion element; Second storage means for storing a reference signal corresponding to the desired potential from outside of the apparatus, the electric signal stored in the first storage means, and the reference signal stored in the second storage means And a comparison means for outputting a binarized signal by comparing the above.

According to a fourth aspect of the present invention, the first storage means is a charge storage means for storing a charge corresponding to the electric signal output from the pixel, and the second storage means is provided. , A charge accumulating means for accumulating charges corresponding to the reference signal output from the pixel.

According to a fifth aspect of the present invention, there is provided a transfer for selectively transferring the electric signal or the reference signal output from the pixel between the pixel and the two charge storage means. A switching means is provided. The invention according to claim 6 is characterized in that the amplifying means is a junction field effect transistor, and the gate of the junction field effect transistor has the signal charge generated by the photoelectric conversion element, The desired potential from the outside is selectively supplied.

According to a seventh aspect of the present invention, the binarizing means includes a current source, and the reference signal according to the desired potential supplied from outside the pixel is a current of the current source. Bias means for biasing the potential of the vertical read line so as to be equal; bias storage means for storing a bias state of the bias means; and an electric signal corresponding to the signal charge generated by the photoelectric conversion element. Current detection means for detecting a difference from the current of the current source; and a current detection means for detecting a difference between the electric signal corresponding to the signal charge generated by the photoelectric conversion element and the current of the current source. And switching means for inputting the data to

Further, in the invention according to claim 8, the bias means is constituted by a constant current transistor having a main current path connected between the vertical read line and the current source,
The bias storage means is provided between a control electrode of the constant current transistor and a terminal connected to the current source among terminals of a main current path of the constant current transistor; Sampling / hold switching means for sampling the bias state of the transistor and thereafter holding the bias state; and bias charge storage means connected to the control electrode of the constant current transistor and holding the bias of the constant current transistor. It was done.

According to a ninth aspect of the present invention, the comparing means is connected to an output signal storing means for storing the binarized signal from the comparing means. According to a tenth aspect of the present invention, the photoelectric conversion element is a buried photodiode.

(Operation) According to the first aspect of the present invention,
By the binarization means provided for each of the plurality of vertical read lines,
A binarized signal of image data is generated, and the generated binarized signal is transmitted from the vertical readout line to the horizontal readout line, and further to the output terminal. Even if noise is superimposed on the electric signal (binary signal), the effect is smaller than in the case of an analog signal.

According to the second aspect of the present invention, since the reference signal used for performing the binarization is output through the amplifying means of the pixel, an electric signal corresponding to the incident light is output. The reference signal and the reference signal can be output through the same path. or,
According to the third aspect of the invention, the electric signal and the reference signal corresponding to the incident light to be output are sequentially stored once through the pixel, and the stored values are simply compared with each other. A quantified signal can be obtained.

According to the fourth aspect of the present invention, it is possible to appropriately store the reference signals sequentially outputted via the pixels in a capacitor or the like. According to the fifth aspect of the present invention, the reference signal output from the amplifying unit and the electric signal corresponding to the incident light can be selectively supplied to the two charge storage units by the transfer switching unit. .

According to the sixth aspect of the present invention, since the electric charge corresponding to the incident light can be directly transferred to the gate, the transfer path of the electric charge is shortened, and the noise is less likely to occur. According to the present invention, the reference signal reflecting the fixed pattern noise of the pixel is easily stored, and the stored reference signal is compared with the electric signal corresponding to the incident light by a simple method. Thus, a binary signal can be obtained.

According to the invention, a circuit for comparing a reference signal with an electric signal to generate a binary signal can be achieved with a simple configuration. According to the ninth aspect of the present invention, since the binarized detection signal is stored in the output signal storage means, the detection signal can be appropriately read from the output terminal at a desired timing. it can.

According to the tenth aspect of the present invention, in the photoelectric conversion element of each pixel, the depletion layer generated at the pn junction of the photodiode does not reach the surface of the pixel, so that dark current is suppressed. You.

[0040]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a circuit diagram showing a schematic configuration of a solid-state imaging device 10 for forming a binary signal according to the first embodiment. In the first embodiment, in order to simplify the description, the four pixels 1, 1, 1, 1 are arranged in a matrix (2
(2) will be described. The pixel 1 (indicated by a broken line in FIG. 1) is a photodiode (photodetector; photoelectric conversion element) PD that generates and accumulates charges according to incident light.
An amplifying transistor (amplifying means; an amplifier) that outputs an electric signal (analog signal) corresponding to incident light to its source in accordance with a signal charge supplied to a control region (control electrode; gate).
In this embodiment, an n-channel junction field effect transistor (JFET) QA and the photodiode P
A transfer MOS transistor (p-channel) for selectively supplying the charge generated and accumulated in D and the potential (voltage levels VRS, VRF, VRD) supplied from the vertical scanning circuit 6 to the gate (control region). (Type) QT (first switch means) and a reset MOS transistor (p-channel type) QP (second switch means) for resetting signal charges accumulated in the gate (control region). ing.

In this embodiment, the photodiode P
As D, a buried photodiode having a vertical overflow structure is used. The reset MOS transistor QP has a potential (voltage level VRS, VR) corresponding to the reference signal sent from the clock lines 4a, 4b.
F, VRD) to the gate (control region).

A power supply voltage VD is connected to the cathode of the photodiode PD.
D outputs a signal charge corresponding to the incident light. A power supply voltage VD is connected to the drain of the amplifying transistor QA so that an electric signal (analog signal) corresponding to the electric charge stored in the gate (control region) by the source follower operation is output from the source. Has become.

The source of the amplifying transistor QA of each pixel 1 is commonly connected to the vertical readout lines 2a and 2b for each column of the matrix arrangement. On the other hand, the gate of the transfer MOS transistor QT is commonly connected to the clock lines 3a and 3b connected to the vertical scanning circuit 6,
When a low-level drive pulse φTG1 or φTG2 is supplied from the vertical scanning circuit 6, the transfer MOS transistors QT are sequentially turned on for each row.
The vertical scanning circuit 6, the clock lines 3a, 3b, 4
a, 4b, etc. constitute a vertical scanning means.

The drains of the reset MOS transistors QP are commonly connected to clock lines 4a and 4b connected to the vertical scanning circuit 6 for each row, and the gates thereof are
Drive pulse generation circuit (not shown) via row line 5a
Side node 5. Also, reset MOS
The source of the transistor QP is shared with the drain of the transfer MOS transistor QT. When a low-level pulse φRG is supplied from the drive pulse generation circuit to the gate of the reset MOS transistor QP, the reset MOS transistor QP is turned on.

In the middle of the above-mentioned vertical read lines 2a and 2b, a binarizing circuit (binarizing means) 7 is arranged for each column (shown by a broken line in the figure). The vertical read lines 2a and 2b on the output side of the binarization circuit 7 are
One terminals of binarized signal storage capacitors CO1 and CO2 are connected via S transistors (n-channel type) QO1 and QO2.

Further, a binary signal storage capacitor CO
1 and CO2 are connected to the horizontal readout switch MOS transistors (n-channel type) QH1 and QH, respectively.
2, a horizontal read line 12 is connected, and an output buffer amplifier 15 is connected to the subsequent stage. still,
The other terminals of the binarized signal storage capacitors CO1 and CO2 are grounded.

In this case, the gates of the switching MOS transistors QO1 and QO2 are connected to the clock line 10a.
Through the node 1 on the side of the drive pulse generation circuit (not shown)
The switching MOS transistors QO1 and QO2 are turned on when a high-level driving pulse φTO is supplied to the gates of the switching MOS transistors QO1 and QO2 from the driving pulse generation circuit.

The gates of the horizontal readout switch MOS transistors QH1 and QH2 are connected to horizontal selection signal lines 11a and 11b, respectively, so that the horizontal scanning circuit 13 connected to the horizontal scanning circuit 13 has a high level. When the drive pulses φH1 and φH2 are applied to the gates of the horizontal readout switch MOS transistors QH1 and QH2, they are turned on, and horizontal readout control (horizontal scanning) is performed. The horizontal scanning means is constituted by the horizontal selection signal lines 11a and 11b, the horizontal scanning circuit 13, and the like.

The horizontal read line 12 has a reset switch MOS transistor (n-channel type) QR
The drain of SH is connected. The source of the reset switch MOS transistor QRSH is grounded. The gate of the reset switch MOS transistor QRSH is connected to the clock line 14.
The clock line 14a is connected to a node 14 on the side of a drive pulse generating circuit (not shown).
Then, the high-level drive pulse φRSH is supplied from the drive pulse generation circuit to the reset switch MOS transistor Q.
When applied to the gate of RSH, the reset switch MOS transistor QRSH is turned on.

The vertical read lines 2a and 2b are connected to the drains of reset switch MOS transistors (n-channel type) QRSV1 and QRSV2 and the constant current sources 17a and 17b for each column. At this time, the reset switch MOS transistors QRSV1 and QRS
The source of V2 is grounded, and a power supply voltage VC (negative) is connected to each of the constant current sources 17a and 17b.

The gates of the reset switch MOS transistors QRSV1 and QRSV2 are connected via a clock line 16a to a node 16 on the side of a drive pulse generating circuit (not shown), and the drive transmitted from the drive pulse generating circuit is provided. When the pulse φRSV is applied to the gates of the reset switch MOS transistors QRSV1 and QRSV2, the reset switch MO transistor
The S transistors QRSV1 and QRSV2 are turned on.

The above-mentioned binarization circuit 7 (shown by broken lines in FIG. 1) branches to two read lines 2a-1, 2a-2, 2b-1, and 2b-1 at nodes n1 and n2, respectively. The vertical read lines 2a and 2b are arranged. That is, the switching MOS is connected to the readout lines 2a-1 and 2b-1.
A transistor (n-channel type) QR (transfer switching means) and a reference signal storage capacitor CR (second storage means) are connected. Further, a switching MOS transistor (n-channel type) QS is connected to the readout lines 2a-2 and 2b-2.
(Transfer switching means) and an output signal storage capacitor CS (first storage means) are connected.

The two read lines 2a-1 and 2a-2 and the read lines 2b-1 and 2b-1 are both connected to a voltage comparator AC (comparing means). Thus, the binary signal (2
Is output. On the other hand, the gates of the switching MOS transistors QS, QR are connected to the clock lines 8a,
Drive pulse generating circuits (not shown) through 9a
The switching MOS transistors QS and QR are turned on when high-level driving pulses φTS and φTR are respectively supplied to the gates from the driving pulse generating circuit.

Next, the operation of the binary signal forming solid-state imaging device 10 having the above configuration will be described with reference to the timing chart of FIG. Note that, in FIG.
t17 indicates the readout operation of the pixel 1 in the first row in FIG. 1, and the period t20 to t27 indicates the readout operation of the pixel 1 in the second row.

As shown in FIG. 2, before the period t10,
The drive pulses φTG1 and φTG2 are held at a high level, the drive pulses φRD1 and φRD2 are held at a low level (voltage level VRS), the drive pulse φRG is held at a high level, and the drive pulses φRSV and φT
R and φTS are held at the low level, and the driving pulse φTO
Is held at a low level. Note that the drive pulse φH
1, φH2 and the drive pulse φRSH are all held at a low level.

Then, during the period t10, the driving pulse φRG is inverted to a low level, the driving pulse φRSV is inverted to a high level, and the driving pulses φTR and φTS are inverted to a high level.

When the driving pulse φRG goes low, the reset MOS transistor (p-channel type) QP is turned on. When the drive pulse φRSV goes high, the reset switch MOS transistors (n-channel type) QRSV1 and QRSV2 are turned on. When the driving pulses φTR and φTS become high level, the switching MOS transistor (n-channel type) Q
R and QS are turned on.

At this time, since the drive pulse φTO is held at a low level, the switching MOS transistors QO1 and QO2 are off. Further, the drive pulses φRD1 and φRD2 are both at the voltage level VRS (low level), and the voltage VRS is applied to the gate (control region) of each amplifying transistor QA via the reset transistor QP which is turned on. It is transmitted.

At this time, the gate (control region) of the amplifying transistor QA is biased to the voltage level VRS. This potential is at a low level, and the amplification transistor QA
Turns off. In this period t10, as described above, the reset switch MOS transistors QRSV1, QRSV1,
Since both the QRSVs 2 are on, the sources of the amplifying transistors QA of all the pixels 1 are grounded.

At this time (period t10), the switch MO
Since the S transistors QR and QS are turned on as described above, the signal charges remaining in the reference signal storage capacitor CR and the output signal storage capacitor CS are also transferred to the constant current source 17.
a and 17b (reset). In this period t10, since the driving pulses φTG1 and φTG2 are both held at a high level, the transfer MOS transistor (p-channel type) QT is turned off, and each photodiode PD receives incident light. Corresponding charges (signal charges) are generated and accumulated.

Next, during the period t11, the driving pulse φ
RD1 is set to the reference voltage level VRF, and the drive pulse φT
S is inverted to low level. The switching MOS transistor (n
The channel type) QS is turned off. Further, at this time, the reference voltage level VRF is applied to the gate (control region) of the amplifying transistor QA of each pixel 1 in the first row via the resetting MOS transistor QP in the first row already held on. Supplied to

The first-row amplifying transistor QA supplied with the reference voltage level VRF in this way is turned on, and the gate (control region) of the amplifying transistor QA is biased to the reference voltage level VRF. Since the drive pulse φRD2 remains at the low level (voltage level VRS), the gate (control region) of each amplification transistor QA in the second row is kept off (unselected) while maintaining the voltage level VRS. Is done.

Next, when the period t12 is reached, the driving pulse φ
RD1 is set to voltage level VRS (low level), drive pulse φRG is inverted to high level, and drive pulse φRSV is inverted to low level. When the drive pulse φRG goes high, the reset MOS transistor (p-channel type) QP is turned off, and the gate (control region) of the first row amplifying transistor QA is in a floating state. Due to the parasitic capacitance of the gate of the amplifying transistor QA, the state of the gate voltage is maintained while being biased to the reference voltage level VRF.

In this period t12, since the drive pulse φRSV is at the low level as described above, the reset switch MOS transistor (n-channel type) Q
RSV1 and QRSV2 are both turned off. Since the drive pulse TS remains at the low level, the switch MO
The S transistor (n-channel type) QS remains off.

As a result, during the period t12, the period t
11, the amplifying transistor QA in the first row selected (turned on) performs a source follower operation, and the potential of the source of the amplifying transistor QA (this potential is referred to as VSR).
Means that the current (drain current) flowing between the source and the drain is IB (current value flowing through the constant current sources 17a and 17b)
Rise until At this time, the current (drain current) IB is equal to the switch M which is already turned on.
It flows through the OS transistor QR to the reference signal storage capacitor CR, and is charged so that the voltage across the both ends becomes VSR.

In the period t12, when the current flowing between the source and the drain becomes IB due to the source follower operation, the potential VSR of the source of the amplifying transistor QA
Is a value represented by the following equation (1). VSR = VRF-VT (1) Here, VT is a gate-source voltage when the drain current of each amplifying transistor QA is IB.

Next, during the period t13, the driving pulse φ
RG is inverted to low level, and drive pulse φTR is inverted to low level. When the drive pulse φTR goes low, the switching MOS transistor (n-channel type) QR is turned off, and the reference signal storage capacitor CR receives the potential VSR represented by the above equation (1) charged in the period t12. Hold.

When the drive pulse φRG goes low, the reset MOS transistor (p-channel type) QP is turned on. Next, when the period t14 is reached,
The drive pulse φRD1 has the voltage level VRD (= read level <VRF). At this time, the voltage VRD is transmitted to the gate (control region) of each of the amplifying transistors QA in the first row through the reset switch MOS transistors QP in the first row that have already been turned on. The gate is biased to the read level VRD.

Next, when the period t15 is reached, the driving pulse φ
TG1 is inverted to low level, drive pulse φRD1 is inverted to low level (voltage level VRS), and drive pulse φRG is inverted to high level. When the drive pulse φRG is inverted to the high level, the reset MOS transistor QP is turned off, and the first
Although the gate (control region) of the amplifying transistor QA in the row is in a floating state, the voltage of the gate is kept biased at the voltage level VRD by the parasitic capacitance of the gate of the MOS transistor QP.

Further, when the driving pulse φTG1 is inverted to the low level, the transfer MOS of the pixel 1 in the first row is changed.
The transistor QT turns on. At this time, the signal charge generated and accumulated in the photodiode PD of the pixel 1 on the first row is transferred to the gate (control region) of the amplification transistor QA of the pixel 1 on the first row. Then, due to the transfer of the signal charge, an electric signal (voltage signal) corresponding to the charge (signal charge) received in the gate (control region) is vertically read from the amplifying transistor QA in the first row by the source follower operation. Output to lines 2a and 2b.

That is, as described above, the amplification transistor Q
When the signal charge corresponding to the incident light is supplied from the photodiode PD to the gate (control region) of A, the potential of the gate of the amplifying transistor QA also increases according to the supplied charge. The rise in the potential causes the amplifying transistor QA in the first row to perform a source follower operation, and the source potential of the amplifying transistor QA also rises in accordance with the rise in the gate potential.

At the end of the period t15, that is, the period t15
At the start of the drive pulse 16, the drive pulse φTG1 is inverted to the high level, and the transfer MOS transistor Q
T turns off again. This transfer MOS transistor Q
When T is turned off, the transfer of the signal charges generated and accumulated in the photodiodes of the pixels 1 in the first row ends, and the gate (control region) of the amplifying transistor QA in the first row returns to the floating state again. However, the voltage of the gate of the amplifying transistor QA is maintained as it is raised by the amount of the signal charges transferred from the photodiode PD due to the parasitic capacitance of the gate of the amplifying transistor QA.

Next, when the period t16 is reached, the driving pulse φ
TS and φTO are inverted to high level. When the drive pulse φTS goes high, the switch M
The OS transistor (n-channel type) QS is turned on.
By turning on the switching MOS transistor QS, an electric charge corresponding to the potential of the source of the amplification transistor QA in the first row is charged in the output signal storage capacitor CS.

On the other hand, when the drive pulse φTO goes high, the switching MOS transistor QO
1 and QO2 are both turned on. By the way, this period t1
6, when the current flowing between the source and the drain becomes IB due to the source follower operation of the amplifying transistor QA, the potential of the source of the amplifying transistor QA (VSS
S) is a value represented by the following equation (2).

VSS = VRD + VS−VT (2) Here, VT is a gate-source voltage when the drain current of each amplifying transistor QA is IB, and VS is (charge / gate capacitance according to incident light). This is the rise in the gate potential that is represented.

Further, since the driving pulse φTS is at a high level (the switching MOS transistor QS is on),
Both ends of the output signal storage capacitor CS are connected during the period t1.
6 is charged to the potential VSS represented by the above equation (2). Note that this potential VSS is not changed until the drive pulse φTS is inverted to the low level at the end of the period t16 (at the start of the period t17) and the switching MOS transistor QS is turned off. Is charged.

As described above, the reference signal storage capacitor C
A voltage VSD (= VRF−VT) is held at both ends of R, and both ends of the output signal storage capacitor CS are connected to the voltage VSS.
(= VRD + VS−VT), the voltage comparator A
C, the voltages VSD and VS generated in the reference signal storage capacitor CR and the output signal storage capacitor CS are generated.
The magnitudes of S are compared, and a binarized signal representing the comparison result is output.

In the period t16, the driving pulse φTO
Is at a high level, the switching MOS transistors (n-channel type) QO1 and QO2 are turned on, and the value of the binarized signal is changed via these switching MOS transistors (n-channel type) QO1 and QO2. Are stored in the binarized signal storage capacitors CO1 and CO2.
At this time, the drive pulses φH1 and φH2 are both at low level, and the switching MOS transistor (n-channel type)
QH1 and QH2 are both off.

Incidentally, the reference voltage level VRF can be set arbitrarily as long as the value is higher than the read voltage VRD. If the reference voltage level is set based on the read voltage VRD (for example, set to the sum of the read voltage VRD and the reference voltage VREF), the reference voltage VREF and the signal voltage VS are used.
And can be directly compared.

Assuming that the reference voltage level at this time is VSR1, the value of VSR1 is expressed by the following equation (3). VSR1 = VRF-VT = VRD + VREF-VT (3) Accordingly, the difference (comparison result) between the voltage VSS and the voltage VSR1 has a relationship represented by the following equation (4).

VSS−VSR1 = (VRD + VS−VT) − (VRD + VREF−VT) = VS−VREF (4) Therefore, the output of the voltage comparator AC is the photodiode P
D, a signal voltage VS corresponding to the charge obtained at D, and a reference voltage V
REF and a binarized signal obtained by comparison.

If the signal voltage VS corresponding to the incident light is higher than the reference voltage VREF, the output of the voltage comparator AC becomes the power supply voltage VD (high level), and the signal voltage VS corresponding to the incident light becomes the reference voltage VD. If it is smaller than (VREF), the output of the voltage comparator AC is at the ground level (low level). In other words, the signal voltage VS corresponding to the incident light
Is converted to a binary signal by the voltage comparator AC with the reference voltage VREF as a threshold level.

The gates in the above equations (1) to (4)
It is known that the value of the source-to-source voltage VT is a factor of variation and fixed pattern noise for each amplifying transistor QA. As described above, the electric signal (signal voltage) and the reference signal (reference voltage) are read out and compared with each other so that the drain current of the same amplifying transistor QA has a constant value IB. When converting into a binarized signal, it is possible to remove the influence of the fixed pattern noise on the binarized signal due to the variation of each amplifying transistor QA of each pixel 1.

The binarized signal output from the voltage comparator AC is the switching MOS transistors QO1 and QO2 which are held on at this time (period t16).
, Binarized signal storage capacitors CO1, CO2
Is charged.

At the end of the period t16, the driving pulse φTO is inverted to low level, so that the switching MOS transistors QO1 and QO2 are turned off,
The capacitors CO1 and CO2 for storing binarized signals are in a floating state. As a result, the binarized signal is held in the binarized signal storage capacitors CO1 and CO2, respectively.
Next, when the period t17 is reached, the driving pulse φH1 from the horizontal scanning circuit 13 rises to a high level for a certain period, and is thereafter kept at a low level.

The drive pulse φH2 is raised to a high level for a predetermined period at predetermined intervals after the drive pulse φH1 is held at a low level, and is then held at a low level. Further, the drive pulse φRSH is raised to a high level for a certain period of time after the drive pulse φH1 falls to a low level and before the drive φH2 rises, and is thereafter held at a low level.
Then, after the drive pulse φH2 falls to a low level, the drive pulse φH2 rises to a high level again for a certain period of time, and is thereafter kept at a low level.

When the driving pulse φH1 is switched to the high level, the binarized signal held in the binarized signal storage capacitor CO1 is read out to the horizontal read line 12 at the switching timing, and is output to the output buffer. Amplifier 1
5 sequentially output to the output terminal VO. Subsequently, when the reset switch MOS transistor QRSH is turned on by the high-level switching of the drive pulse φRSH, the horizontal read line 12 is reset (initialized). This is because, when a voltage signal is read out to the horizontal read line 12 by the parasitic capacitance of the horizontal read line 12, a part of the electric signal (voltage signal) is held in the parasitic capacitance. This is for resetting the electric signal remaining in the device.

When the drive pulse φH2 is switched to the high level, the binarized signal held in the binarized signal storage capacitor CO2 is read out to the horizontal read line 12 at the switching timing, and the output buffer amplifier Fifteen
Are sequentially output to the output terminal VO. Finally, when the drive pulse φRSH switches to a high level, the reset switch MOS transistor QRSH is turned on, and the horizontal read line 12 is reset (initialized) again.

The electric signal (voltage signal) read to the horizontal read line 12 takes a long time to reach a steady state due to the waveform distortion due to the influence of the above-mentioned parasitic capacitance of the read line. Since the electric signal (voltage signal) appearing on the horizontal read line 12 has already been converted into a binary signal, it is possible to determine whether the electric signal represents a high level or a low level even if the electric signal does not reach a steady state. This makes it possible to speed up the reading operation.

At the end of period t17 (until period t20), drive pulse φRG is inverted to low level, and drive pulse φRSV, drive pulse φTR, and drive pulse φTS are inverted to high level. When the drive pulse φRG goes low, the reset switch MOS transistor QP turns on.

When the driving pulse φRSV goes high, the switching MOS transistor QRSV
1 and QRSV2 are both turned on and the vertical read line 2
The charges on a and 2b are discharged. Also, the driving pulse φT
When R and φTS go high, the switching MOS transistors QR and QS are turned off, and the reference signal storage capacitor CR and the output signal storage capacitor C are turned off.
The charges stored in S are discharged.

The above-described readout operation of the pixels in the first row in the periods t10 to t17 is performed in the subsequent periods t20 to t17.
At 27, the same is repeated for the pixels in the second row.

Next, a specific configuration of the pixel 1 shown in FIG. 1 will be described in detail with reference to FIGS. As shown in FIG. 1, the pixel 1 includes a buried photodiode PD having a vertical overflow structure for generating and accumulating a signal charge according to incident light, and the buried photodiode P
D, and a junction field-effect transistor QA that amplifies the signal charges stored in the buried photodiode PD.
Transfer MOS transistor QT for transferring to the gate of A
And a reset MOS transistor QP for resetting the charge of the gate of the junction field effect transistor QA.

FIGS. 3A to 3C are views showing the device structure of the pixel 1 shown in FIG. 1, of which FIG.
FIG. 3 is a plan view showing an example of a device structure of the pixel 1, and FIG.
3B is a cross-sectional view taken along line X1-X1 in FIG. 3A, and FIG. 3C is a cross-sectional view taken along line Y1-Y1 in FIG. As shown in FIGS. 3A to 3C, the pixel 1 includes an embedded photodiode PD that generates and stores a signal charge corresponding to incident light, and an electricity corresponding to a signal charge received at a gate (control region). An amplifying transistor (JFET) QA for outputting a signal, and a transfer MOS transistor QT for transferring a signal charge generated and accumulated by the embedded photodiode PD to a gate (control region) of the amplifying transistor (JFET) QA. A reset MOS transistor QP for resetting the charge of the gate (control region) of the amplifying transistor (JFET) QA.
It is constituted by.

The transfer MOS transistor QT
Represents a p region of the buried photodiode PD and an amplifying transistor (JFET) Q, as shown in FIG.
A p-type MOS transistor having a p-type gate region of A as two diffusion layers and TG as a gate is configured.

The reset MOS transistor QP
As shown in FIG. 3B, RG is
(P region) as a drain and a p-channel type MOS having a source as a p region constituting a gate of the amplification transistor QA
It is configured as a transistor. As shown in FIGS. 3A to 3C, the embedded photodiode PD itself has an npnp vertical direction from the surface of the n-type silicon layer (n ⁺ ) toward the p-type silicon substrate (p-Sub). A buried photodiode having a mold overflow structure (a buried photodiode is formed by npn and an overflow structure is formed by pnp) is formed.

Therefore, bleeding phenomena such as blooming and smear can be suppressed by the overflow structure absorbing the overflowing carriers, and the depletion layer generated at the pn junction by the buried photodiode PD does not reach the surface. Since the current is suppressed and no charge remains in the photodiode PD after the transfer of the signal charge, ideal characteristics in which afterimages and reset noise are suppressed can be obtained.

Further, an amplifying transistor (JFET) QA
As shown in FIGS. 3A to 3C, the n ⁺ type source region and the n ⁺ type drain region and the p type gate region (p
Gate) and an n-type channel region (n-channel). Of these, the p-type gate region (p-gate)
The p-type gate regions (p-gates formed above and below) are formed above and below the channel region (n-channel). (P-gate) and p-type silicon substrate (p-Sub) are electrically separated by an n-well.

As a result, the influence of the substrate voltage (substrate bias effect) on the characteristics of the photodiode PD itself as a photoelectric conversion element is greatly reduced, and each pixel 1, 1, 1, 1
There is a great effect in improving the resolution of the image and reducing the variation in the characteristics (for example, the reduction of fixed pattern noise).

As described above, according to the solid-state imaging device 10 for forming a binarized signal of the first embodiment, the path from which the electric signal corresponding to the incident light is obtained from the photodiode PD and the reference signal are obtained. Route is the same,
The S / N ratio can be increased by eliminating the influence of not only the pixel portion but also the subsequent variations of the peripheral circuit elements in each column (variations in the manufacturing of capacitors, switching MOS transistors, etc.).

Further, since the removal of the fixed pattern noise caused by the dark current, which has been conventionally performed, is performed at the time of generating the reference signal, the difference which has been conventionally required for removing the fixed pattern noise is conventionally used. No dynamic amplifier is required. (Second Embodiment) Next, a binary signal forming solid-state imaging device 20 according to a second embodiment will be described with reference to FIGS.

The solid-state imaging device 20 for forming a binarized signal according to the second embodiment has only the configurations of the solid-state imaging device 10 for forming a binarized signal and the binarization circuit 27 according to the first embodiment. different. Therefore, the solid-state imaging device 20 for forming a binary signal
The same components as those of the binary signal forming solid-state imaging device 10 are denoted by the same reference numerals, and description thereof is omitted.
Binarization circuit 27 of solid-state imaging device 20 for forming a binarized signal
4, a bias MOS transistor (p-channel type) QB (bias means) and a switching MOS transistor (p-channel type) QRB as shown in a broken line in FIG.
(Bias storage means; sample / hold switching means)
And a switching MOS transistor (n-channel type) Q
SB (switching means) and bias storage capacitor CRB
(Bias storage means; bias charge accumulation means), current detection MOS transistor (n-channel type) QX (current detection means), binarized output MOS transistor (n-channel type) QY, and load current source CS And inverter A
X. The inverter AX outputs a binary signal obtained by comparing an electric signal corresponding to the incident light from the pixel 1 with a predetermined reference signal. Note that this binarization circuit 27
Each of the vertical readout lines 22a and 22b is arranged in the middle of each of the plurality of pixels 1, 1, 1, and 1 arranged in a matrix.

More specifically, the bias MOS transistor QB constituting the binarization circuit 27 has its source
The drains (main current paths) are connected to the corresponding vertical read lines 22a and 22b, respectively, and the gates are connected to one terminal of the bias storage capacitor CRB. The other terminal of the bias storage capacitor CRB is grounded.

The node n21 to which the source of the bias MOS transistor QB is connected is connected to the switch MO.
The one terminal of the bias storage capacitor CRB is connected via the S transistor QRB. Further, a constant current source (current source) 17 is connected to this node n21.
a and 17b are connected. On the downstream side of the node n21 (the lower part in FIG. 4), a current detecting MOS transistor QSB is connected via a switching MOS transistor QSB.
The drain and gate of X and the gate of the binarized output MOS transistor QY are connected.

In this case, the source of the current detecting MOS transistor QX and the binarized output MOS transistor QY
Are connected to a power supply voltage VC (negative). Further, the drain of the binarized output MOS transistor QY is connected to a load current source CS and an inverter AX.
Is connected to the input terminal of In this case, the power supply voltage VD (positive) is connected to the load constant current source CS.

The gate of the switching MOS transistor QRB is connected to a node n23 on the side of a drive pulse generating circuit (not shown) via a clock line 23a.
It is connected to the. Thus, when a low-level drive pulse φR is applied from the drive pulse generation circuit to the gate of the switching MOS transistor (p-channel type) QRB, the switching MOS transistor QRB is turned on.

The switching MOS transistor Q
The gate of the SB is connected to a node n24 on the side of a drive pulse generation circuit (not shown) via a clock line 24a. When a high-level drive pulse φS is supplied from the drive pulse generation circuit to the gate of the switching MOS transistor (n-channel type) QSB, the switching MOS transistor QSB is turned on.

Next, generation of a binary signal by the binary signal forming solid-state imaging device 20 will be described with reference to a timing chart shown in FIG. In addition, as shown in FIG.
The periods t10 to t17 show the readout operation of the pixels 1 in the first row, and the periods t20 to t27 show the readout operations of the pixels 1 in the second row.

As shown in FIG. 5, before the period t10,
The driving pulses φTG1 and φTG2, the driving pulse φRG and the driving pulse φR are held at a high level, and the driving pulse φR
D1 and φRD2 are held at a low level (voltage level VRS). In addition, other drive pulses φS, drive pulse φTO, drive pulses φH1, φH2, drive pulse φR
SH are all held at low level.

Then, when the period t10 is reached, the drive pulse φRG is inverted to a low level, and the reset MOS transistor (p-channel type) QP in the pixel 1 is turned on. Further, the drive pulses φRD1 and φRD2 are both at the voltage level VRS (low level), and the voltage VRS is supplied via the reset transistor QP which is turned on.
RS is the gate of each amplifying transistor QA (control region)
It is transmitted to.

At this time, drive pulses φTG1, φTG
2 are both held at a high level, so that the transfer MO
The S transistor (p-channel type) QT is off, and in each photodiode PD, a charge (signal charge) corresponding to the incident light is generated and accumulated. Then
Although the gate (control region) of the amplifying transistor QA is biased to the voltage level VRS, its output is at the low level at this time (initial state) as in the first embodiment, These amplifying transistors QA are turned off as a whole.

Since the driving pulse φR is kept at the high level, the switching MOS transistor (p-channel type) QRB is off. Further, since the driving pulse φS is kept at the low level, the switching MOS transistor (n-channel type)
QSB is also off. At this time, the driving pulse φ
Since TO is held at a low level, the switch M
The OS transistors QO1 and QO2 are off.

Next, when the period t11 is reached, the driving pulse φ
RD1 is set to the reference voltage level VRF, and the drive pulse φR
Is inverted to a low level. Then, the driving pulse φ
The reference voltage level VRF of RD1 is supplied to the gate (control region) of the amplifying transistor QA of the pixel 1 via the reset MOS transistor QP which is already turned on, and the gate (control region) of the amplifying transistor QA ) Is biased to the reference voltage level VRF.

It should be noted that each amplifying transistor QA in the second row
Means that the drive pulse φRD2 is at a low level (voltage level VR
S) is kept off (not selected) because it remains.
Also, during this period t11, as described above, the drive pulse φ
Since R goes low, the switching MOS transistor (p-channel type) QRB is turned on, and the gate and drain of the biasing MOS transistor QB are connected.

At this time, the drain current of the amplifying transistor QA in the first row and the bias MOS transistor Q
B so that the drain current of B becomes IB (constant current source 17
a, 17b), the amplifying transistor QA
, And the potential of the gate of the bias MOS transistor QB are automatically set. Further, the potential of the gate of the bias MOS transistor QB at this time is held between the bias storage capacitors CRB.

Next, when the period t12 is reached, the driving pulse φ
RD1 is returned to the low level (voltage level VRS), and the drive pulse φRG and the drive pulse φR are inverted to the high level. When the drive pulse φRG goes high, the reset MOS transistor QP in the pixel 1 is turned off, and the gate (control region) of the first row amplifying transistor QA is in a floating state. , The gate voltage remains biased to the reference voltage level VRF.

In the period t12, since the driving pulse φR is at the high level as described above, the switching MOS transistor (p-channel type) QRB is turned off, and the gate of the biasing MOS transistor QB is in a floating state. At this time, the bias storage capacitor C
By the RB, the voltage of the gate of the bias MOS transistor QB is held at the bias level set in the period t11 (the bias level at which the drain current of the bias MOS transistor QB becomes IB).

At time t13, drive pulse φRG is again inverted to low level. Due to the inversion of the drive pulse φRG, the reset MOS transistor QP in the pixel 1 is turned on again, and the voltage of the gate (control electrode) of the amplifying transistor QA of the pixel 1 in the first row is again changed to the voltage level VRS (drive (The level of the pulse φRD1).

When the next period t14 is reached, the drive pulse φRD1 is changed to the voltage level VRD (= read level <
VRF). This voltage level VRD is supplied to the gate (control region) of each amplifying transistor QA in the first row via the reset switch MOS transistor QP in the pixel 1 which has been turned on, and the amplifying transistor QA Is held at the read level VRD.

At time t15, drive pulse φTG1
Is inverted to the low level, the drive pulse φRD1 is returned to the voltage level VRS (low level), and the drive pulse φRG is inverted to the high level. The drive pulse φR
When G goes high, the reset switch MOS transistor QP in the pixel 1 is turned off.

On the other hand, when the drive pulse φTG1 goes low, the transfer MO of each pixel 1 in the first row is changed.
The S transistor QT is turned on, and each pixel 1 in the first row is turned on.
The signal charge generated and accumulated in the photodiode PD is transferred to the gate (control region) of the amplification transistor QA in the first row. The amplifying transistor QA having received the signal charge at its gate generates an electric signal corresponding to the signal charge at its source and outputs the electric signal (voltage signal) to the vertical readout lines 22a and 22b.

Then, during the period t16, the drive pulse φTG1, the drive pulse φS, and the drive pulse φTO are inverted to the high level. When the drive pulse φTG1 goes high, the transfer MOS transistor (p-channel type) QT in the first row is turned off, and the transfer of the signal charge from the pixel 1 ends.

At this time, due to the parasitic capacitance of the gate, the state is maintained while the voltage of the gate of the amplifying transistor QA is increased (VS described later) by the charge transferred from the photodiode PD. In addition, the above driving pulse φ
When S goes high, the switching MOS transistor QSB is turned on, and the drive pulse φTO
Becomes high level, the switching MOS transistors QO1 and QO2 are turned on.

By the way, when the gate potential of the amplifying transistor QA is at the reference level VRF before the period t16 (period t11), the drain current of the amplifying transistor QA and the bias MOS transistor QB When the drain current is IB (constant current source 17a,
17b) is held at the gate of the bias MOS transistor QB.

Therefore, during this period t16, when the gate potential of the amplifying transistor QA rises according to the signal charge from the photodiode PD and the gate potential of the amplifying transistor QA becomes higher than VRF, the drain of the amplifying transistor QA The current and the drain current of the bias MOS transistor QB temporarily become larger than IB (the current value flowing through the constant current sources 17a and 17b).

When the potential of the gate of the amplifying transistor QA becomes lower than VRF, the drain current of the amplifying transistor QA and the drain current of the bias MOS transistor QB temporarily become IB (constant current sources 17a and 17B).
b). Here, assuming that the gate potential of the amplifying transistor QA after the charge corresponding to the incident light is transferred to the gate (control region) of the amplifying transistor QA is VGS, this potential VGS is expressed by the following equation (5).
It is represented by

VGS = VRD + VS (5) Here, VS is a value represented by (charge / gate capacitance according to incident light). Incidentally, the reference voltage level VRF supplied to the gate of the amplifying transistor QA via the reset switch MOS transistor QP during the period t11 can be set arbitrarily (provided that it is higher than the read voltage VRD).

If the reference voltage level VRF is forcibly set to a desired value VGB (= VRF = VRD + VREF), the drain current of the amplifying transistor QA becomes I
If B, the value VGS of the gate voltage of the amplifying transistor QA becomes a value represented by the following equation (6). VGS-VGB = (VRD + VS)-(VRD + VREF) = VS-VREF (6) Assuming that the drain current of the amplifying transistor QA and the drain current of the bias MOS transistor QB are ID, the above-described voltage value VGS is a voltage value. When the voltage is greater than VGB (when VS is greater than VREF), the value of the drain current (indicated by ID) is determined by the constant current source 17a,
The current value temporarily becomes larger than the current value IB flowing through 17b.

At this time, due to the operation of the constant current sources 17a and 17b, the difference between the current ID and the current IB (ID
-IB) is the switch M which is turned on at this time.
The current flows between the drain and source of the current detection MOS transistor QX via the OS transistor QSB. Here, since the current detection MOS transistor QX and the binarized output MOS transistor QY form a current mirror circuit, a drain current is supplied to the binarized output MOS transistor QY. .

At this time, the drain potential of the binarized output MOS transistor QY falls (low level), and the output of the inverter AX goes to the power supply voltage level (high level). Conversely, when the value VGS is smaller than the value VGB (the value V
When S is smaller than the value VREF), the current value ID becomes smaller than IB, so that no current flows between the source and the drain of the current detecting MOS transistor QX. Therefore, both the gate of the current detection MOS transistor QX and the gate potential of the binarized output MOS transistor QY are reduced, and the binarized output MOS transistor QY is turned off.

At this time, the drain potential rises (high level), and the output of inverter AX goes to the ground level (low level). As described above, in the solid-state imaging device 20 for forming a binarized signal according to the present embodiment, the electric signal from the pixel 1 is converted by the binarizing circuit 27 into a binary signal with the reference voltage level VRF (reference voltage VREF) as the threshold level. It will be valued.

The drain current ID of the amplifying transistor QA depends on the value of the gate-source voltage VT, and the value of the gate-source voltage VT varies for each amplifying transistor QA. Factor) is known. As described above, when the gate of the amplifying transistor QA is biased so that the current has a constant value (IB), when the signal is converted into a binary signal, the amplifying transistor QA of each pixel 1 is converted. It is possible to remove the influence of the fixed pattern noise on the binarized signal due to the variation in each case.

The binarized signal output from the inverter AX is supplied to the switching MOS transistors QO1 and QO2 which are turned on during the period t16.
The capacitors CO1, CO2 for storing the digitized signal are charged. Then, during the period t17, the drive pulse φS and the drive pulse φTO are inverted to low level. When the drive pulse φTO goes low, the switching MOS transistors QO1 and QO2 are both turned off, and the binarized signal storage capacitors CO1 and CO2 are in a floating state, and the binarized signal is converted to a binarized signal. It is held in the storage capacitors CO1 and CO2. Further, when the drive pulse φS goes low, the switching MOS transistor QSB is turned off.

Next, when the period t17 is reached, as in the first embodiment, the drive pulse φH1 from the horizontal scanning circuit 13 rises to a high level for a certain period of time, and is thereafter held at a low level. As for the drive pulse φH2, after the drive pulse φH1 is held at a low level, the drive pulse φH1 is raised to a high level for a predetermined period at predetermined intervals, and then held at a low level.

Further, the drive pulse φRSH is raised to a high level for a certain period of time after the drive pulse φH1 falls to a low level and before the drive φH2 rises, and is thereafter kept at a low level. After the drive pulse φH2 falls to a low level, the drive pulse φH2 rises to a high level again for a certain period of time, and is thereafter kept at a low level.

When the driving pulse φH1 is switched to the high level, the binarized signal held in the binarized signal storage capacitor CO1 is read out to the horizontal readout line 12 and output via the output buffer amplifier 15. And is sequentially output to the output terminal VO. Subsequently, when the reset switch MOS transistor QRSH is turned on by the high-level switching of the drive pulse φRSH, the horizontal read line 12 is reset (initialized). This is because when the electric signal (voltage signal) is read out to the horizontal read line 12, a part of the electric signal (voltage signal) may be held by the parasitic capacitance due to the parasitic capacitance of the horizontal read line 12. Therefore, this operation is for resetting the electric signal remaining on the horizontal read line 12.

Then, by the high level switching of the drive pulse φH2, the binarized signal held in the binarized signal storage capacitor CO2 is read out to the horizontal readout line 12, and is output via the output buffer amplifier 15. Are sequentially output to the output terminal VO. Finally, when the drive pulse φRSH switches to a high level, the reset switch MOS transistor QRSH is turned on, and the horizontal read line 12 is reset (initialized) again.

The voltage signal read to the horizontal read line 12 takes a long time to reach a steady state due to the effect of the parasitic capacitance of the read line. Since the voltage signal appearing on the line 12 has already been converted to a binary signal, it is possible to determine whether the binary signal indicates a high level or a low level without reaching a steady state. The speed of the read operation is increased.

At the end of the period t17 (until the period t20), the drive pulse φRG is inverted to a low level, and the reset switch MOS transistor QP in the pixel 1 is turned on. The reading operation of the pixels in the first row in the periods t10 to t17 described above is performed in the subsequent period t2.
From 0 to t27, the same process is repeated for the pixels in the second row.

(Third Embodiment) Next, a solid-state imaging device 30 for forming a binary signal according to a third embodiment of the present invention will be described.
This will be described with reference to FIGS. In the solid-state imaging device 30 for forming a binarized signal according to the third embodiment, the binarization circuit 37 is configured such that the binarization circuit 37 does not pass through the output signal charge storage means (the capacitors CO1 and CO2 of the first embodiment). Switching MOS transistors (n-channel type) QH11, QH2
The difference from the solid-state imaging device 10 for forming a binarized signal of the above-described first embodiment is that the solid-state imaging device 10 is connected to the horizontal readout line 12 via only 1.

Accordingly, the solid-state imaging device 3 for forming a binary signal
In FIG. 0, the same parts as those of the solid-state imaging device 10 for forming a binarized signal of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. The operation of generating the binarized signal by the binarized signal forming solid-state imaging device 30 will be described with reference to the timing chart of FIG.

The solid-state imaging device 3 for forming a binary signal
The operation at 0 is different from the operation of the solid-state imaging device 10 for forming a binarized signal of the first embodiment only in the operations in the period t17 and the period t27. Therefore, the period t10 to t
The operation in 16 (periods t20 to t26) is the same as that of the first embodiment, and a detailed description thereof will be omitted. Also, in FIG. 7, the period t10 to t17 corresponds to the pixel 1 in the first row.
During the period t20 to t27.
The read operation of the pixel 1 in the second row is shown.

Hereinafter, the operation in the period t17 of FIG. 7 will be described. As in the case of the first embodiment, the period t
By 17 (at the end of the period t16), the electric signal corresponding to the incident light from the pixel 1 is compared with the reference level VRF (reference voltage VREF) by the operation of the binarization circuit 37, and the binary level has already been obtained. (The output of the voltage comparator AC).

Then, when the period t17 is reached, the drive pulse φH1 from the horizontal scanning circuit 13 rises to a high level for a certain period, and is thereafter kept at a low level. As for the drive pulse φH2, after the drive pulse φH1 is held at a low level, the drive pulse φH1 is raised to a high level for a predetermined period at predetermined intervals, and then held at a low level.

At this time, the binarized signal from the binarizing circuit 37 is sequentially read out to the horizontal read line 12 for each column,
Thereafter, the signals are sequentially output to the output terminal VO via the output buffer amplifier 15. It should be noted that the voltage signal read out to the horizontal read line 12 due to the influence of the parasitic capacitance of the read line takes time until the waveform is distorted and reaches a steady state. Has already been converted to a binary signal, so that it is possible to determine whether the binary signal indicates a high level or a low level without reaching a steady state,
The speed of the read operation is increased.

Further, since it is not necessary to discharge the electric charge on the horizontal read line 12, the reading speed can be further increased. (Fourth Embodiment) Next, a binary signal forming solid-state imaging device 40 according to a fourth embodiment will be described with reference to FIGS.

The solid-state imaging device 40 for forming a binary signal
Means that the binarization circuit 47 is an output signal charge storage means (second
Without the capacitors CO1, CO2) of the embodiment
Switching MOS transistor (n-channel type) QH1
The difference from the solid-state imaging device 20 for forming a binarized signal of the above-described second embodiment is that it is connected to the horizontal readout line 12 via only the QH21 and QH21.

Therefore, the solid-state imaging device 4 for forming a binary signal
In FIG. 0, the same components as those of the solid-state imaging device 20 for forming a binary signal according to the second embodiment are denoted by the same reference numerals, and description thereof will be omitted. The operation of generating the binarized signal by the binarized signal forming solid-state imaging device 40 will be described with reference to the timing chart of FIG. The operation of the solid-state imaging device 40 for forming a binarized signal is performed during a period t17.
Only the operation in the period t27 is different from that of the second embodiment. Therefore, the period t10 to t16 (the period t
Operations 20 to 26) are the same as in the first embodiment, and a detailed description thereof will be omitted. Also, in FIG.
The periods t10 to t17 show the readout operation of the pixels 1 in the first row, and the periods t20 to t27 show the readout operations of the pixels 1 in the second row.

Hereinafter, only the operation in the period t17 of FIG. 9 will be described. As in the case of the second embodiment, the period t1
7 (at the end of the period t16), the electric signal corresponding to the incident light from the pixel 1 is compared with the reference level VRF (reference voltage VREF) by the operation of the binarization circuit 47, and the binary level has already been obtained. (The output of the voltage comparator AC).

By the time t17, the drive pulse φS has already been inverted to the high level in the period 16 and its state is maintained, and the switching MOS transistor (n
The (channel type) QSB is turned on, and the on state is maintained in the period t17.

During the period t17, the driving pulse φH1 from the horizontal scanning circuit 13 rises to the high level for a certain period of time, and then is held at the low level. Subsequently, the driving pulse φH2 is changed to the low level. After that, the signal is raised to a high level for a predetermined period at a predetermined interval, and is thereafter kept at a low level. At this time, the binarized signal from the binarizing circuit 47 is sequentially read out to the horizontal readout line 12 for each column, and then sequentially output to the output terminal VO via the output buffer amplifier 15.

It should be noted that the electric signal (voltage signal) read out to the horizontal read line 12 takes a long time to reach a steady state due to the effect of the parasitic capacitance of the read line. Since the electric signal (voltage signal) appearing on the readout line 12 has already been converted into a binary signal, it is determined whether the binary signal indicates a high level or a low level without reaching a steady state. And the speed of the read operation can be increased.

Further, since it is not necessary to discharge the electric charge on the horizontal read line 12, the reading speed can be further increased. In the above-described first to fourth embodiments, the pixel 1 in which the control region (gate) of the amplification transistor QA is controlled by the parasitic capacitance of the gate has been described as an example. Of course, the present invention can be similarly applied to a pixel in which a voltage signal is supplied to a region by capacitive coupling to obtain an electric signal corresponding to incident light.

In the first to fourth embodiments, the case where the junction field effect transistor (JFET) is used as the amplifying transistor QA of the pixel has been described as an example. A MOS transistor, a bipolar transistor, or the like may be used. In this case,
The output voltage and current of the drain or collector, the source or the emitter, etc. may be controlled by the voltage supplied to the gate (the control region) of the MOS transistor or the base of the bipolar transistor. Further, these may be used together to form a pixel.

Further, in the first to fourth embodiments, the case where the pixels 1 are arranged in a two-dimensional matrix has been described. Can be.

[0157]

As described in detail above, according to the solid-state imaging device for forming a binarized signal according to any one of the first to tenth aspects, the binarizing means is provided for each column, and the binarized means is provided for incident light. Accordingly, a binary signal is obtained by comparing the electric signal output from each pixel with a predetermined reference signal, and is then transferred to the horizontal read line. Therefore, even if the noise caused by the noise appears on the signal on the horizontal readout line, since the signal has already been binarized, the influence of the noise on the signal processing can be reduced. or,
Since it is possible to quickly determine whether the binarized signal is at the high level or the low level, the signal processing is speeded up.

In the solid-state imaging device for forming a binarized signal according to any one of the first to tenth aspects, since the binarization processing is performed in the device, the dynamic range is not limited by the peripheral circuit. There is also an effect that the dynamic range of the solid-state imaging device can be used as it is in the binarization processing. According to the solid-state imaging device for forming a binarized signal according to any one of the first to tenth aspects, the binarizing means is provided outside the pixel. It can output a digitized signal and does not lower the aperture ratio or resolution of the pixel.

Further, according to the third to tenth aspects,
According to the solid-state imaging device for forming a coded signal, the path from which the electric signal corresponding to the incident light is obtained from the light detection unit is the same as the path from which the reference signal is obtained. The S / N ratio can be increased by eliminating the influence of the subsequent variation of the peripheral circuit elements in each column (variation in manufacturing of capacitors, switching MOS transistors, etc.). Further, since the removal of the fixed pattern noise caused by the dark current, which has been conventionally performed, is performed at the time of generation of the reference signal, the differential amplifier conventionally required for removing the fixed pattern noise is required. It becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram illustrating a schematic configuration of a solid-state imaging device for forming a binarized signal according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the solid-state imaging device for forming a binary signal.

FIG. 3 is a diagram showing a device structure of a pixel 1 of the solid-state imaging device 10 for forming a binary signal.

FIG. 4 is a schematic circuit diagram illustrating a schematic configuration of a binary signal forming solid-state imaging device 20 according to a second embodiment;

FIG. 5 is a timing chart illustrating the operation of the solid-state imaging device 20 for forming a binary signal.

FIG. 6 is a schematic circuit diagram illustrating a schematic configuration of a binary signal forming solid-state imaging device 30 according to a third embodiment.

FIG. 7 is a timing chart illustrating the operation of the solid-state imaging device 30 for forming a binary signal.

FIG. 8 is a schematic circuit diagram illustrating a schematic configuration of a binary signal forming solid-state imaging device 40 according to a fourth embodiment.

FIG. 9 is a timing chart illustrating an operation of the solid-state imaging device 40 for forming a binary signal.

FIG. 10 shows a conventional solid-state imaging device 100 for forming a binary signal.
1 is a schematic circuit diagram showing a schematic configuration of FIG.

FIG. 11 shows a conventional solid-state imaging device 100 for forming a binary signal.
6 is a timing chart for explaining the operation of FIG.

FIG. 12 is a block diagram of a conventional image processing apparatus 120 provided with a binarizing unit outside a solid-state imaging device.

[Explanation of symbols]

1 pixel 2a, 2b vertical readout line 6 vertical scanning circuit (vertical scanning means) 7, 27, 37, 47 binarization circuit (binarization means) 12 horizontal readout line 13 horizontal scanning circuit (horizontal scanning means) 15 output buffer Amplifiers 17a, 17b Constant current source (current source) PD Photodiode (photodetector, photoelectric conversion element) QA Amplifying transistor (amplifying means) QT Transfer MOS transistor (first switch means) QP Reset MOS transistor (first 2) QS, QR switching MOS transistor (transfer switching means) CS output signal storage capacitor (first storage means; charge storage means) CR reference signal storage capacitor (second storage means; charge storage means) ) AC voltage comparator (comparing means) QRSV1, QRSV2 MOS transistor for reset switch Star QRSH reset switch MOS transistor QB bias MOS transistor (biasing means;
Constant current transistor) QRB switch MOS transistor (bias storage means; sample and hold means) QSB switch MOS transistor (switch means) CRB Bias storage capacitor (bias storage means; bias charge storage means) QX Current detection MOS transistor (Current Detecting Means) QY Binary Output MOS Transistor CS Load Current Source AX Inverter QO1, QO2 Switch MOS Transistor (First
QH1, QH2 MOS transistor for horizontal readout switch (second switching means)

Claims (10)

[Claims] 1. A plurality of pixels arranged in a matrix and outputting signal charges generated by a photodetector through an amplifying means, and a plurality of vertical read lines provided for each column of the plurality of pixels. Vertical scanning means for selecting a specific row of the plurality of pixels and transferring an electrical signal corresponding to a signal charge from a photodetector of the pixel to the vertical readout line at a desired timing; An electric signal corresponding to the signal charge output from the pixel at the desired timing and a reference signal output via the amplifying unit at a timing different from the desired timing, provided on each of the readout lines. A binarizing unit for comparing and outputting a binarized signal; and a horizontal scanning unit for sequentially horizontally scanning the plurality of vertical read lines and transferring the binarized signal to the horizontal read line. Binary signal for forming a solid-state imaging device according to claim and. 2. The photodetector comprises a photoelectric conversion element for generating a signal charge according to incident light, and the amplifying means selects a signal charge from the photoelectric conversion element for a control region of the amplifying means. And a second switch for selectively supplying a desired potential from outside the pixel to a control region of the amplifying unit. The solid-state imaging device for forming a binarized signal according to claim 1. 3. The binarizing unit includes: a first storage unit configured to store an electric signal corresponding to the signal charge generated by the photoelectric conversion element; A second storage unit for storing a corresponding reference signal, and comparing the electric signal stored in the first storage unit with the reference signal stored in the second storage unit.
3. The solid-state imaging device for forming a binarized signal according to claim 2, comprising a comparing unit that outputs a binarized signal. 4. The first storage unit is a charge storage unit that stores a charge corresponding to the electric signal output from the pixel, and the second storage unit is configured to store the charge output from the pixel. The solid-state imaging device for forming a binary signal according to claim 3, wherein the solid-state imaging device is a charge storage unit that stores a charge corresponding to a reference signal. 5. A transfer switching means for selectively transferring the electric signal or the reference signal output from the pixel is provided between the pixel and the two charge storage means. The solid-state imaging device for forming a binary signal according to claim 4, wherein: 6. The amplifying means is a junction field-effect transistor, and the gate of the junction field-effect transistor has the signal charge generated by the photoelectric conversion element and the desired signal from outside the pixel. 5. The solid-state imaging device for forming a binary signal according to claim 4, wherein the potential is selectively supplied. 7. The vertical read-out unit according to claim 6, wherein the binarizing unit is configured to: a current source; and the vertical readout so that the reference signal corresponding to the desired potential supplied from outside the pixel is equal to the current of the current source. Bias means for biasing a line potential; bias storage means for storing a bias state of the bias means; an electric signal corresponding to the signal charge generated by the photoelectric conversion element; and a current of the current source. Current detection means for detecting a difference between the electric signal and the electric signal corresponding to the signal charge generated by the photoelectric conversion element, and a current difference between the current of the current source and the current detection means for inputting the current to the current detection means. 3. The solid-state imaging device for forming a binarized signal according to claim 2, wherein said solid-state imaging device is constituted by switching means. 8. The bias means comprises a constant current transistor having a main current path connected between the vertical read line and the current source, and the bias storage means controls the constant current transistor. An electrode is provided between a terminal of the main current path of the constant current transistor and a terminal connected to the current source, for sampling a bias state of the constant current transistor, and thereafter holding the bias state. Sample / hold switching means, connected to the control electrode of the constant current transistor,
7. The solid-state imaging device for forming a binarized signal according to claim 6, further comprising: bias charge storage means for holding a bias of said constant current transistor. 9. The apparatus according to claim 1, wherein the comparing means is connected to an output signal storing means for storing the binarized signal from the comparing means. Solid-state imaging device for forming a binary signal. 10. The solid-state imaging device according to claim 1, wherein the photoelectric conversion element is a buried photodiode.