JPH10223930A - Semiconductor light emitting element - Google Patents

Semiconductor light emitting element

Info

Publication number
JPH10223930A
JPH10223930A JP2138897A JP2138897A JPH10223930A JP H10223930 A JPH10223930 A JP H10223930A JP 2138897 A JP2138897 A JP 2138897A JP 2138897 A JP2138897 A JP 2138897A JP H10223930 A JPH10223930 A JP H10223930A
Authority
JP
Japan
Prior art keywords
semiconductor
electrode
light emitting
layer
side electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2138897A
Other languages
Japanese (ja)
Other versions
JP3752339B2 (en
Inventor
Yukio Shakuda
幸男 尺田
Shunji Nakada
俊次 中田
Masayuki Sonobe
雅之 園部
Takeshi Tsutsui
毅 筒井
Norikazu Ito
範和 伊藤
Atsushi Ichihara
淳 市原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP02138897A priority Critical patent/JP3752339B2/en
Publication of JPH10223930A publication Critical patent/JPH10223930A/en
Application granted granted Critical
Publication of JP3752339B2 publication Critical patent/JP3752339B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body

Landscapes

  • Led Device Packages (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To make sure the electrical connections between p- and n-side electrodes on the same surface side of a laminated semiconductor section formed on a substrate to form a light emitting layer and other leads by forming the p- and n-side electrodes to substantially equal heights. SOLUTION: After a laminated semiconductor section 10 is formed as a light emitting layer on a single-crystal substrate 1 by successively laminating semiconductor layers 3-5 upon another, a p-side electrode 8 is formed in a state where the electrode 8 is electrically connected to a p-type layer 4 on the surface side of the laminated section 10. Then an n-side electrode 9 is formed in a state where the electrode 9 is electrically connected to an n-type layer 3 exposed by removing part of the laminated section 10. At the time of forming the electrode 9, the part 10a of the laminated section 10 is left at the forming location of the electrode 9 without etching the part 10a and the electrode 9 is formed continuously from the part 10a and the n-type layer 3 exposed around the part 10a. Therefore, the part 9a of the n-side electrode 9 on the part 10a of the laminated section 10 is formed at nearly the same height as that of the p-side electrode 8.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は基板上に発光層を形
成すべく半導体層が積層され、その半導体層が積層され
た同一面側にp側およびn側の両電極が設けられる発光
ダイオードやレーザダイオードなどの半導体発光素子に
関する。さらに詳しくは、その両電極が基板から実質的
に同じ高さに形成される半導体発光素子に関する。
The present invention relates to a light emitting diode in which a semiconductor layer is laminated on a substrate to form a light emitting layer, and both p-side and n-side electrodes are provided on the same surface on which the semiconductor layer is laminated. The present invention relates to a semiconductor light emitting device such as a laser diode. More specifically, the present invention relates to a semiconductor light emitting device in which both electrodes are formed at substantially the same height from a substrate.

【0002】[0002]

【従来の技術】たとえば青色系(紫外線から黄色)の発
光ダイオード(以下、LEDという)は、図4にそのL
EDチップの一例の概略図が示されるように、サファイ
アからなる電気的絶縁性の基板上にチッ化ガリウム系化
合物半導体層が積層されて形成される。すなわち、サフ
ァイア基板21上にたとえばn形のGaNがエピタキシ
ャル成長されたn形層(クラッド層)23と、バンドギ
ャップエネルギーがクラッド層のそれよりも小さくなる
材料、たとえばInGaN系(InとGaの比率が種々
変わり得ることを意味する、以下同じ)化合物半導体か
らなる活性層24と、p形のGaNからなるp形層(ク
ラッド層)25とからなり、その表面に図示しないNi
-Auの合金層からなる電流拡散層を介してp側(上
部)電極28が設けられ、積層された半導体層の一部が
エッチングされて露出するn形層23の表面にn側(下
部)電極29が設けられることにより形成されている。
2. Description of the Related Art For example, a light emitting diode (hereinafter, referred to as an LED) of a blue type (from ultraviolet rays to yellow) is shown in FIG.
As shown in a schematic diagram of an example of the ED chip, a gallium nitride-based compound semiconductor layer is formed by lamination on an electrically insulating substrate made of sapphire. That is, an n-type layer (cladding layer) 23 in which, for example, n-type GaN is epitaxially grown on a sapphire substrate 21 and a material whose band gap energy is smaller than that of the cladding layer, for example, an InGaN-based material (the ratio of In to Ga is lower). An active layer 24 made of a compound semiconductor and a p-type layer (cladding layer) 25 made of p-type GaN.
A p-side (upper) electrode 28 is provided via a current diffusion layer made of an -Au alloy layer, and a part of the laminated semiconductor layer is etched and exposed to the n-side (lower) surface of the n-type layer 23. It is formed by providing the electrode 29.

【0003】この構造のLEDチップがリードの先端な
どにダイボンディングされ、2本のリードとp側および
n側の電極が金線などのワイヤボンディングにより接続
されたり、2本のリード上にそれぞれp側およびn側の
電極が別々に接続されるようにLEDチップを裏向き
(フェースダウン)にしてボンディングされ、その周囲
が樹脂でモールドされてそのリードと反対側から発光す
る発光素子ランプにされたり、両端に端子電極が設けら
れた基板上にLEDチップがボンディングされて各電極
がワイヤボンディングにより端子電極と接続されるチッ
プ型発光素子として用いられる。
[0003] An LED chip having this structure is die-bonded to the tip of a lead or the like, and two leads and p-side and n-side electrodes are connected by wire bonding such as a gold wire. The LED chip is bonded face down so that the electrodes on the n-side and n-side are connected separately, and the periphery is molded with resin to form a light-emitting element lamp that emits light from the side opposite to the lead. An LED chip is bonded on a substrate provided with terminal electrodes at both ends, and each electrode is used as a chip-type light emitting element in which each electrode is connected to the terminal electrode by wire bonding.

【0004】一方、電流注入領域をメサ形にしてストラ
イプ状に制限するメサストライプ型半導体レーザで、前
述のように基板に電気的絶縁性基板が用いられる半導体
レーザでは、図5に示されるようにフェースダウンでダ
イボンディングされ、両電極38、39がクリームハン
ダ、In、Au-Snなどの低融点金属40により同時
にマウント台41の電極端子(図示せず)に電気的に接
続される。なお、図5において、31はサファイア基
板、33はn形クラッド層、34は活性層、35はp形
クラッド層をそれぞれ示す。
On the other hand, in a mesa stripe type semiconductor laser in which a current injection region is formed in a mesa shape and limited in a stripe shape, and as described above, a semiconductor laser using an electrically insulating substrate is used as shown in FIG. Die bonding is performed face down, and both electrodes 38 and 39 are simultaneously electrically connected to electrode terminals (not shown) of the mount table 41 by a low melting point metal 40 such as cream solder, In, or Au-Sn. In FIG. 5, 31 denotes a sapphire substrate, 33 denotes an n-type cladding layer, 34 denotes an active layer, and 35 denotes a p-type cladding layer.

【0005】[0005]

【発明が解決しようとする課題】前述の青色系の半導体
発光素子のように、絶縁性の基板上に半導体層が積層さ
れる半導体発光素子は、p側電極もn側電極も同一面側
に設けられることが多い。このように、同一面側に両電
極が設けられる半導体発光素子では、その両電極とリー
ドもしくはチップ型素子の端子電極などとの電気的接続
がワイヤボンディングによりなされる。しかし、前述の
ように、同一面側に両電極が設けられる半導体発光素子
では、一方の電極は積層された半導体層の上層の半導体
層上に設けられ、他方の電極が積層された半導体層の一
部がエッチングなどにより除去されて露出する下層の半
導体層に設けられる。そのため、両電極の高さが基板の
面から同じ高さにならない。この両電極の高さが同じで
ないと、ワイヤボンディングのときにp側電極とn側電
極とで同じ圧力でボンディングをすることができない。
そのため、ボンディング不良が出たり、ボンディングの
信頼性が低下するという問題がある。一方、両電極によ
りボンディングの条件を変えると、ボンディング工程が
非常に複雑になる。
In a semiconductor light emitting device in which a semiconductor layer is laminated on an insulating substrate like the above-mentioned blue semiconductor light emitting device, both the p-side electrode and the n-side electrode are on the same surface side. Often provided. As described above, in a semiconductor light emitting device in which both electrodes are provided on the same surface side, an electrical connection between the two electrodes and a lead or a terminal electrode of a chip type device is made by wire bonding. However, as described above, in a semiconductor light-emitting element in which both electrodes are provided on the same surface side, one electrode is provided on the semiconductor layer above the stacked semiconductor layer, and the other electrode is provided on the semiconductor layer on which the other electrode is stacked. A portion is provided in a lower semiconductor layer which is removed by etching or the like and exposed. Therefore, the height of both electrodes does not become the same height from the surface of the substrate. If the heights of the two electrodes are not the same, bonding cannot be performed at the same pressure between the p-side electrode and the n-side electrode during wire bonding.
For this reason, there is a problem that bonding failure occurs and bonding reliability decreases. On the other hand, if the bonding conditions are changed by both electrodes, the bonding process becomes very complicated.

【0006】また、LEDチップを裏向きにしてフェー
スダウンで両電極を直接リードの先端にボンディングを
する場合や、レーザダイオートチップをマウント台上に
フェースダウンでダイボンディングをする場合、LED
チップやレーザダイオードチップの電極部の高さに段差
があるとボンディングをしにくいと共に傾きやすいとい
う問題がある。とくにレーザダイオードチップの場合、
傾いてダイボンディングされると、ビームが傾き所望の
特性が得られないという問題がある。さらに、メサ形状
に残されたストライプ部分はその幅が数μm程度と非常
に細く、その部分にかかる力が大きくなり、劣化しやす
い。とくに、ダイボンディングの際に低融点金属の表面
にできる酸化膜を擦って除去するスクラブを行いながら
ダイボンディングを行うが、幅の狭いストライプ部に大
きな力がかかるため、ストライプ部分を劣化させやす
い。
In the case where the two electrodes are directly bonded to the tips of the leads face down with the LED chip facing down, or when the laser die auto chip is die-bonded face down on a mount base,
If there is a step in the height of the electrode portion of the chip or the laser diode chip, there is a problem that bonding is difficult and the chip is easily inclined. Especially for laser diode chips
When die bonding is performed with a tilt, there is a problem that the beam is tilted and desired characteristics cannot be obtained. Further, the stripe portion left in the mesa shape has a very small width of about several μm, and the force applied to the portion is large, so that the stripe portion is easily deteriorated. In particular, die bonding is performed while scrubbing to remove an oxide film formed on the surface of the low melting point metal during die bonding. However, since a large force is applied to a narrow stripe portion, the stripe portion is easily deteriorated.

【0007】本発明は、このような問題を解決するため
になされたもので、積層された半導体層の一部をエッチ
ングなどにより除去して、同一面側にp側電極およびn
側電極が設けられる半導体発光素子においても、その電
極と他のリードなどとの電気的接続が確実になり、その
信頼性が向上する半導体発光素子を提供することを目的
とする。
The present invention has been made to solve such a problem, and a part of a stacked semiconductor layer is removed by etching or the like, and a p-side electrode and an n-side electrode are formed on the same surface.
It is another object of the present invention to provide a semiconductor light emitting device in which a side electrode is provided, the electrical connection between the electrode and another lead or the like is ensured, and the reliability is improved.

【0008】本発明の他の目的は、メサストライプ型の
半導体レーザをフェースダウンでダイボンディングをし
て製造する場合にも、メサストライプ部を劣化させた
り、傾きが生じてビーム特性を低下させない半導体レー
ザを提供することにある。
Another object of the present invention is to provide a semiconductor laser in which a mesa stripe portion is not deteriorated or tilted to lower beam characteristics even when a mesa stripe type semiconductor laser is manufactured by die bonding face down. It is to provide a laser.

【0009】[0009]

【課題を解決するための手段】本発明による半導体発光
素子は、基板と、該基板上に発光層を形成すべく積層さ
れる半導体積層部と、該半導体積層部の表面側の第1導
電形の半導体層に接続して設けられる第1の電極と、前
記半導体積層部の一部がエッチングにより除去されて露
出する第2導電形の半導体層に接続して設けられる第2
の電極とからなり、前記第1および第2の電極が、前記
基板からほぼ同じ高さになるように形成されている。
SUMMARY OF THE INVENTION A semiconductor light emitting device according to the present invention comprises a substrate, a semiconductor laminated portion laminated on the substrate to form a light emitting layer, and a first conductivity type on the surface side of the semiconductor laminated portion. A first electrode provided in connection with the first semiconductor layer, and a second electrode provided in connection with a second conductivity type semiconductor layer in which a part of the semiconductor laminated portion is removed by etching and exposed.
And the first and second electrodes are formed so as to have substantially the same height from the substrate.

【0010】ここにほぼ同じ高さとは、LEDチップや
レーザチップをフェースダウンでボンディングする場合
に、p側電極とn側電極とで極端な段差が生じないで、
通常の方法で傾きが生じないようにボンディングするこ
とができたり、p側電極とn側電極にワイヤボンディン
グをする場合に、極端にボンディングの圧力条件に差が
でない程度に段差が生じないことを意味する。また、第
1導電形および第2導電形とは、半導体の極性のn形お
よびp形のいずれか一方を第1導電形としたとき、他方
のp形またはn形が第2導電形であることを意味する。
Here, the substantially same height means that when an LED chip or a laser chip is bonded face down, there is no extreme step between the p-side electrode and the n-side electrode.
It is possible to perform bonding so as not to cause inclination by a normal method, and to perform wire bonding between the p-side electrode and the n-side electrode so that a step does not occur to such an extent that there is no extreme difference in bonding pressure conditions. means. Further, the first conductivity type and the second conductivity type are such that when one of the n-type and p-type of the polarity of the semiconductor is the first conductivity type, the other p-type or n-type is the second conductivity type. Means that.

【0011】この構造にすることにより、p側電極とn
側電極とがそれぞれリードの先端やサブマウントに直接
ボンディングされるようにLEDチップやレーザチップ
をフェースダウンでボンディングする場合でも段差がな
いため、傾きが生ぜず簡単にダイボンディングをするこ
とができる。また、ワイヤボンディングをする場合に
も、p側電極とn側電極とに同じ条件でボンディングを
することができるため、容易で、しかも確実にボンディ
ングをすることができる。
With this structure, the p-side electrode and the n-side electrode
Even when the LED chip or the laser chip is bonded face down so that the side electrodes are directly bonded to the tip of the lead or the submount, respectively, there is no step, so that the die bonding can be easily performed without inclination. Also, in the case of wire bonding, bonding can be performed to the p-side electrode and the n-side electrode under the same conditions, so that bonding can be performed easily and reliably.

【0012】前記第2の電極が、前記半導体積層部の一
部が除去されて露出する第2導電形の半導体層と、前記
半導体積層部がエッチングされないで残存する部分に連
続して形成されることにより、第2導電形半導体層と確
実に電気的に接続することができると共に、ワイヤボン
ディングなどがされる電極のパッド部分は積層された半
導体積層部上に形成され、第1の電極と同じ高さにする
ことができる。
The second electrode is formed continuously with a semiconductor layer of the second conductivity type, which is exposed by removing a part of the semiconductor laminated portion, and a portion where the semiconductor laminated portion remains without being etched. Thereby, the semiconductor device can be reliably electrically connected to the second conductivity type semiconductor layer, and the pad portion of the electrode to be subjected to wire bonding or the like is formed on the stacked semiconductor laminated portion and is the same as the first electrode. Can be height.

【0013】前記基板が電気的絶縁性基板であったり、
前記半導体積層部がチッ化ガリウム系化合物半導体であ
る場合にとくに効果が大きい。
The substrate is an electrically insulating substrate,
The effect is particularly large when the semiconductor laminated portion is a gallium nitride compound semiconductor.

【0014】ここにチッ化ガリウム系化合物半導体と
は、III 族元素のGaとV族元素のNとの化合物または
III 族元素のGaの一部がAl、Inなどの他のIII 族
元素と置換したものおよび/またはV族元素のNの一部
がP、Asなどの他のV族元素と置換した化合物からな
る半導体をいう。
The gallium nitride compound semiconductor is a compound of a group III element Ga and a group V element N or
Compounds in which part of the group III element Ga is replaced by another group III element such as Al or In and / or compound in which part of the group V element N is replaced by another group V element such as P or As. Semiconductor.

【0015】前記第1導電形の半導体層がストライプ状
に残存するようにメサエッチングがなされて半導体レー
ザが形成されている場合に、ボンディング時のストライ
プ部の劣化がなく、またビームの傾きがなく高性能の半
導体レーザが得られる。
In the case where the semiconductor laser is formed by mesa etching so that the semiconductor layer of the first conductivity type remains in a stripe shape, there is no deterioration of the stripe portion at the time of bonding and no inclination of the beam. A high-performance semiconductor laser can be obtained.

【0016】[0016]

【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体発光素子について説明をする。図1には、た
とえば青色系の発光に適するチッ化ガリウム系化合物半
導体が積層された本発明の半導体発光素子のチップの断
面および平面の説明図が示されている。
Next, a semiconductor light emitting device of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory view showing a cross section and a plan view of a chip of a semiconductor light emitting device of the present invention in which, for example, a gallium nitride compound semiconductor suitable for blue light emission is laminated.

【0017】本発明の半導体発光素子は、たとえば図1
に示されるように、サファイア(Al2 3 単結晶)な
どからなる基板1の表面に発光層を形成する半導体層3
〜5が積層されて半導体積層部10が形成され、その表
面側の第1導電形の半導体層(p形層5)に電気的に接
続してp側電極(第1の電極)8が形成されている。ま
た、半導体積層部10の一部が除去されて露出する第2
導電形の半導体層(n形層3)に電気的に接続してn側
電極(第2の電極)9が形成されている。本発明では、
n側電極9が、エッチングにより露出するn形層3だけ
に設けられるのではなくて、n側電極9の形成場所に半
導体積層部の一部10aをエッチングしないで残存さ
せ、その残存した半導体積層部の一部10aとその周囲
の露出するn形層3に連続してn側電極9が形成されて
いることに特徴がある。その結果、残存した半導体積層
部の一部10a上のn側電極の部分9aがワイヤボンデ
ィングなどの接続部とされることにより、p側電極8と
ほぼ同じ高さで形成される。
The semiconductor light emitting device of the present invention is, for example, shown in FIG.
As shown in FIG. 1, a semiconductor layer 3 for forming a light emitting layer on the surface of a substrate 1 made of sapphire (Al 2 O 3 single crystal) or the like.
5 are laminated to form a semiconductor laminated portion 10, which is electrically connected to a semiconductor layer (p-type layer 5) of the first conductivity type on the surface side to form a p-side electrode (first electrode) 8. Have been. In addition, the second exposed part of the semiconductor laminated portion 10 is removed.
An n-side electrode (second electrode) 9 is formed electrically connected to the conductive semiconductor layer (n-type layer 3). In the present invention,
The n-side electrode 9 is not provided only on the n-type layer 3 exposed by the etching, but a portion 10a of the semiconductor laminated portion is left without being etched at the place where the n-side electrode 9 is formed, and the remaining semiconductor laminated portion is formed. It is characterized in that an n-side electrode 9 is formed continuously from a portion 10a of the portion and the exposed n-type layer 3 around the portion 10a. As a result, the portion 9a of the n-side electrode on the remaining portion 10a of the semiconductor laminated portion is formed as a connection portion such as wire bonding, so that the portion 9a is formed at substantially the same height as the p-side electrode 8.

【0018】すなわち、n側電極9が形成される部分
は、図1に示されるように、半導体積層部10の一部が
エッチングされてn形層3が露出する。しかし、本発明
では、図1(b)に示されるように、そのn側電極9の
形成場所に半導体積層部の一部10aを残存させてお
き、その残存した半導体積層部の一部10aおよびその
周囲のn形層3にn側電極9が形成されている。この
際、n形層3と残存する半導体積層部の一部10aの上
面とでは段差があるが、その間で電極切れが生じても周
囲全体に亘って切れない限り問題はなく、ステップカバ
レジが問題になることはない。また、このn側電極9
は、従来のように、n形層3とオーミックコンタクト特
性の良好な、たとえばTiとAlの合金から形成され
る。残存する半導体積層部の一部10aの表面は、p形
層5のままの場合もあるが、p形層5とのオーミックコ
ンタクト特性を考慮する必要がなく、n形層3とのオー
ミックコンタクトのみを考えればよい。
That is, in the portion where the n-side electrode 9 is formed, as shown in FIG. 1, a part of the semiconductor lamination portion 10 is etched to expose the n-type layer 3. However, in the present invention, as shown in FIG. 1B, a portion 10a of the semiconductor laminated portion is left at the place where the n-side electrode 9 is formed, and the remaining portions 10a and 10a of the semiconductor laminated portion are formed. An n-side electrode 9 is formed on the surrounding n-type layer 3. At this time, there is a step between the n-type layer 3 and the upper surface of the remaining portion 10a of the semiconductor laminated portion, but there is no problem even if the electrode is cut between them, as long as the electrode is not cut over the entire periphery, and step coverage is a problem. Never be. The n-side electrode 9
Is formed of, for example, an alloy of Ti and Al having good ohmic contact characteristics with the n-type layer 3 as in the prior art. Although the surface of the remaining portion 10a of the semiconductor laminated portion may remain as the p-type layer 5, there is no need to consider the ohmic contact characteristics with the p-type layer 5, and only the ohmic contact with the n-type layer 3 is required. Should be considered.

【0019】また、このような半導体積層部の一部10
aを残存させる場合は、その部分だけレジスト膜が残存
するようにマスクのパターニングをして半導体積層部1
0をエッチングすることにより形成され、従来のn側電
極9を設けるために半導体積層部10をエッチングする
のと同じ工数で同様に形成することができる。また、こ
の残存させる半導体積層部の一部10aは、図1(b)
に示されるように、露出するn形層3の中心部に設けら
れる必要はなく、p側電極が接続されるp形層5とショ
ートしない範囲であればどこに設けられてもよい。
Further, a part 10 of such a semiconductor laminated portion is formed.
a, the mask is patterned so that the resist film remains only in that portion, and the semiconductor laminated portion 1 is formed.
It is formed by etching 0, and can be formed in the same manner with the same man-hour as etching the semiconductor laminated portion 10 to provide the conventional n-side electrode 9. Further, a part 10a of the remaining semiconductor laminated portion is shown in FIG.
As shown in (1), it is not necessary to provide at the center of the exposed n-type layer 3, but may be provided anywhere as long as the p-side electrode is not short-circuited with the p-type layer 5 to be connected.

【0020】半導体積層部10は、たとえばGaNから
なる低温バッファ層、クラッド層となるn形のGaNお
よび/またはAlGaN系(AlとGaの比率が種々変
わり得ることを意味する、以下同じ)化合物半導体の積
層構造からなるn形層3、バンドギャップエネルギーが
クラッド層のそれよりも小さくなる材料、たとえばIn
GaN系化合物半導体からなる活性層4、およびp形の
AlGaN系化合物半導体層および/またはGaN層か
らなるp形層(クラッド層)5が、それぞれ順次積層さ
れることにより構成されている。
The semiconductor laminated portion 10 is made of, for example, a low-temperature buffer layer made of GaN and an n-type GaN and / or AlGaN-based (which means that the ratio of Al to Ga can be variously changed, hereinafter the same) a clad layer. N-type layer 3 having a layered structure of a material having a band gap energy smaller than that of the cladding layer, for example, In
An active layer 4 made of a GaN-based compound semiconductor and a p-type layer (cladding layer) 5 made of a p-type AlGaN-based compound semiconductor layer and / or a GaN layer are sequentially laminated.

【0021】p側電極8は、図示しないAuとNiの合
金層からなる電流拡散層を介してTiとAuの積層構造
により形成される。この電流拡散層が形成された後にn
側電極形成のためのエッチングが行われる場合、残存す
る半導体積層部の一部10aの表面に電流拡散層が形成
されていてもよい。残存する半導体積層部の一部10a
はn側電極9の高さ調整のためのものだからである。
The p-side electrode 8 is formed by a laminated structure of Ti and Au via a current diffusion layer made of an alloy layer of Au and Ni (not shown). After the current diffusion layer is formed, n
When the etching for forming the side electrode is performed, a current diffusion layer may be formed on the surface of a portion 10a of the remaining semiconductor laminated portion. Part 10a of remaining semiconductor laminated portion
Is for adjusting the height of the n-side electrode 9.

【0022】この半導体発光素子を製造するには、たと
えば有機金属化学気相成長法(MOCVD法)により、
反応ガスおよび必要なドーパントガスを導入してn形層
3を1〜5μm程度、活性層4を0.05〜0.3μm程
度、およびp形層5を0.2〜1μm程度、それぞれエ
ピタキシャル成長する。その後、NiおよびAuをそれ
ぞれ真空蒸着などにより積層してシンターすることによ
り合金化して、活性層4で発光する光を透過させると共
に、電流を拡散させる電流拡散層(図示せず)を2〜1
00nm程度形成する。ついで、表面にレジスト膜を設
け、パターニングをして塩素ガスなどによる反応性イオ
ンエッチングにより、積層された半導体積層部10を図
1(b)に示されるように部分的に除去する。このパタ
ーニングの際に半導体積層部の一部10aが残存するよ
うにレジスト膜を残す。その後、前述の電極金属を蒸着
してパターニングをすることにより、またはリフトオフ
法によりp側電極8およびn側電極9を形成する。
In order to manufacture this semiconductor light emitting device, for example, a metal organic chemical vapor deposition (MOCVD) method is used.
A reactive gas and a necessary dopant gas are introduced to epitaxially grow the n-type layer 3 about 1 to 5 μm, the active layer 4 about 0.05 to 0.3 μm, and the p-type layer 5 about 0.2 to 1 μm. . Thereafter, Ni and Au are laminated by vacuum deposition or the like, respectively, and alloyed by sintering. A current diffusion layer (not shown) for transmitting light emitted from the active layer 4 and diffusing current is set at 2 to 1.
It is formed to a thickness of about 00 nm. Next, a resist film is provided on the surface, patterned, and the laminated semiconductor laminated portion 10 is partially removed by reactive ion etching using chlorine gas or the like, as shown in FIG. 1B. At the time of this patterning, the resist film is left so that a part 10a of the semiconductor laminated portion remains. Thereafter, the p-side electrode 8 and the n-side electrode 9 are formed by depositing the above-described electrode metal and patterning the same, or by a lift-off method.

【0023】本発明によれば、LEDチップのp側電極
8とn側電極9とがほぼ同一面に形成されているため、
たとえば図2(a)に示されるように、LEDチップ1
3を第1のリード11にダイボンディングをして、その
p側電極8およびn側電極9をそれぞれ第2のリード1
2および第1のリード11と金線14などによりワイヤ
ボンディングをする場合、両電極8、9がほぼ同一面に
あるため、自動のワイヤボンディング機を用いて行って
も均一なボンディングをすることができる。
According to the present invention, since the p-side electrode 8 and the n-side electrode 9 of the LED chip are formed on substantially the same plane,
For example, as shown in FIG.
3 is die-bonded to the first lead 11, and the p-side electrode 8 and the n-side electrode 9 are respectively connected to the second lead 1.
When performing wire bonding with the second and first leads 11 and the gold wire 14 or the like, since both electrodes 8 and 9 are substantially on the same surface, uniform bonding can be performed even with an automatic wire bonding machine. it can.

【0024】また、図2(b)に示されるように、LE
Dチップ13を裏向きにしてそれぞれの電極9、8が第
1および第2のリード11、12に電気的に接続される
ようにボンディングをする場合にも、LEDチップ13
のp側電極8とn側電極9とがほぼ同一面にあるため、
同じ高さのリード11、12の上に載置してボンディン
グをすることができ、容易に、かつ、確実にダイボンデ
ィングをすることができる。なお、これらのLEDチッ
プ13部分がLEDチップ13で発光する光を透過する
樹脂により被覆されて樹脂パッケージ15が形成される
ことにより、ランプ型の発光素子とされる。
Further, as shown in FIG.
The LED chip 13 is also used for bonding such that the electrodes 9 and 8 are electrically connected to the first and second leads 11 and 12 with the D chip 13 facing down.
Since the p-side electrode 8 and the n-side electrode 9 are substantially in the same plane,
Bonding can be performed by mounting the leads 11 and 12 on the same height, and die bonding can be performed easily and reliably. Note that these LED chips 13 are covered with a resin that transmits light emitted by the LED chips 13 to form the resin package 15, thereby forming a lamp-type light emitting element.

【0025】一方、n側電極9をp側電極8と実質的に
同じ高さにするため、残存する半導体積層部の一部10
aを設けることは、従来のn側電極を形成するために半
導体積層部10を部分的にエッチングする場合のマスク
のパターニングを変えるだけで、製造工程は何等変わる
ことがない。そのため、LEDチップの製造時には工数
増になることもなく、むしろ後のボンディング時には作
業が容易で全体としては工数減になると共に、ボンディ
ングの信頼性が向上する。
On the other hand, in order to make the n-side electrode 9 substantially the same height as the p-side electrode 8, a part 10
Providing a only changes the patterning of the mask when partially etching the semiconductor laminated portion 10 in order to form the conventional n-side electrode, and the manufacturing process does not change at all. Therefore, the man-hour does not increase during the manufacture of the LED chip, but rather the work is easy during the later bonding, the man-hour is reduced as a whole, and the reliability of the bonding is improved.

【0026】図3(a)〜(c)は、本発明の半導体発
光素子の他の実施形態であるチッ化ガリウム系化合物半
導体を用いた半導体レーザの製造工程を示す図、図3
(d)はそのチップの平面説明図である。まず、LED
チップの場合と同様に、サファイア基板31上に、n形
クラッド層33、活性層34、およびp形層35を同様
の組成および同程度の厚さで積層する。その後、アニー
ルをしてp形クラッド層35の活性化処理を行う。そし
てNiおよびAuを蒸着してシンターすることにより、
Au-Ni合金からなるp側電極38をリフトオフ法な
どによりストライプ状に形成する。その後、p側電極3
8部および半導体積層部の一部30aが残存する(図3
(b)参照)ようにマスクを形成し、塩素ガスなどによ
る反応性イオンエッチングにより、積層された半導体積
層部を部分的に除去する。ついで、Al-Ti合金およ
びAuの積層構造からなるn側電極39をリフトオフ法
などにより形成し、ダイシングすることにより、レーザ
チップが形成される。
3 (a) to 3 (c) are views showing a manufacturing process of a semiconductor laser using a gallium nitride compound semiconductor as another embodiment of the semiconductor light emitting device of the present invention.
(D) is an explanatory plan view of the chip. First, LED
As in the case of the chip, the n-type cladding layer 33, the active layer 34, and the p-type layer 35 are laminated on the sapphire substrate 31 with the same composition and the same thickness. Thereafter, annealing is performed to activate the p-type cladding layer 35. Then, Ni and Au are deposited and sintered,
A p-side electrode 38 made of an Au-Ni alloy is formed in a stripe shape by a lift-off method or the like. Then, the p-side electrode 3
8 and a part 30a of the semiconductor laminated portion remain (FIG. 3).
As shown in (b)), a mask is formed, and the stacked semiconductor laminated portions are partially removed by reactive ion etching using chlorine gas or the like. Next, a laser chip is formed by forming an n-side electrode 39 having a laminated structure of an Al-Ti alloy and Au by a lift-off method or the like and dicing.

【0027】このチップをサブマウントなどのマウント
台にフェースダウンでダイボンディングをすることによ
り、傾きが生じたり、ストライプ状メサ部にダメージを
与えることなく、精度のよいダイボンディングをするこ
とができる。なお、半導体レーザにする場合、図3
(d)に平面図が示されるように、活性層34のチップ
側面からビーム状に光を照射するため、積層された半導
体層の表面側からの光の取出しの必要がなく、電流拡散
層を設けることなく、p側電極38は電気的接触が充分
に行われるように、p形クラッド層の全面に設けられ
る。
By performing die bonding of this chip face-down on a mount base such as a submount, accurate die bonding can be performed without tilting or damaging the stripe-shaped mesa portion. When a semiconductor laser is used, FIG.
As shown in the plan view of FIG. 4D, since light is emitted in a beam form from the chip side surface of the active layer 34, there is no need to take out light from the surface side of the stacked semiconductor layers, and the current diffusion layer is formed. Without being provided, the p-side electrode 38 is provided on the entire surface of the p-type clad layer so that electrical contact is sufficiently performed.

【0028】なお、図1〜3に示される例では、チッ化
ガリウム系化合物半導体を用いた青色系の半導体発光素
子であったが、GaAs系やGaP系の化合物半導体を
用いた赤色系や緑色系の半導体発光素子であっても、p
側およびn側の電極が積層された半導体層側である同一
面側に設けられる場合は同様に本発明を適用することに
より、ワイヤボンディングなどが容易になる。さらに、
前述のLEDの例では、n形層3とp形層5とで活性層
4が挟持されたダブルヘテロ接合構造であるが、n形層
とp形層とが直接接合するpn接合構造の半導体発光素
子でも同様である。
In the examples shown in FIGS. 1 to 3, a blue semiconductor light emitting device using a gallium nitride compound semiconductor is used. However, a red or green semiconductor light emitting device using a GaAs or GaP compound semiconductor is used. System semiconductor light emitting device
If the n-side electrode and the n-side electrode are provided on the same surface side, which is the semiconductor layer side on which the layers are stacked, the present invention is similarly applied to facilitate wire bonding and the like. further,
In the example of the LED described above, the active layer 4 is sandwiched between the n-type layer 3 and the p-type layer 5, but the semiconductor has a pn junction structure in which the n-type layer and the p-type layer are directly bonded. The same applies to a light emitting element.

【0029】[0029]

【発明の効果】本発明によれば、p側電極およびn側電
極が実質的に(ほぼ)同じ高さに形成されているため、
ワイヤボンディングなどの作業が容易になると共に、確
実にボンディングをすることができる。その結果、ボン
ディング時の工数減および歩留りの向上によりコストダ
ウンが図られると共に、ボンディングの信頼性が向上す
る。
According to the present invention, the p-side electrode and the n-side electrode are formed at substantially (substantially) the same height.
Work such as wire bonding becomes easy, and bonding can be performed reliably. As a result, the cost is reduced by reducing the number of steps and the yield during bonding, and the reliability of bonding is improved.

【0030】また、メサストライプ型の半導体レーザが
フェースダウンでダイボンディングされる場合でも、ス
トライプ部にダメージを与えることなく、しかも傾きな
どが生じることなく高特性の半導体レーザが得られる。
Further, even when the mesa stripe type semiconductor laser is die-bonded face down, a semiconductor laser having high characteristics can be obtained without damaging the stripe portion and without causing inclination or the like.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体発光素子の一実施形態のLED
チップの説明図である。
FIG. 1 shows an LED according to an embodiment of the semiconductor light emitting device of the present invention.
It is explanatory drawing of a chip.

【図2】図1のLEDチップをリードなどにマウントす
る場合の断面説明図である。
FIG. 2 is an explanatory sectional view when the LED chip of FIG. 1 is mounted on a lead or the like;

【図3】本発明の半導体発光素子の他の実施形態である
半導体レーザの一例の製造工程を示す図である。
FIG. 3 is a diagram showing a manufacturing process of an example of a semiconductor laser which is another embodiment of the semiconductor light emitting device of the present invention.

【図4】従来の半導体発光素子のLEDチップの一例の
斜視説明図である。
FIG. 4 is a perspective explanatory view of an example of a conventional LED chip of a semiconductor light emitting device.

【図5】従来の半導体レーザをフェースダウンでダイボ
ンディングする説明図である。
FIG. 5 is an explanatory diagram of face-down die bonding of a conventional semiconductor laser.

【符号の説明】[Explanation of symbols]

1 基板 3 n形層 5 p形層 8 p側電極 9 n側電極 10 半導体積層部 Reference Signs List 1 substrate 3 n-type layer 5 p-type layer 8 p-side electrode 9 n-side electrode 10 semiconductor laminated portion

───────────────────────────────────────────────────── フロントページの続き (72)発明者 筒井 毅 京都市右京区西院溝崎町21番地 ローム株 式会社内 (72)発明者 伊藤 範和 京都市右京区西院溝崎町21番地 ローム株 式会社内 (72)発明者 市原 淳 京都市右京区西院溝崎町21番地 ローム株 式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Tsutsui No.21, Saiin Mizozakicho, Ukyo-ku, Kyoto-shi Inside Rohm Co., Ltd. Inventor Atsushi Ichihara 21 Ryozaki-cho, Saiin, Ukyo-ku, Kyoto City Inside ROHM Co., Ltd.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板と、該基板上に発光層を形成すべく
積層される半導体積層部と、該半導体積層部の表面側の
第1導電形の半導体層に接続して設けられる第1の電極
と、前記半導体積層部の一部がエッチングにより除去さ
れて露出する第2導電形の半導体層に接続して設けられ
る第2の電極とからなり、前記第1および第2の電極
が、前記基板からほぼ同じ高さになるように形成されて
なる半導体発光素子。
1. A semiconductor device comprising: a substrate; a semiconductor laminated portion laminated to form a light emitting layer on the substrate; and a first conductive type semiconductor layer provided on a surface side of the semiconductor laminated portion, the first conductive type semiconductor layer being provided on the surface side of the semiconductor laminated portion. An electrode, and a second electrode provided in connection with a semiconductor layer of a second conductivity type in which a part of the semiconductor laminated portion is removed by etching and is exposed, wherein the first and second electrodes are A semiconductor light emitting device formed to be substantially the same height from a substrate.
【請求項2】 前記第2の電極が、前記半導体積層部の
一部が除去されて露出する第2導電形の半導体層と、前
記半導体積層部がエッチングされないで残存する部分に
連続して形成されてなる請求項1記載の半導体発光素
子。
2. The semiconductor device according to claim 1, wherein the second electrode is formed continuously on a semiconductor layer of the second conductivity type where a part of the semiconductor laminated portion is removed and exposed, and on a portion where the semiconductor laminated portion remains without being etched. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is formed.
【請求項3】 前記基板が電気的絶縁性基板である請求
項1または2記載の半導体発光素子。
3. The semiconductor light emitting device according to claim 1, wherein said substrate is an electrically insulating substrate.
【請求項4】 前記半導体積層部がチッ化ガリウム系化
合物半導体からなる請求項1、2または3記載の半導体
発光素子。
4. The semiconductor light emitting device according to claim 1, wherein said semiconductor laminated portion is made of a gallium nitride compound semiconductor.
【請求項5】 前記第1導電形の半導体層がストライプ
状に残存するようにメサエッチングがなされて半導体レ
ーザが形成されてなる請求項1、2、3、または4記載
の半導体発光素子。
5. The semiconductor light emitting device according to claim 1, wherein the semiconductor laser is formed by mesa etching so that the semiconductor layer of the first conductivity type remains in a stripe shape.
JP02138897A 1997-02-04 1997-02-04 Semiconductor light emitting device Expired - Fee Related JP3752339B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02138897A JP3752339B2 (en) 1997-02-04 1997-02-04 Semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02138897A JP3752339B2 (en) 1997-02-04 1997-02-04 Semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JPH10223930A true JPH10223930A (en) 1998-08-21
JP3752339B2 JP3752339B2 (en) 2006-03-08

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Country Link
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