JPH10209496A - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device

Info

Publication number
JPH10209496A
JPH10209496A JP1122597A JP1122597A JPH10209496A JP H10209496 A JPH10209496 A JP H10209496A JP 1122597 A JP1122597 A JP 1122597A JP 1122597 A JP1122597 A JP 1122597A JP H10209496 A JPH10209496 A JP H10209496A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor
light emitting
layer
led chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1122597A
Other languages
Japanese (ja)
Inventor
Takeshi Tsutsui
毅 筒井
Shunji Nakada
俊次 中田
Yukio Shakuda
幸男 尺田
Masayuki Sonobe
雅之 園部
Norikazu Ito
範和 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP1122597A priority Critical patent/JPH10209496A/en
Publication of JPH10209496A publication Critical patent/JPH10209496A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Devices (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device having an electrode structure which hardly deteriorates the device in light extraction efficiency, wherein wires can be automatically and easily bonded to an LED chip where a pair of electrodes are provided to the same surface side. SOLUTION: An LED chip is composed of a substrate 1, a semiconductor laminate 10 which includes a light emitting semiconductor layer on the substrate 1, a first electrode (P-side electrode 8) provided and connected to the uppermost first conductivity-type semiconductor layer (P-type layer 5) of the semiconductor laminate 10, and a second electrode (N-type electrode 9) provided and connected to the second conductivity-type semiconductor layer (N-type layer 3) exposed by partially removing the semiconductor laminae 10 by etching, wherein the first electrode 8 is provided to the plane center of the LED chip, and the other second electrode 9 is formed concentrical with the plane center of the LED chip, wide enough for the bonding of a wire, and constant in width surrounding all the periphery of the first electrode 8.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は基板上に半導体層が
積層され、積層される半導体層の表面側にｐ側およびｎ
側の両電極が形成される半導体発光素子に関する。さら
に詳しくは、両電極にワイヤボンディングをする場合
に、自動機で行っても間違いなく容易に行うことができ
るように電極が設けられると共に、外部への光の取出し
効率を低下させない半導体発光素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor layer laminated on a substrate, and the p-side and n-side
The present invention relates to a semiconductor light emitting device in which both electrodes on the side are formed. More specifically, the present invention relates to a semiconductor light emitting device which is provided with electrodes so as to be able to carry out wire bonding to both electrodes without fail even if performed by an automatic machine, and which does not reduce the efficiency of extracting light to the outside. .

【０００２】[0002]

【従来の技術】たとえば青色系の半導体発光素子は、図
３にその発光素子チップ（以下、ＬＥＤチップという）
の一例の概略図が示されるように、サファイアからなる
絶縁性の基板２１上にチッ化ガリウム系化合物半導体層
が積層されて、その表面側にｐ側電極２８およびｎ側電
極２９の両方が設けられることにより形成されている。
すなわち、ウェハ状のサファイア基板２１上にたとえば
ｎ形のＧａＮがエピタキシャル成長されたｎ形層（クラ
ッド層）２３と、バンドギャップエネルギーがクラッド
層のそれよりも小さくなる材料、たとえばＩｎＧａＮ系
（ＩｎとＧａの比率が種々変わり得ることを意味する、
以下同じ）化合物半導体からなる活性層２４と、ｐ形の
ＧａＮからなるｐ形層（クラッド層）２５とが積層さ
れ、その表面のｐ形層２５に電気的に接続してｐ側電極
２８が、積層された半導体層の一部がエッチングされて
露出するｎ形層２３と電気的に接続してｎ側電極２９が
設けられることにより、ＬＥＤチップ２０が形成されて
いる。2. Description of the Related Art For example, a blue semiconductor light emitting device is shown in FIG. 3 as a light emitting device chip (hereinafter referred to as an LED chip).
As shown in a schematic diagram of an example, a gallium nitride-based compound semiconductor layer is laminated on an insulating substrate 21 made of sapphire, and both a p-side electrode 28 and an n-side electrode 29 are provided on the surface side thereof. It is formed by being performed.
That is, an n-type layer (cladding layer) 23 in which, for example, n-type GaN is epitaxially grown on a wafer-like sapphire substrate 21 and a material whose band gap energy is smaller than that of the cladding layer, for example, an InGaN-based (In and Ga) Means that the ratio of can vary.
An active layer 24 made of a compound semiconductor and a p-type layer (cladding layer) 25 made of p-type GaN are laminated, and electrically connected to the p-type layer 25 on the surface thereof to form a p-side electrode 28. The LED chip 20 is formed by providing an n-side electrode 29 that is electrically connected to the n-type layer 23 where a part of the stacked semiconductor layers is etched and exposed.

【０００３】このＬＥＤチップ２０がたとえば図４に断
面図およびその拡大平面図が示されるように、第１のリ
ード１１の先端部の湾曲部内にダイボンディングされ、
ｎ側電極２９が第１のリード１１の先端部の突出部１１
ａと、ｐ側電極２８が第２のリード１２の先端部とそれ
ぞれ金線１３によりワイヤボンディングされ、その周囲
が発光層で発光する光を透過させる樹脂で被覆されて樹
脂パッケージ１４が形成されることにより、発光ランプ
が形成される。The LED chip 20 is die-bonded into a curved portion at the tip of the first lead 11 as shown in, for example, a sectional view of FIG. 4 and an enlarged plan view thereof.
The n-side electrode 29 is a protrusion 11 at the tip of the first lead 11.
a and the p-side electrode 28 are each wire-bonded to the tip of the second lead 12 by the gold wire 13, and the periphery thereof is covered with a resin that transmits light emitted by the light emitting layer to form the resin package 14. Thereby, a light emitting lamp is formed.

【０００４】[0004]

【発明が解決しようとする課題】しかし、ＬＥＤチップ
の電極の形成が前述の構造であると、図５（ａ）に示さ
れるように、ＬＥＤチップ２０が第１のリード１１の先
端にマウントされ、ワイヤボンディングされるときに、
ｎ側電極２９とｐ側電極２８とがリード１１、１２側の
ボンディングされる位置Ｌと同列にない。そのため、Ｌ
ＥＤチップ２０のｐ側電極２８およびｎ側電極２９の位
置をそれぞれｘ座標、ｙ座標の両方で認識してワイヤボ
ンディングをしなければならず（ｘ方向、ｙ方向の両方
向に移動させなければならない）、時間を要する。ま
た、図５（ｂ）に示されるようにＬＥＤチップ２０がマ
ウントされる場合には、ワイヤボンディングの金線がク
ロスすることになり、ワイヤボンディングをすることが
できない。However, when the electrodes of the LED chip are formed as described above, the LED chip 20 is mounted on the tip of the first lead 11 as shown in FIG. , When wire bonding
The n-side electrode 29 and the p-side electrode 28 are not in the same row as the bonding position L on the leads 11 and 12 side. Therefore, L
Wire bonding must be performed by recognizing the positions of the p-side electrode 28 and the n-side electrode 29 of the ED chip 20 at both the x-coordinate and the y-coordinate (they must be moved in both the x and y directions). ), It takes time. Further, when the LED chip 20 is mounted as shown in FIG. 5B, the gold wires of the wire bonding cross, and the wire bonding cannot be performed.

【０００５】一方、特開平８−２５０７７０号公報や特
開平７−３０１５３号公報には、図６（ａ）〜（ｃ）に
示されるように、一方の電極２９の周囲にほぼ全面に亘
って他方の電極２８が設けられるものも開示されている
が、図６（ａ）に示される構造のものでは、ＬＥＤチッ
プの外形が４角形状で電極の内周が円形であるため、Ｌ
ＥＤチップの各辺の中心部では外側の電極２８の幅が狭
く、ワイヤボンディングはチップの角部で行わなければ
ならない。また、図６（ｂ）に示される構造のものは、
外側の電極２８がチップの中心から一定の距離のところ
になく、ＬＥＤチップが回転してマウントされたとき、
内側の電極２９と外側の電極２８とが一定距離になら
ず、自動的にワイヤボンディングをすることができな
い。さらに、図６（ｃ）に示される構造では、発光面が
殆ど電極２８で覆われることになり、外部への光の取出
し効率が低下する。なお、図３と同じ部分には同じ符号
を付してその説明を省略する。On the other hand, in Japanese Patent Application Laid-Open Nos. 8-250770 and 7-30153, as shown in FIGS. Although the one provided with the other electrode 28 is also disclosed, in the structure shown in FIG. 6A, the outer shape of the LED chip is square and the inner circumference of the electrode is circular.
The width of the outer electrode 28 is narrow at the center of each side of the ED chip, and wire bonding must be performed at the corner of the chip. In addition, the structure shown in FIG.
When the outer electrode 28 is not located at a certain distance from the center of the chip and the LED chip is rotated and mounted,
The inner electrode 29 and the outer electrode 28 do not have a fixed distance, so that wire bonding cannot be performed automatically. Further, in the structure shown in FIG. 6C, the light emitting surface is almost covered with the electrode 28, and the light extraction efficiency to the outside is reduced. The same parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

【０００６】本発明は、このような問題を解決するため
になされたもので、同一面側に一対の電極が設けられ、
両電極にワイヤボンディングされる場合に、ＬＥＤチッ
プが回転してマウントされても、容易に自動的にワイヤ
ボンディングを行うことができると共に、外部への光の
取出し効率を低下させない電極構造を有する半導体発光
素子を提供することを目的とする。The present invention has been made to solve such a problem, and a pair of electrodes are provided on the same surface side.
A semiconductor having an electrode structure that can easily and automatically perform wire bonding even when the LED chip is rotated and mounted when both electrodes are wire-bonded, and that does not reduce the efficiency of extracting light to the outside. It is an object to provide a light-emitting element.

【０００７】[0007]

【課題を解決するための手段】本発明による半導体発光
素子は、基板と、該基板上に発光層を形成すべく半導体
が積層される半導体積層部と、該半導体積層部の表面側
の第１導電形の半導体層に接続して設けられる第１の電
極と、前記半導体積層部の一部がエッチングにより除去
されて露出する第２導電形の半導体層に接続して設けら
れる第２の電極とから発光素子チップが形成され、前記
第１または第２の電極の一方が前記発光素子チップの平
面形状の中心部に設けられ、他方の電極が、前記中心部
と同心で、かつ、ワイヤボンディングがされる幅を有す
ると共に同じ幅で前記一方の電極の周囲全周に設けられ
ている。According to the present invention, there is provided a semiconductor light emitting device comprising: a substrate; a semiconductor laminated portion on which a semiconductor is laminated to form a light emitting layer on the substrate; A first electrode provided in connection with the semiconductor layer of the conductivity type, and a second electrode provided in connection with the semiconductor layer of the second conductivity type in which a part of the semiconductor laminated portion is removed by etching and exposed. A light emitting element chip is formed, one of the first and second electrodes is provided at the center of the planar shape of the light emitting element chip, and the other electrode is concentric with the center, and wire bonding is performed. And has the same width and is provided all around the one electrode.

【０００８】ここに第１導電形および第２導電形とは、
半導体の極性のｎ形およびｐ形のいずれか一方を第１導
電形としたとき、他方のｐ形またはｎ形が第２導電形で
あることを意味する。Here, the first conductivity type and the second conductivity type are:
When one of the n-type and p-type of the polarity of the semiconductor is set to the first conductivity type, it means that the other p-type or n-type is the second conductivity type.

【０００９】この構造にすることにより、ＬＥＤチップ
をリードなどの先端にマウントし、ＬＥＤチップの両電
極と２本のリードとがワイヤボンディングにより接続さ
れる場合に、ＬＥＤチップがどの向きに（回転して）マ
ウントされても、一方の電極はその中心部に存在し、他
方の電極はその中心部から常に一定の距離のところに存
在し、しかも２本のリードとＬＥＤチップのそれぞれの
ワイヤボンディング部分を一直線上にすることができる
ため、機械的にワイヤボンディングをすることができ
る。With this structure, when the LED chip is mounted on the tip of a lead or the like and the two electrodes of the LED chip are connected to the two leads by wire bonding, the direction (rotation) When mounted, one electrode is at its center and the other electrode is always at a fixed distance from its center, and each of the two leads and the wire bonding of the LED chip Since the portions can be aligned, wire bonding can be performed mechanically.

【００１０】前記他方の電極の幅が５０〜１５０μｍで
あることが、ワイヤボンディングを確実に行うことがで
きると共に、光の遮断を最小限に抑えることができ、外
部への光の取出し効率を向上させることができるため好
ましい。When the width of the other electrode is 50 to 150 μm, wire bonding can be performed reliably, light can be cut off to a minimum, and efficiency of extracting light to the outside can be improved. It is preferable because it can be performed.

【００１１】[0011]

【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体発光素子について説明をする。図１には、た
とえば青色系の発光に適するチッ化ガリウム系化合物半
導体が積層された本発明の半導体発光素子のチップの断
面および平面の説明図が示されている。ここにチッ化ガ
リウム系化合物半導体とは、III 族元素のＧａとＶ族元
素のＮとの化合物またはIII 族元素のＧａの一部がＡ
ｌ、Ｉｎなどの他のIII 族元素と置換したものおよび／
またはＶ族元素のＮの一部がＰ、Ａｓなどの他のＶ族元
素と置換した化合物からなる半導体をいう。Next, a semiconductor light emitting device of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory view showing a cross section and a plan view of a chip of a semiconductor light emitting device of the present invention in which, for example, a gallium nitride compound semiconductor suitable for blue light emission is laminated. Here, the gallium nitride-based compound semiconductor is a compound of a group III element Ga and a group V element N or a part of the group III element Ga is A
l, In and others substituted with Group III elements and / or
Alternatively, it refers to a semiconductor including a compound in which part of N of a group V element is replaced with another group V element such as P or As.

【００１２】本発明の半導体発光素子は、たとえば図１
に示されるように、サファイア（Ａｌ2 Ｏ3 単結晶）な
どからなる絶縁性の基板１の表面に発光層を形成する半
導体積層部１０が形成されて、その表面側の第１導電形
の半導体層（ｐ形層５）に、図示しない電流拡散層を介
してｐ側電極（第１の電極）８が電気的に接続されてい
る。また、半導体積層部１０の一部が除去されて露出す
る第２導電形の半導体層（ｎ形層３）に電気的に接続さ
れるようにｎ側電極（第２の電極）９が電気的に接続さ
れている。本発明では、図１（ｂ）に平面図が示される
ように、ＬＥＤチップの中心部に半導体積層部１０が円
柱状に残存するようにその周囲がエッチングされ、その
残存した円柱状の半導体積層部１０の中心部にｐ側電極
８が設けられている。そして、半導体積層部１０の周囲
のエッチングにより露出したｎ形層３の表面にＬＥＤチ
ップの中心（半導体積層部１０の中心）部と同心で、ワ
イヤボンディングをすることができる一定の幅Ｂでリン
グ状にｎ側電極９が形成されていることに特徴がある。
その結果、ｐ側電極８の中心とｎ側電極９との距離は常
に一定となる。The semiconductor light emitting device of the present invention is, for example, shown in FIG.
As shown in FIG. 1, a semiconductor laminated portion 10 for forming a light emitting layer is formed on a surface of an insulating substrate 1 made of sapphire (Al 2 O 3 single crystal) or the like, and a semiconductor of the first conductivity type on the surface side. A p-side electrode (first electrode) 8 is electrically connected to the layer (p-type layer 5) via a current diffusion layer (not shown). Further, the n-side electrode (second electrode) 9 is electrically connected so as to be electrically connected to the semiconductor layer (n-type layer 3) of the second conductivity type which is exposed by removing a part of the semiconductor lamination portion 10. It is connected to the. In the present invention, as shown in the plan view of FIG. 1B, the periphery is etched so that the semiconductor laminated portion 10 remains in the center of the LED chip in a cylindrical shape, and the remaining cylindrical semiconductor laminated portion is etched. A p-side electrode 8 is provided at the center of the portion 10. Then, a ring having a constant width B allowing wire bonding to be concentric with the center of the LED chip (the center of the semiconductor laminated portion 10) on the surface of the n-type layer 3 exposed by etching around the semiconductor laminated portion 10. It is characterized in that the n-side electrode 9 is formed in the shape of a circle.
As a result, the distance between the center of the p-side electrode 8 and the n-side electrode 9 is always constant.

【００１３】このような形状のＬＥＤチップを形成する
には、ウェハ状のサファイア基板１に半導体層を積層し
て半導体積層部１０および図示しない電流拡散層を形成
した後に、その表面にレジスト膜を設け、ＬＥＤチップ
の中心部に円形状に残存するようにパターニングをし、
半導体積層部１０をエッチングをすることによりチップ
の中心部に半導体積層部１０を円柱状に残存させること
ができる。電極の形成も同様にマスクのパターニングに
より、所望の形状に形成することができる。その結果、
従来の製造工程と同じ工程で、マスクのパターニング形
状を変えるだけで、図１に示されるような構造のＬＥＤ
チップが得られる。In order to form an LED chip having such a shape, a semiconductor layer is laminated on a sapphire substrate 1 in the form of a wafer to form a semiconductor laminated portion 10 and a current diffusion layer (not shown). Provided and patterned so as to remain in a circular shape at the center of the LED chip,
By etching the semiconductor laminated portion 10, the semiconductor laminated portion 10 can be left in a columnar shape at the center of the chip. Similarly, the electrode can be formed into a desired shape by patterning the mask. as a result,
In the same process as the conventional manufacturing process, an LED having a structure as shown in FIG.
Chips are obtained.

【００１４】このエッチングの形状は、たとえばＬＥＤ
チップの一辺の長さＤが約６００μｍ程度、円柱状の半
導体積層部１０の外径Ｃが約３６０μｍ程度、ｐ側電極
８の直径Ａが約１００μｍ程度、ｎ側電極９の幅Ｂが１
００μｍ程度に形成される。この程度の寸法で形成する
ことにより、従来のチップの一辺が数百μｍ角程度より
若干大きくなるが、従来以上の輝度が得られる。The shape of this etching is, for example, LED
The length D of one side of the chip is about 600 μm, the outer diameter C of the columnar semiconductor laminated portion 10 is about 360 μm, the diameter A of the p-side electrode 8 is about 100 μm, and the width B of the n-side electrode 9 is 1
It is formed to about 00 μm. By forming with such a size, one side of the conventional chip is slightly larger than about several hundred μm square, but higher luminance than the conventional one can be obtained.

【００１５】半導体積層部１０は、たとえばＧａＮから
なる低温バッファ層、クラッド層となるｎ形のＧａＮお
よび／またはＡｌＧａＮ系（ＡｌとＧａの比率が種々変
わり得ることを意味する、以下同じ）化合物半導体の積
層構造からなるｎ形層３、バンドギャップエネルギーが
クラッド層のそれよりも小さくなる材料、たとえばＩｎ
ＧａＮ系化合物半導体からなる活性層４、およびｐ形の
ＡｌＧａＮ系化合物半導体層および／またはＧａＮ層か
らなるｐ形層（クラッド層）５が、基板１上にそれぞれ
順次積層されることにより構成されている。The semiconductor laminated portion 10 includes, for example, a low-temperature buffer layer made of GaN and an n-type GaN and / or AlGaN-based (which means that the ratio of Al to Ga can be variously changed, the same applies hereinafter) compound semiconductor to be a clad layer. N-type layer 3 having a layered structure of a material having a band gap energy smaller than that of the cladding layer, for example, In
An active layer 4 made of a GaN-based compound semiconductor and a p-type layer (cladding layer) 5 made of a p-type AlGaN-based compound semiconductor layer and / or a GaN layer are sequentially laminated on the substrate 1. I have.

【００１６】この半導体発光素子を製造するには、たと
えば有機金属化学気相成長法（ＭＯＣＶＤ法）により、
反応ガスおよび必要なドーパントガスを導入してｎ形層
３を１〜５μｍ程度、活性層４を０.０５〜０.３μｍ程
度、およびｐ形層５を０.２〜１μｍ程度、それぞれエ
ピタキシャル成長する。その後、電流拡散層を設ける場
合は、たとえばＮｉおよびＡｕをそれぞれ真空蒸着など
により積層してシンターすることにより合金化し、２〜
１００ｎｍ程度の厚さに形成する。In order to manufacture this semiconductor light emitting device, for example, a metal organic chemical vapor deposition (MOCVD) method is used.
A reactive gas and a necessary dopant gas are introduced to epitaxially grow the n-type layer 3 about 1 to 5 μm, the active layer 4 about 0.05 to 0.3 μm, and the p-type layer 5 about 0.2 to 1 μm. . Thereafter, when a current diffusion layer is provided, for example, Ni and Au are laminated by vacuum deposition or the like and alloyed by sintering.
It is formed to a thickness of about 100 nm.

【００１７】ついで、表面にレジスト膜を設け、パター
ニングをして塩素ガスなどによる反応性イオンエッチン
グにより、積層された半導体層の一部を図１に示される
ように除去することにより、チップの中心部に円柱状の
半導体積層部１０を残す。その後、たとえばリフトオフ
法により、ＴｉとＡｕとを積層して両金属の積層構造か
らなるｐ側電極８を形成する。また同様に、たとえばリ
フトオフ法により、ＴｉとＡｌをそれぞれ積層してシン
ターすることにより両金属の合金層からなるｎ側電極９
を形成する。この半導体積層部のエッチングおよびｐ側
とｎ側の電極８、９の形成の際に、前述のようにマスク
のパターニングを行うことにより、図１に示されるよう
な構造のＬＥＤチップが得られる。Next, a resist film is provided on the surface, patterned, and a part of the laminated semiconductor layer is removed by reactive ion etching with chlorine gas or the like as shown in FIG. The columnar semiconductor laminated portion 10 is left in the portion. Thereafter, Ti and Au are laminated by, for example, a lift-off method to form a p-side electrode 8 having a laminated structure of both metals. Similarly, by stacking and sintering Ti and Al respectively by, for example, a lift-off method, the n-side electrode 9 made of an alloy layer of both metals is formed.
To form By performing the patterning of the mask as described above at the time of etching the semiconductor laminated portion and forming the p-side and n-side electrodes 8 and 9, an LED chip having a structure as shown in FIG. 1 is obtained.

【００１８】本発明の半導体発光素子によれば、一方の
電極（たとえばｐ側電極８）がＬＥＤチップの中心部に
設けられ、他方の電極（たとえばｎ側電極９）がその周
囲の一定距離のところに、しかもワイヤボンディングを
することができる一定の幅Ｂで設けられている。そのた
め、組立工程で、ＬＥＤチップをマウントしてワイヤボ
ンディングをする場合に、ＬＥＤチップの向きが回転し
ていても中心にさえマウントされておれば、常に両電極
は一定の距離のところに存在し、自動機で機械的にワイ
ヤボンディングをすることができる。そのため、非常に
簡単に組み立てることができる。一方、周囲にリング状
に設けられる電極は、ワイヤボンディングをするために
必要な幅、すなわち５０〜１５０μｍ程度の幅だけであ
るため、発光面を電極で遮断する面積は最低限に抑制さ
れている。その結果、外部に取り出すことができる光の
割合である外部発光効率を充分に向上させることができ
る。According to the semiconductor light emitting device of the present invention, one electrode (for example, the p-side electrode 8) is provided at the center of the LED chip, and the other electrode (for example, the n-side electrode 9) is provided at a certain distance around the periphery. However, it is provided with a constant width B that allows wire bonding. Therefore, when mounting the LED chip and performing wire bonding in the assembling process, both electrodes always exist at a fixed distance as long as the LED chip is mounted at the center even if the orientation is rotated. In addition, wire bonding can be performed mechanically by an automatic machine. Therefore, it can be assembled very easily. On the other hand, an electrode provided in a ring shape around the electrode is only a width necessary for wire bonding, that is, a width of about 50 to 150 μm, and therefore, an area in which the light emitting surface is blocked by the electrode is minimized. . As a result, external luminous efficiency, which is the ratio of light that can be extracted to the outside, can be sufficiently improved.

【００１９】本発明は、以上のように、ＬＥＤチップの
中心部に一方の電極が設けられ、他方の電極が同心状に
その周囲に一定の幅で設けられていることに特徴があ
り、図１に示される構造に限定されるものではない。す
なわち、図２に示されるように、半導体積層部１０のエ
ッチングをＬＥＤチップの中心部に設け、中心部に露出
するｎ形層３に電気的に接続してｎ側電極９を設け、そ
の周囲に残存する半導体積層部１０のｐ形層５に電気的
に接続してｐ側電極８がワイヤボンディングをすること
ができる幅で、チップの中心部と同心で、かつ、リング
状に設けられてもよい。この場合、半導体積層部１０の
エッチング領域を最低限に抑えることができ、ｐ側電極
８の外周でも活性層４を含む半導体積層部１０があり発
光に寄与するため、小さいチップ面積で発光領域を大き
く確保することができる。なお、図１と同じ部分には同
じ符号を付してある。As described above, the present invention is characterized in that one electrode is provided at the center of the LED chip and the other electrode is provided concentrically with a constant width around the center. However, the present invention is not limited to the structure shown in FIG. That is, as shown in FIG. 2, the etching of the semiconductor laminated portion 10 is provided at the center of the LED chip, and is electrically connected to the n-type layer 3 exposed at the center, and the n-side electrode 9 is provided. The p-side electrode 8 is electrically connected to the p-type layer 5 of the semiconductor lamination portion 10 and has a width that allows wire bonding, and is provided concentrically with the center of the chip and in a ring shape. Is also good. In this case, the etching region of the semiconductor lamination portion 10 can be minimized, and the semiconductor lamination portion 10 including the active layer 4 exists on the outer periphery of the p-side electrode 8 and contributes to light emission. It can be secured large. The same parts as those in FIG. 1 are denoted by the same reference numerals.

【００２０】また、図１に示される例では、ｎ形層３と
ｐ形層５とで活性層４が挟持されるダブルヘテロ接合構
造であるが、ｎ形層とｐ形層とが直接接合するｐｎ接合
構造の半導体発光素子でも同様である。また、積層され
る半導体層の材料も一例であって、その材料には限定さ
れない。さらに、前述の各例では、絶縁性の基板上に半
導体層が積層される例であったが、絶縁性の基板上に半
導体層が積層される場合に一対の両電極が基板の一面側
に設けられる可能性が高いものの、ＧａＡｓ基板やＧａ
Ｐ基板など、導電性の基板上に半導体層が積層される半
導体発光素子においても、基板の同一面側に両電極が設
けられる場合に本発明を適用することができる。Further, in the example shown in FIG. 1, the active layer 4 is sandwiched between the n-type layer 3 and the p-type layer 5, but the n-type layer and the p-type layer are directly joined. The same applies to a semiconductor light emitting device having a pn junction structure. The material of the semiconductor layers to be stacked is also an example, and is not limited to the material. Further, in each of the above-described examples, the semiconductor layer is laminated on the insulating substrate. However, when the semiconductor layer is laminated on the insulating substrate, the pair of electrodes are disposed on one side of the substrate. Although it is likely to be provided, a GaAs substrate or Ga
The present invention can also be applied to a semiconductor light emitting element in which a semiconductor layer is stacked on a conductive substrate such as a P substrate when both electrodes are provided on the same surface side of the substrate.

【００２１】[0021]

【発明の効果】本発明によれば、ワイヤボンディングが
非常に容易になると共に、ｎ側電極とｐ側電極とでワイ
ヤボンディングの金線がクロスすることがなく、ボンデ
ィング工数の削減および歩留り向上を果たすことができ
る。According to the present invention, the wire bonding is greatly facilitated, and the gold wire of the wire bonding does not cross between the n-side electrode and the p-side electrode, thereby reducing the number of bonding steps and improving the yield. Can be fulfilled.

【００２２】さらに、電極は最低限の一定幅で設けられ
ているため、ＬＥＤチップの表面が必要以上に電極で覆
われることがなく、外部発光効率が向上する。Further, since the electrodes are provided with a minimum constant width, the surface of the LED chip is not unnecessarily covered with the electrodes, and the external luminous efficiency is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体発光素子の一実施形態のＬＥＤ
チップの断面および平面説明図である。FIG. 1 shows an LED according to an embodiment of the semiconductor light emitting device of the present invention.
It is sectional drawing and a plane explanatory view of a chip.

【図２】本発明の半導体発光素子の他の実施形態のＬＥ
Ｄチップの断面説明図である。FIG. 2 shows an LE of another embodiment of the semiconductor light emitting device of the present invention.
It is sectional explanatory drawing of a D chip.

【図３】従来の半導体発光素子のＬＥＤチップの一例の
斜視説明図である。FIG. 3 is a perspective explanatory view of an example of a conventional LED chip of a semiconductor light emitting device.

【図４】従来のＬＥＤチップのワイヤボンディングの説
明図である。FIG. 4 is an explanatory diagram of wire bonding of a conventional LED chip.

【図５】従来のＬＥＤチップのワイヤボンディングの説
明図である。FIG. 5 is an explanatory diagram of wire bonding of a conventional LED chip.

【図６】従来のＬＥＤチップの電極パターンの他の例の
説明図である。FIG. 6 is an explanatory diagram of another example of the electrode pattern of the conventional LED chip.

【符号の説明】[Explanation of symbols]

１ 基板 ３ ｎ形層 ５ ｐ形層 ８ ｐ側電極 ９ ｎ側電極 １０ 半導体積層部 Reference Signs List 1 substrate 3 n-type layer 5 p-type layer 8 p-side electrode 9 n-side electrode 10 semiconductor laminated portion

───────────────────────────────────────────────────── フロントページの続き (72)発明者 園部 雅之 京都市右京区西院溝崎町21番地 ローム株 式会社内 (72)発明者 伊藤 範和 京都市右京区西院溝崎町21番地 ローム株 式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masayuki Sonobe 21st Ryoin Mizozakicho, Ukyo-ku, Kyoto City (72) Inventor Noriwa Ito 21st Rohm Co., Ltd., Saiin-Mizozakicho, Ukyo-ku, Kyoto

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 基板と、該基板上に発光層を形成すべく
半導体が積層される半導体積層部と、該半導体積層部の
表面側の第１導電形の半導体層に接続して設けられる第
１の電極と、前記半導体積層部の一部がエッチングによ
り除去されて露出する第２導電形の半導体層に接続して
設けられる第２の電極とから発光素子チップが形成さ
れ、前記第１または第２の電極の一方が前記発光素子チ
ップの平面形状の中心部に設けられ、他方の電極が、前
記中心部と同心で、かつ、ワイヤボンディングがされる
幅を有すると共に同じ幅で前記一方の電極の周囲全周に
設けられてなる半導体発光素子。1. A semiconductor device comprising: a substrate; a semiconductor laminated portion on which a semiconductor is laminated to form a light emitting layer on the substrate; and a first conductive type semiconductor layer provided on a front surface side of the semiconductor laminated portion. A light emitting element chip is formed from one electrode and a second electrode provided in connection with a second conductive type semiconductor layer in which a part of the semiconductor laminated portion is removed by etching and exposed; One of the second electrodes is provided at a central portion of the planar shape of the light emitting element chip, and the other electrode is concentric with the central portion, has a width to be wire-bonded, and has the same width as the one of the second electrode. A semiconductor light emitting device provided around the entire periphery of an electrode. 【請求項２】 前記他方の電極の幅が５０〜１５０μｍ
である請求項１記載の半導体発光素子。2. The width of the other electrode is 50 to 150 μm.
The semiconductor light emitting device according to claim 1, wherein
JP1122597A 1997-01-24 1997-01-24 Semiconductor light emitting device Pending JPH10209496A (en)

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