JPH0837239A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent depletion in gates due to draw-out of impurities by a polycide layer by positioning a n-type polysilicon layer of a high impurity concentration above the p- and n-type gates, and connecting these gates with each other. CONSTITUTION:A p-type well and a n-type well are formed on a silicon substrate 1, and a selective oxide film 2 is formed for element isolation. Then a gate oxide film 3 is formed, and subsequently a polysilicon layer 4 is formed for dual gate formation. Thereafter, a polysilicon layer 5 doped with n-type impurities at high concentration is formed thereon. This prevents depletion in the gates due to impurities being drawn out of the gates or being diffused. As a result, it is possible to reduce gate resistance and gate contact resistance, which obtains high speed devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for an integrated circuit or the like, and more particularly to a P-channel transistor having a P-type polysilicon gate electrode and an N-type polysilicon gate electrode. The present invention relates to a semiconductor device in which N-channel transistors are adjacent to each other with an element isolation oxide film interposed therebetween, that is, a CMOS semiconductor device having a so-called dual gate structure.

[0002]

2. Description of the Related Art In semiconductor devices, there is a great demand for miniaturization of circuit patterns, and technical development for this is being advanced, but on the other hand, there are many problems associated with miniaturization. . As one of them, there is a so-called narrow channel effect in which the effective channel region of the transistor is narrowed and the threshold value is lowered with miniaturization, and particularly in a so-called sub-harf micron process in which the design rule is 0.5 micron or less. , The effect is remarkable.

In order to solve such a problem, CMOS
It is effective to make the surface type of both the P-channel type transistor and the N-channel type transistor which form the transistor, and as a means for realizing this, the gate of the P-channel type transistor is used as the gate of the P-channel type transistor. There is known a transistor structure having a so-called dual gate for introducing N-type impurities into the gate.

In this case, an ion implantation method is generally used as the impurity introduction method. According to this method, the conventional N
+ Gate (phosphorus diffusion gate by phosphorous glass deposition)
The resistance of the gate electrode is higher than that of (g). On the other hand, B (boron) is used as a low resistance material (donor) in the formation of the P-type gate, but it is a solid solution in silicon as compared with the N-type material As (arsenic) or P (phosphorus). Since the limit is low, the resistance of the gate electrode also increases. As a result, the resistance value of the gate of the transistor having the dual gate is generally higher than the resistance value of the conventional N + gate by about one digit, and the basic performance of the transistor such as a decrease in the operating speed. Was causing deterioration.

[0005]

As a technique for solving such a problem, polycide and salicide gate methods are widely used in which a silicide layer is formed on both gates to reduce contact resistance and gate resistance. It is used.
As a result, both the P-type gate and the N-type gate can be ohmic-junctioned, so that the threshold voltage shift can be prevented and the operation speed can be increased. Here polycide
In the case of using titanium, as a material thereof, WSix (tungsten silicide) or W (tungsten) having a high melting point and a high corrosion resistance is effective.

However, since the silicide portion of these polycide gates generally has a large diffusion coefficient with respect to the implanted impurities, impurities (particularly B) are sucked out from the polysilicon gate, and further, they are mutually diffused into both gates. However, there is a problem that it causes it (see Japanese Patent Laid-Open No. Hei 2-5422). As a result, the gate is depleted, which seriously adversely affects the basic performance of the transistor, such as fluctuations in the threshold voltage of the transistor and a decrease in operating speed.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and its object is to prevent depletion of the gate due to absorption of impurities from the polycide layer.
The purpose of this is to reduce the gate resistance. A further object of the present invention is to avoid the generation of PN barriers in the gate and upper layers and reduce the wiring resistance. Consequently, the present invention aims to provide a semiconductor device which realizes high integration, high speed and high reliability.

[0008]

In order to solve the above-mentioned problems, according to the present invention described in claim 1, in a semiconductor device having a dual gate, a dual gate
It is characterized in that an N-type polysilicon layer having a high impurity concentration is provided as an upper layer of the dual gate to connect the gates to each other, and the P-type gate and the N-type gate are connected to each other.

According to the second aspect of the present invention, the refractory metal layer or the refractory metal silicide layer is provided only between the N-type polysilicon layer and the P-type gate forming the dual gate. It is characterized by having.

Further, the present invention according to claim 3 is characterized in that a refractory metal layer or a refractory metal silicide layer having high corrosion resistance is provided on the N-type polysilicon layer.

In addition, the present invention described in claim 5 is characterized by including the following steps. (1) A step of forming a polysilicon film for forming a well on a silicon substrate, element isolation, channel doping, gate oxide film formation, and dual gate formation; (2) N by a photolithography technique. Masking the channel type transistor region and introducing impurities into the P channel type transistor region; (3) forming a thin refractory metal or refractory metal silicide layer; A step of removing the refractory metal or refractory metal silicide layer together with a mask on the N-channel transistor region by lift-off method, (5) high concentration N
Forming a polysilicon layer into which a type impurity is introduced,
(6) A step of forming a gate pattern by a known photoengraving technique and etching technique, (7) a gate, a source and a drain region for each of the P-channel type transistor and the N-channel type transistor. A step of simultaneously performing ion implantation for formation.

[0012]

According to the first aspect of the present invention, in a semiconductor device having a dual gate, P constituting the dual gate is used.
Since the N-type polysilicon layer having a high impurity concentration is provided on the upper layers of both the N-type and N-type polysilicon gates to connect both the gates, depletion of the gates due to impurity extraction is prevented, and the gates are also combined. It is possible to obtain a semiconductor device having a reduced resistance.

According to the second aspect of the invention, the refractory metal layer or refractory metal silicide layer is further provided only between the N-type polysilicon layer and the P-type gate constituting the dual gate. In addition to the effect of the first aspect of the invention, it is possible to prevent the generation of the PN barrier due to the existence of the PN junction.

According to the invention of claim 3, a refractory metal layer or refractory silicide layer having high corrosion resistance is further provided on the N-type polysilicon layer. The wiring resistance can be further reduced.

Further, according to the invention of claim 5, claim 2
5. The method for manufacturing a semiconductor device according to claim 4, wherein the resist on the N-type transistor at the time of introducing the impurities into the P-type transistor is removed by a lift-off method of the refractory metal layer or refractory silicide layer in a subsequent step. Since it can also be used as a resist for the above, it is possible to provide a method for manufacturing the semiconductor device with fewer steps.

[0016]

【Example】

<Embodiment 1> Hereinafter, the present invention will be described with reference to a preferred first embodiment. FIG. 1 shows a process for manufacturing a semiconductor device which is a first embodiment of the present invention. The manufacturing method for forming such a semiconductor device is as follows.

(1) By a known method, the silicon substrate 1
P-type and N-type wells are formed on the well, and a selective oxide film 2 for element isolation is formed. Next, channel doping to the silicon substrate 1 for threshold setting is performed, and then the gate is formed.
The oxide film 3 is formed. Subsequently, a polysilicon layer 4 for forming a dual gate is formed to a film thickness of 1500 to 2500Å (FIG. 1 (a)).

(2) Subsequently, a polysilicon layer 5 into which a high concentration N-type impurity (for example, P or As) is introduced is formed on the upper portion thereof. For example, by the CVD method, 1 × 10 ²⁰ to 1 × 10
Polysilicon layer with ²¹ / cm ³ P introduced simultaneously is 500-100
It is formed with a film thickness of 0Å. Furthermore, this polysilicon layer 5
In addition, by the known photoengraving technology and etching technology,
A top pattern is formed (FIG. 1 (b)).

(3) Next, for each of the P-type channel transistor and the N-type channel transistor, ion implantation for forming a gate, a source and a drain region is simultaneously performed. At this time, the implantation energy of BF ₂ ions into the P-type channel transistor is 30 to 80 keV, and the implantation dose amount is 2 × 10 ¹⁵ to 1 × 10 ¹⁶ . Here, since the polysilicon film 5 has a high concentration of the introduced N-type impurities, its conductivity type does not change even if such P-type impurities are introduced.
On the other hand, the implantation energy of As ions into the N-type channel transistor is 40 to 120 keV, and the implantation dose is 3 × 10 ¹⁵ to 2 ×.
It is 10 ¹⁶ / cm ³ . Further, here, the activation of impurities is set to R
It performed using a TA (R apid- T hermal- A nealing ) method. The condition at this time is 1000 ° C. for 10 to 30 seconds (FIG. 1 (c)).

(4) After that, a side wall 6 for forming an LDD structure is formed if necessary, and an interlayer film, a contact, and a wiring layer are formed by a known method to obtain a desired structure. A transistor having a dual gate structure is obtained. (Fig. 1 (d))

The characteristics of the transistor obtained by the above manufacturing method were evaluated. The result of measuring the gate contact resistance was 50 to 100 (Ωcm □). This value is about 1/10 of the value without the polysilicon layer 5 into which the high-concentration N-type impurity is introduced, and it can be seen that the gate contact resistance is reduced. Further, this value is about an order of magnitude larger than that of the polycide gate, but is a negligible difference in comparison with the wiring resistance in the semiconductor device based on the design rule of subharf micron to quarter micron.

Further, in the structure of this embodiment, remarkable impurity diffusion (particularly B) such as suction of gate impurities by silicide and mutual diffusion between dual gates through silicide cannot occur. Since there is concern about the diffusion of impurities (particularly B) between the P-type gate and the polysilicon layer in which the N-type impurity of the upper layer is introduced, its confirmation was also performed. When SIMS analysis of impurities in the gate of this example was performed, it was found that the P-type implantation region (the interface between the polysilicon layer doped with N-type impurities and the P-type gate and between the P-type gate and the silicon oxide film). B concentration (including near interface) is 0.5 to 1.5 ×
It was about 10 ²⁰ / cm ³ .

No penetration of impurities into the substrate was observed, and no diffusion of B into the polysilicon layer region into which the N-type impurity was introduced was observed. This is considered to be the suppressing effect by P (the same applies to As) in the polysilicon layer region into which the N-type impurity has been introduced, that is, the occurrence of remarkable gate depletion due to B deficiency is suppressed. be able to. However, in order to avoid the gate depletion of the P-type transistor, B implantation for P + gate formation is performed.
It is preferable to do this before forming the top pattern. This increases the photolithography process once, but
Impurity implantation energy and drain for drain formation
This is because the amount of gap can be minimized and the source / drain can have a shallow junction.

Further, the P between the P-type layer and the N-type layer above it.
The N barrier (depletion layer due to the PN junction) was evaluated. N on the upper layer
Comparison was made between a single P-type transistor and an N-type transistor, which were manufactured under the same conditions except that the mold layer was not provided, and this example. As a result, there was no difference in N-type transistor characteristics, and in the P-type transistor, the difference in threshold voltage was about 0.1 to 0.2V. This difference does not cause a problem of absorption degree by optimizing the manufacturing process conditions, and thus, the remarkable PN barrier and gate depletion which are the effects of the present invention are avoided. Was confirmed.

<Second Embodiment> The present invention will be described below with reference to a preferred second embodiment. FIG. 2 shows steps for manufacturing a semiconductor device according to the second embodiment of the present invention. The manufacturing method for forming such a semiconductor device is as follows.

(1) By a known method, the silicon substrate 1
P-type and N-type wells are formed on the well, and a selective oxide film 2 for element isolation is formed. Next, channel doping to the silicon substrate 1 for threshold setting is performed, and then the gate is formed.
The oxide film 3 is formed. Then, a polysilicon film 4 for forming a dual gate is formed with a film thickness of 1500 to 2500Å (FIG. 2A).

(2) Next, a resist 9 is formed on the N-type region using a known photolithography technique, and then impurities are implanted to form the P-type gate of the P-channel transistor.
Here, B is an injection energy of 10 to 30 keV and a dose amount of 3 to 5
Inject x10 ¹⁵ / cm ³ (Fig. 2 (b)).

(3) Subsequently, a thin refractory metal or refractory metal silicide layer 10 is formed. Here, WSi
Is formed with a film thickness of about 200 Å by the sputtering method (FIG. 2C). This layer is not for connecting both gates, but for preventing formation of a PN barrier (PN junction) between the P-type gate and the N-type layer above it. is there.

(4) After that, the refractory metal or refractory metal silicide layer 9 (here, W
The Si layer) is removed by the lift-off method (FIG. 2).
(d)). Regarding the method of removing the thin refractory metal or refractory metal silicide layer 9 that is thin in the upper portion of the N-type region in this step, after forming the thin film before forming the resist, the P-type transistor region is formed by a known photoengraving technique. After forming a resist pattern on the top, use this as a mask for N
Alternatively, the refractory metal or refractory metal silicide layer above the type transistor region may be removed by etching. Although such a method is more common, the method described above is employed here because the resist 9 can be used for implanting impurities into the P-type gate and the photolithography process can be reduced. The lift-off method is effective for thin films.

(5) Subsequently, a polysilicon layer 5 into which a high concentration N-type impurity (for example, P or As) is introduced is formed on the upper portion thereof. For example, by the CVD method, 1 × 10 ²⁰ to 1 × 10
Polysilicon layer with ²¹ / cm ³ P introduced simultaneously is 500-100
It is formed with a film thickness of 0Å. Furthermore, this polysilicon layer 5
In addition, by the known photoengraving technology and etching technology,
A top pattern is formed (FIG. 2 (e)).

(6) Finally, for each of the P-channel type transistor and the N-type channel transistor,
Ion implantation for gate, source, and drain region formation is performed simultaneously. At this time, the implantation energy of BF ₂ ions into the P-channel type transistor is 20 to 30 kev, and the implantation dose amount is 3 × 10 ¹⁵ / cm ³ . On the other hand, the implantation energy of P ions into the N-channel transistor is 30 to 40 ke.
v, injection dose is 5 × 10 ¹⁵ / cm ³ . Further, activation of impurities is performed by using the RTA method. The condition at this time is 1000
C is -10 to 30 seconds. After that, a side wall 6 for forming an LDD structure is formed, if necessary, and an interlayer film, a contact, and a wiring layer are formed by a known method to form a transistor having a desired dual gate structure. Is obtained (FIG. 2 (f)).

The characteristics of the transistor obtained by the above manufacturing method were evaluated. The result of measuring the gate contact resistance was 50 to 100 (Ωcm □). This value is about 1/10 of the value without the polysilicon layer 5 into which the high-concentration N-type impurity is introduced, and it can be seen that the gate contact resistance is reduced. Further, this value is about an order of magnitude larger than that of the polycide gate, but is a negligible difference in comparison with the wiring resistance in the semiconductor device based on the design rule of subharf micron to quarter micron.

Next, SIMS analysis of impurities in the gate revealed that the B concentration in the P-type implantation region (including the vicinity of the interface between the P-type gate and the silicon oxide film) was 0.8 to 2 × 10. ²⁰ / cm ³
As a result, gate B implantation further reduces the concern of gate depletion. Further, similar to Example 1, almost no penetration of impurities into the substrate was observed, and no diffusion of B into the N-type region was observed. Next, the characteristics of the transistor of this example and the single P-channel transistor and N obtained by making the other forming conditions the same without providing the N-type layer as the upper layer and the N-type transistor
When compared with the characteristics of the channel type transistor, no difference was found. That is, due to the presence of the refractory metal or the refractory metal silicide layer, the gate depletion is further improved as compared with the first embodiment, and the PN barrier (PN junction) formation is sufficiently prevented. It was confirmed.

<Third Embodiment> The present invention will be described below with reference to a preferred third embodiment. FIG. 3 shows a semiconductor device according to the present invention. The manufacturing method for forming such a semiconductor device is as follows.

(1) From the formation of P-type and N-type wells on the silicon substrate 1 by the same method as in Example 2, N-type wells are formed.
Processes up to the removal of the refractory metal or refractory metal silicide layer 10 on the upper part of the mold region are performed (FIG. 3A to FIG.
(d)).

(2) Then, in the same manner as in Example 2, a high concentration N-type impurity (for example, P or A) is formed on the upper portion thereof.
A polysilicon layer 5 containing s) is formed. Further, after forming a refractory metal or refractory metal silicide layer 11 (for example, WSix) on the upper layer by sputtering, a CVD method or the like, by a known photoengraving technique or etching technique,
A gate pattern is formed (FIG. 3 (e)).

(3) Finally, the ion implantation for forming the gate, source and drain regions is simultaneously performed for each of the P-channel type transistor and the N-type channel transistor by the same method as in the second embodiment. To do. After that, a side wall 6 for forming an LDD structure is formed, if necessary, and an interlayer film, a contact, and a wiring layer are formed by a known method to form a transistor having a desired dual gate structure. Is obtained (FIG. 3 (f)).

The gate resistance of the semiconductor device obtained by the above manufacturing method was about 1/10 of that of the semiconductor device of the second embodiment. That is, the gate contact resistance is improved by about two orders of magnitude as compared with the case where only the implantation gate is used. Further, the characteristics of the transistor were almost the same as those of the second embodiment, and it was confirmed that the gate depletion and the PN barrier were sufficiently prevented. As described above, in the invention of the third embodiment, the high-concentration layer of the N-type impurity, which is the intermediate layer, functions as a barrier, and the refractory metal silicide (WSi or the like) is directly injected between the gates (dual gate). Since it is not used for the above, there is no problem such as absorption of impurities from the gate electrode. The effect of this semiconductor device is expected to be particularly remarkable as a technique for increasing the speed in an integrated circuit of a design rule of quarter micron or less.

In any of the embodiments, the manufacturing method described above is an example for obtaining the semiconductor device of the present invention, and is not limited to these. That is, the components described in the above-mentioned embodiments can be freely combined without departing from the spirit of the present invention.

[0040]

As described above, according to the semiconductor device of the present invention described in claim 1, in the semiconductor device having the dual gate structure effective for preventing the narrow channel effect,
Gate by sucking out impurities from the gate or diffusing impurities
Depletion can be prevented. By this
Since the gate resistance and the gate contact resistance can be reduced, the speed of the device can be increased. Further, according to the present invention described in claim 2, depletion of the gate can be prevented more reliably, and formation of a PN barrier between the dual gates (depletion layer of the PN junction) is prevented. Therefore, the transistor characteristics can be improved. Furthermore, according to the present invention as set forth in claim 3, a semiconductor device further enhancing the above effects can be obtained, so that the transistor characteristics can be further improved. In addition, according to the invention of claim 5, in the method of manufacturing a semiconductor device according to any one of claims 2 to 4, the resist on the N-type transistor at the time of introducing impurities into the P-type transistor has a high melting point in a subsequent step. Since it can also be used as a resist for removing the metal layer or the refractory silicide layer by the lift-off method, it is possible to provide a method for manufacturing the semiconductor device with fewer steps.
That is, according to the present invention described above, it is possible to provide a semiconductor device that achieves high integration, high speed, and high reliability.

[0041]

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

[Explanation of symbols]

1 Silicon Substrate 2 Selective Oxide Film 3 Gate Oxide Film 4 Polysilicon Film 5 Polysilicon Film with N-type Impurity 6 Sidewall 9 Resist 10, 11 Refractory Metal or Refractory Metal Silicide Layer

Claims (5)

[Claims] 1. A semiconductor device comprising a P-channel type transistor having a P-type polysilicon gate electrode and an N-channel type transistor having an N-type polysilicon gate electrode. A semiconductor device comprising an N-type polysilicon layer having a high impurity concentration as an upper layer of the gate and connecting both the P-type gate and the N-type gate. 2. A semiconductor device according to claim 1, wherein a refractory metal layer or a refractory metal silicide layer is provided only between the N-type polysilicon layer and the P-type gate. 3. The semiconductor device according to claim 1, further comprising a refractory metal layer or a refractory silicide layer having high corrosion resistance on the N-type polysilicon layer. 4. The semiconductor device according to claim 1, wherein the concentration (carrier concentration) of the N-type polysilicon layer is 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^3. . 5. A method of manufacturing a semiconductor device, comprising the following steps. (1) A step of forming a polysilicon film for well formation, element isolation, channel doping, gate oxide film formation, and dual gate formation on a silicon substrate, (2) N by photolithography Masking the channel type transistor region and introducing impurities into the P channel type transistor region; (3) forming a thin refractory metal or refractory metal silicide layer; A step of removing the melting point metal or the refractory metal silicide layer together with a mask on the N-channel type transistor region by a lift-off method; (5) a step of forming a polysilicon layer into which a high concentration N-type impurity is introduced; Forming a gate pattern by the photoengraving technology and etching technology of (7) P-channel transistor and For each channel transistors, gate - DOO, source - scan, and simultaneously process the ion implantation for the drain regions.