JPH02153538A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce gate-induced leakage current in a drain by a method wherein high-concentration source and drain regions are formed by an ion-implantation using an oxide film formed on the sidewall parts of the gate as a mask. CONSTITUTION:A field oxide film 2 is formed on a P-type silicon substrate 1 and thereafter, a gate insulating film 3 and a poly silicon film 4 are formed and moreover, a non-oxidizable nitride film 5 is deposited on the film 4 to form a gate. Then, an oxide film 6 is formed on the sidewall parts of the gate using the film 5 as a mask. Moreover, arsenic ions are implanted using the films 5 and 6 as masks to form high-concentration source and drain regions 7. Then, after the films 5 and 6 are removed, phosphorus ions are ion-implanted by an obliquely rotational implantation method to form low-concentration source and drain regions 8. Thereby, the overlap of the gate ends with the high- concentration source and drain region ends is prevented and gate-induced leakage current in a drain is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing an insulated gate field effect semiconductor device having a structure (hereinafter referred to as LDD).

[Conventional technology]

FIGS. 4A to 4C are cross-sectional views showing the main stages of a conventional method for manufacturing a semiconductor device of this type. (
(See Japanese Patent Application No. 60-43951 and Japanese Patent Application No. 60-43952). In these figures, 21 is a p-type silicon substrate, 22 is a field oxide film, 23 is a gate insulating film, and 24 is a p-type silicon substrate.
25 is a photoresist, 26 is a low concentration source/drain region (n-layer),
27 is a highly doped source/drain region (n'' layer).

Next, the manufacturing process will be explained.

First, as shown in FIG. 4(a), a p-type silicon substrate 2
After forming a field oxide film 22 on the first nitride film 22, a first nitride film made of Si3N4 is deposited as a gate insulating film 23 with a thickness of about 200%.
Form people. Next, as a gate electrode material for forming a gate electrode, polysilicon 24 was deposited using a CVD method.
After doping the polysilicon 24 with an impurity such as P (phosphorus) to make it conductive,
Gate voltage tiTa iI using photoresist 25
Buttering is done so that areas remain. Next, using the patterned photoresist 25 as a mask, the polysilicon 24, which is the gate electrode material, is etched by RIE or the like to form a gate electrode 24G (FIG. 4(b)).
. Thereafter, the photoresist 25 is removed, and using the gate electrode 24G as a mask, P ions are implanted into the p-type silicon substrate 1 at an angle of approximately 45 degrees from the vertical direction, as shown in FIG. 4(b). , a low concentration source/drain region (n- layer) 26 is formed. Then, as shown in FIG. 4(C), As (arsenic) is implanted by normal vertical ion implantation, and the high concentration source/drain region (n4- layer) 27
is formed to obtain an LDD structure.

(Problems to be Solved by the Invention) The LDD structure obtained by the conventional manufacturing method as described above has a gate voltage tf! Since the end of 24a overlaps the high concentration source/drain region 27 which is the n1 layer, when the gate insulating film 23 becomes thinner, tunneling occurs between bands in the depleted drain in the overlap region. , there was a problem that drain leakage current occurred (for details, see T, Y, Chan, J, Ch.
en, P., Ko and C.) Iu.

1987 IEDM Technical Diges
t, p, 718. (See Japanese Patent Application Laid-Open No. 61-101077, etc.).

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce gate-induced drain leakage current of the resulting semiconductor device.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes forming a gate having a gate insulating film on a conductive semiconductor substrate, a polycrystalline silicon film serving as a gate electrode on the gate insulating film, and an oxidation-resistant insulating film on the gate insulating film. a step of forming an oxide film on the gate sidewalls using the insulating film as a mask, and a step of ion-implanting impurities of a conductivity type different from that of the semiconductor substrate using the oxidation-resistant insulating film and the oxide film on the gate sidewalls as masks. After removing the insulating film and the oxide film on the side walls of the gate, impurity ions of a conductivity type different from that of the semiconductor substrate are obliquely implanted using the gate as a mask. The method includes a step of forming a low concentration region of the drain.

Further, in the above, the lightly doped source/drain regions may be formed first, and then the highly doped source/drain regions may be formed.

[Effect]

In the method for manufacturing a semiconductor device according to claim (1) of the present invention, the high concentration regions of the source and drain are formed by oblique rotational ion implantation using the gate as a mask.
The high concentration region of the drain is formed by ion implantation using an oxide film and an insulating film as masks, with an oxide film formed on the gate sidewalls, so that the overlap between the gate end and the end of the high concentration region of the source/drain is prevented. Prevented.

In the method for manufacturing a semiconductor device according to claim (2) of the present invention, the low concentration source/drain regions are formed by ion implantation, the high concentration source/drain regions are formed by ion implantation using the gate as a mask, Thereafter, an oxide film is formed on the side walls of the gate, thereby shortening the gate and preventing the gate end from overlapping with the end of the high concentration region of the source/drain.

〔Example〕

FIGS. 1A to 1C are cross-sectional views showing the main steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention.

In these figures, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate insulating film, 4 is a polycrystalline silicon film, 5 is a nitride film, 6 is an oxide film, and 7 is a high concentration source/drain region ( 8 is a low concentration source/drain region (n" layer).

Next, the manufacturing process will be explained.

First, as shown in FIG. 1(a), a field oxide film 2 is formed on, for example, a p-type silicon substrate 1, and then a gate insulating film 3 made of, for example, an oxide film and a polycrystalline silicon film 4 that will become a gate electrode are formed. After that, add LPCV on top of that.
An oxidation-resistant nitride film 5, for example, is deposited by method D and photoetched to form a gate. Next, as shown in FIG. 1(b), nitrided D! 5 as a mask, heat treatment is performed to form an oxide film 6 on the gate sidewalls. Then, using the nitride film 5 and the oxide film 6 on the gate side wall portion 6 as a mask,
For example, arsenic ions As are implanted at 4×10” (cm−2) to form high concentration source/drain regions 7. Next, the first
As shown in Figure (C), after removing the nitride film 5 and the oxide film 6 on the gate sidewalls, for example, phosphorus ions P are
The LDD structure is obtained by performing oblique rotational ion implantation at an angle of about 45 degrees from the vertical direction at an implantation dose of 1.5 cm -2 to form low concentration source/drain regions 8.

Although not shown below, the device is completed by performing processes such as opening contact windows and wiring electrodes. Here, if, for example, an oxidation-resistant 5NOS structure (oxide film + nitride film) is adopted as the gate insulating film 3, it is more effective because only the gate sidewalls are oxidized.

Further, in the above embodiment, the highly doped source/drain regions 7 are formed first, but it is also possible to form the lightly doped source/drain regions 8 first.

An example in this case will be explained with reference to FIGS. 2(a) to (d). First, as shown in FIG. 2(a), as shown in FIG.
After forming a field oxide film 2 on a P-type silicon substrate 1 in the same manner as above, a gate insulating film 3 made of a nitride film, a gate made of a polycrystalline silicon film 4 and a nitride film 5 is formed, and the nitride film 5 is masked. The low concentration source/drain regions 8 are formed by ion implanting a low concentration n-type impurity such as P using oblique rotational ion implantation. Next, as shown in FIG. 2(b), the nitride film 5 is used as a mask and exposed to a high temperature oxidizing atmosphere to form an oxide film 6 on the gate sidewalls. As as a mask
A high concentration n-type impurity such as the like is ion-implanted to form a high concentration source/drain region 7 to obtain an LDD structure.

With this method, there is no need to remove the oxide film 6 on the side walls of the gate during ion implantation in the subsequent process, and there is no reduction in the thickness of the field oxide film 2.

Further, the nitride film 5 on the polycrystalline silicon film 4 serving as the gate electrode and the nitride film 5 on the high concentration source/drain region 7 are removed, and further, as shown in FIG.
By depositing 9 by sputtering and subjecting it to heat treatment, the gate electrode portion and the high concentration source/drain regions 7 can be silicided and their resistance can be lowered. However, since the gate sidewall part has an oxide film 6, it is not silicided, and by removing unreacted Ti9, the gate electrode and high concentration source/drain regions are formed in the self-alignment line as shown in FIG. 2(d). A silicide portion 10.11 can be formed at 7. Note that the ion implantation for forming the high concentration source/drain regions 7 is as follows:
SALICIDE: Selfaligne
It is also possible to carry out the process after forming the d5ilicide structure.

Furthermore, although the above two embodiments have described the method of manufacturing an N-channel insulated gate electrode effect semiconductor device, by changing the p-substrate to an n-substrate and replacing the n-type impurity ions to be implanted with p-type impurity ions, it is possible to It is also applicable to channel insulated gate field effect semiconductor devices.

By the way, when creating a CMOS in the above embodiment, it is necessary to use photoresist or the like to limit the source/drain ion implantation region, but high temperature heat treatment is required between low concentration and high concentration ion implantation. If there is, there is a problem that the number of times of patterning the photoresist increases.

However, according to the method described below, it becomes possible to simultaneously perform low-concentration and high-concentration implantation of the source and drain.

That is, first, as shown in FIG. 3(a), after patterning a photoresist 12 for forming a gate electrode, a nitride film 5. After etching the polycrystalline silicon film 4 by RIE, the photoresist 12 is removed. Next, in order to form n-type source/drain regions, a photoresist 13 is used and patterned to cover other regions. Thereafter, as shown in FIG. 3(b), the photoresist 13. Using polysilicon 4 and nitride film 5 as masks, n-type impurities,
For example, the low concentration source/drain regions 8 are created by performing oblique rotational ion implantation of P at an angle of 45° from the vertical direction. Next, as shown in FIG. 3(e), for example, As is rotationally injected at an angle of about 7° from the vertical direction (to prevent channeling).
By forming the highly doped source/drain regions 7, an n-type LDD structure is formed. Then, after this, Figure 2 (d
), an oxide film 6 is formed on the side walls of the gate,
The overlap of the high concentration source/drain regions 7 is eliminated. In addition, the p-type source and drain in the n-well 14 are also L
If a DD structure is used, it can be created in a similar manner. Furthermore, as shown in FIG. 3(e), it is also possible to use a salicide structure. The reason for implanting ions at an angle of approximately 7° as described above is that when implanting ions at an angle of 0° onto a St substrate without an oxide film 6 as usual, the implantation occurs in the crystal lattice of a channeling ((ioo) or (111) substrate). The implantation angle is thus tilted by about 7 degrees because a phenomenon occurs in which ions do not collide and the ions implanted there are deeply implanted.

[Effects of the Invention] As explained above, the method for manufacturing a semiconductor device according to claim (1) of the present invention includes a gate insulating film on a semiconductor substrate of one conductivity type, and a polycrystalline silicon film serving as a gate electrode on the gate insulating film. , a step of forming a gate with an oxidation-resistant insulating film thereon, a step of forming an oxide film on the gate sidewalls using the insulating film as a mask, and a step of oxidizing the oxidation-resistant insulating film and the gate sidewalls. Using the film as a mask, impurities of a conductivity type different from that of the semiconductor substrate are ion-implanted to form high concentration regions of the source and drain. After removing the insulating film and the oxide film on the side walls of the gate, the semiconductor substrate is implanted using the gate as a mask. This process includes the step of obliquely rotationally implanting impurity ions of a conductivity type different from that of the substrate to form low concentration regions of the source/drain, so that the gate edge and the edge of the source/drain region do not overlap. This has the effect of reducing induced drain leakage current. In addition, an LD in which only the low concentration regions of the gate and source/drain overlap
Since it has a D structure, gate capacitance is reduced.

Further, in the method for manufacturing a semiconductor device according to claim (2) of the present invention, after forming the low concentration source/drain regions first,
Since highly doped source/drain regions are formed, there is an advantage in addition to the effects of the above-mentioned aspect (1) that there is no need to remove the oxide film on the side walls of the gate during ion implantation.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining one embodiment of the present invention;
2 and 3 are cross-sectional views for explaining other embodiments of the present invention, and FIG. 4 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device having an LDD structure. In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate insulating film, 4 is a polycrystalline silicon film, 5 is a nitride film, 6 is an oxide film, 7 is a high concentration source/drain region, and 8 is a Low concentration source/drain regions, 9 Ti, 10.
11 is a silicide part, 12.13 is a photoresist, 1
4 is an n-well. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A step of forming a gate having a gate insulating film on a semiconductor substrate of one conductivity type, a polycrystalline silicon film to serve as a gate electrode on the gate insulating film, and an oxidation-resistant insulating film on the gate insulating film, and the insulating film forming an oxide film on the gate sidewall using the oxidation-resistant insulating film and the oxide film on the gate sidewall as a mask, and ion-implanting an impurity of a conductivity type different from that of the semiconductor substrate to form the source and drain. After removing the insulating film and the oxide film on the side walls of the gate, impurity ions of a conductivity type different from that of the semiconductor substrate are obliquely ion-implanted into the source region using the gate as a mask. 1. A method of manufacturing a semiconductor device, comprising the step of forming a low concentration region of a drain. (2) A step of forming a gate having a gate insulating film on a semiconductor substrate of one conductivity type, a polycrystalline silicon film to serve as a gate electrode on the gate insulating film, and an oxidation-resistant insulating film on the gate insulating film, and forming the gate. forming low concentration regions of the source and drain by obliquely rotating ion implantation of impurities of a conductivity type different from that of the semiconductor substrate into the source and drain regions as a mask;
a step of forming an oxide film on the gate sidewall using the oxidation-resistant insulating film as a mask; a step of ion-implanting impurities of a conductivity type different from that of the semiconductor substrate to form high concentration regions of the source and drain; 1. A method for manufacturing a semiconductor device, comprising the step of removing an oxidation-resistant insulating film and a gate insulating film in source/drain regions.