JPH0823094A - Compression bonded high withstanding voltage semiconductor device - Google Patents

Abstract

PURPOSE:To prevent post electrode-control electrode coupled parts from being shorted by insulatively placing a control electrode and control electrode interconnection board on a bottom face of a recess formed at a second main electrode forming region and extending a part of a second main electrode disposed outside the recess to the bottom face of the recess. CONSTITUTION:A recess 17 is formed at an emitter electrode forming region, gate electrode interconnection board 10 is disposed on a bottom face of the recess 17 and an emitter electrode 9 is extended from outside of the recess 17 to the bottom face thereof. A second oxide film 11 on the electrode 9 is etched off to remove only the film 11 covering a part of the electrode 9 disposed outside the recess, with leaving the film 11 covering other part extending to the bottom face of the recess. This prevents a gate electrode 6 or gate electrode interconnection board from contacting with a post electrode to result in short circuit at compression bonding of the exposed part of the emitter electrode with the post electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type high breakdown voltage semiconductor device, and more particularly, when the main electrode is pressure-contacted by a post electrode, the post electrode is prevented from being short-circuited to a circuit portion related to a control electrode. The present invention relates to a pressure contact type high withstand voltage semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a high breakdown voltage semiconductor device uses a module structure in which each electrode terminal of the high breakdown voltage semiconductor device is connected to an external electrode by using wire bonding, soldering, etc. The reliability of the high withstand voltage semiconductor device may decrease due to breakage of the wire bonding portion or cracking of the solder. Therefore, in order to prevent the reliability of the high breakdown voltage semiconductor device from being lowered, relatively recently, the high breakdown voltage semiconductor device is pressure-contacted by a pair of post electrodes, and the pressure contact enables high voltage resistance without using wire bonding or solder. A pressure contact type high breakdown voltage semiconductor device has been developed in which each electrode terminal of the breakdown voltage semiconductor device is electrically connected to an external electrode. An example of such a pressure contact type high breakdown voltage semiconductor device is disclosed in JP-A-3-218643 and JP-A-4-29.
No. 0272, Japanese Utility Model Laid-Open No. 4-131954, Japanese Patent Laid-Open No. 4-3
No. 22471 is disclosed.

FIG. 7 is a plan view showing an example of the configuration of a known pressure contact type high breakdown voltage semiconductor device. FIG. 7 (a) is a plan view showing the overall configuration of the pressure contact type high breakdown voltage semiconductor device, and FIG. FIG. 3 is an enlarged plan view showing a configuration of a range A surrounded by a circle in the configuration, showing an example in which a pressure contact type high breakdown voltage semiconductor device constitutes an insulated gate bipolar transistor (IGBT).

As shown in FIGS. 7A and 7B, a pressure contact type high breakdown voltage semiconductor device 61 includes a plurality of semiconductor active regions 63 separated by a gate electrode wiring board 62 and a pressure contact type high breakdown voltage semiconductor device. It comprises a gate electrode pad 64 provided in a substantially central portion of 61 and a termination region 65 provided so as to surround a plurality of semiconductor active regions 63. In this case, each semiconductor active region 63 is provided with a plurality of emitter electrodes 81 formed in a stripe shape, and a plurality of these emitter electrodes 81 are integrated so that
One semiconductor active region 63 is formed. In this case, the gate electrode wiring board 62 includes the plurality of semiconductor active regions 6
3 is formed in order to control evenly, and has a function of transmitting the gate control signal to the semiconductor active region 63 located away from the gate electrode pad 64 without delay and has a large area pressure contact. It is necessary when forming the high voltage semiconductor device 61 of the die type. The gate electrode wiring board 62 is arranged in a grid pattern on one surface of the pressure contact type high breakdown voltage semiconductor device 61 so as to surround each semiconductor active region 63.

FIG. 8 is a sectional view showing an example of a known pressure contact type package that houses a pressure contact type high breakdown voltage semiconductor device (IGBT).

As shown in FIG. 8, the press-contact type package 67 is provided with buffer plates 68a and 68b respectively arranged on both surface sides of the press-contact type high breakdown voltage semiconductor device 61 and outside the buffer plates 68a and 68b. These buffer plates 68
A pair of post electrodes 69a and 69b that press-contact both surfaces of the pressure-contact type high withstand voltage semiconductor device 61 via a and 68b, and a gate terminal plate 70 provided at the installation position of the gate electrode pad 64 of the press-contact type high-withstand voltage semiconductor device 61. And this gate terminal board 7
A spring member 71 for elastically pressing 0 on the gate electrode pad 64;
The gate lead 72 is electrically connected to the gate terminal plate 70.

The pair of post electrodes 69a and 69b
Is a pressure contact type high breakdown voltage semiconductor device 6 due to their pressure contact.
The gate terminal plate 70 is conductively connected to the collector electrode and the emitter electrode (both not shown) exposed on both surfaces of the gate electrode 1, and the gate terminal plate 70 is provided on one surface of the pressure contact type high breakdown voltage semiconductor device 61 by the spring material 71. Conductively connected to 64.

Subsequently, FIG. 9 shows the C- line shown in FIG.
Pressure contact type high breakdown voltage semiconductor device (IGB
11 is a cross-sectional view showing the cross-sectional structure of (T) 61, and FIG.
FIG. 8 is a sectional view showing a sectional structure of a pressure contact type high breakdown voltage semiconductor device (IGBT) 61 taken along a line DD ′ shown in FIG. 7B.

As shown in FIGS. 9 and 10, the pressure contact type high breakdown voltage semiconductor device 61 includes an n drift layer 73, a p high concentration layer 74 provided on the entire surface of the n drift layer 73, and
The p well layer 75 and the p channel layer 90 selectively provided on the other surface of the n drift layer 73, the two emitter layers 76 selectively provided in the p channel layer 90, and the p well layers 75, p. A gate oxide film 77 provided so as to cover the surfaces of the channel layer 90 and the emitter layer 76, a gate electrode 78 provided on the gate oxide film 77, and a gate electrode 78.
An interlayer insulating film 79 provided so as to cover the collector electrode 80, a collector electrode 80 in low ohmic contact with the entire surface of the p high-concentration layer 74, and the interlayer insulating film 79, and a part of the p well layer 75 and the emitter layer 76. Electrode 81 in low ohmic contact with
(The same as the emitter electrode 81 shown in FIG. 7B) and a gate electrode wiring board 82 which is provided on the interlayer insulating film 79 and a part of which makes a low ohmic contact with the gate electrode 78. Between the one emitter electrode 81 and the next emitter electrode 81, the p well layer 75, the gate oxide film 77,
The gate electrode 78 and the interlayer insulating film 79 are each recessed toward the n drift layer 73 side to form a recessed portion 83, and the gate electrode wiring board 82 is arranged on the bottom surface of this recessed portion 83. In this case, the reason why the recesses 83 are provided between the emitter electrodes 81 and the gate electrode wiring board 82 is arranged on the bottom surface of the recesses 83 is that the exposed surface of each emitter electrode 81 is one post electrode 68a (see FIG. 8), if each emitter electrode 81 and each gate electrode wiring board 82 have the same height, each emitter electrode 81 and each gate electrode wiring board 82 are connected by one post electrode 68a. This is to prevent electrical short circuit.

By the way, the structure of the pressure contact type high breakdown voltage semiconductor device 61 shown in FIG. 9 (hereinafter referred to as the structure of FIG. 9) and the structure of the pressure contact type high breakdown voltage semiconductor device 61 shown in FIG. 10 is different from the structure of FIG. 10 in that the structure of FIG. 10 includes an n drift layer 73, a p high concentration layer 74, ap well layer 75, an emitter layer 76, a gate electrode 78, a collector electrode 80, and an emitter electrode 81. The structure of FIG. 9 is different from that of the structure of FIG. 9 in that the semiconductor active region part 63a is configured. And the structure of FIG. 10 are substantially the same.

Since the operation of the known pressure contact type high breakdown voltage semiconductor device (IGBT) 61 having such a configuration is well known in the art, the operation relating to the known pressure contact type high breakdown voltage semiconductor device 61. The description is omitted.

Next, FIG. 11 shows E shown in FIG. 7 (a).
Pressure contact type high breakdown voltage semiconductor device (IGB
(T) 61 is a cross-sectional view showing the cross-sectional structure of the termination region 65 having a triple guard ring.

As shown in FIG. 11, the termination region 65 includes an n drift layer 73 and an n drift layer 73.
P high concentration layer 74 provided on the entire one surface, three p guard ring regions 84 selectively provided on the other surface of the n drift layer 73, and also similarly provided on the other surface of the n drift layer 73. One n-channel stopper region 85 provided,
An oxide film 86 provided so as to cover the surfaces of the n drift layer 73 and the p guard ring region 84, an interlayer insulating film 79 provided so as to cover the oxide film 86, and an interlayer insulating film 79.
Is provided on the p guard ring region 84 or n
A field electrode 87 made of aluminum in low ohmic contact with the channel stopper region 85, another oxide film 88 provided so as to cover these field electrodes 87, and a discharge provided so as to cover another oxide film 88. And a polyimide resin film 89 for prevention.

The termination region 6 having such a configuration
5 is formed, first, three p guard ring regions 84 and one n channel stopper region 85 are selectively formed on the other surface of the n drift layer 73, and then three p guard rings are formed. N drift layer 73 including each surface of region 84 and one n channel stopper region 85
An oxide film 86 is formed on the other surface. Subsequently, contact holes are formed in the oxide film 86 corresponding to the respective surfaces of the three p guard ring regions 84 and one n channel stopper region 85, and the field electrode 87 is separately formed around these contact hole formation points. To form. Next, another oxide film 88 is formed on the oxide film 86 including these field electrodes 87, the other oxide film 88 on the emitter electrode 81 in the semiconductor active region 63 is selectively removed, and then the termination region is formed. A polyimide resin film 89 is formed on another oxide film 88 of 65 to complete the termination region 65.

The termination region 65 having such a configuration
Is usually provided in order to achieve high breakdown voltage of the semiconductor device, and one or more semiconductor active regions 63 are
It has a structure surrounded by one or more guard ring regions 84. Since the operation of the known termination area 65 is well known in the technical field, the description of the operation of the known termination area 65 will be omitted.

[0016]

In a known pressure contact type high breakdown voltage semiconductor device having a termination region 65,
When manufacturing the termination region 65, after forming the field electrodes 87, the field electrodes 87 are formed.
While a step of forming another oxide film 88 on the semiconductor active region 63 is necessary (in this case, another oxide film 88 is also formed on the emitter electrode 8 of the semiconductor active region 63).
Then, in order to bring the emitter electrode 81 and one post electrode 68a into a low ohmic contact by pressure contact, it is necessary to remove another oxide film 88 formed on the exposed surface of the emitter electrode 81. Will be included.

By the way, in order to remove another oxide film 88 on the surface of the emitter electrode 81, a hydrofluoric acid-based solution is caused to act on the another oxide film 88, and another oxide film on the surface of the emitter electrode 81 is removed. Sufficient time must be etched to completely thaw 88. In this case, if another oxide film 88 remains on the emitter electrode 81 to which one of the post electrodes 68a is pressed,
There is a risk that the remaining oxide film 88 will be destroyed by the pressure contact of one of the post electrodes 68a, and the fragments at the time of destruction will destroy the emitter electrode 81 in the lower layer. In order to completely remove another oxide film 88 on the surface of the emitter electrode 81, in consideration of the processing accuracy of the other oxide film 88, a thickness of at least several μm or more than the thickness of the other oxide film 88 is taken into consideration. An etching process for removing another oxide film 88 is required. Further, not only the surface portion of the emitter electrode 81 but also the portion extending from the surface portion of the emitter electrode 81 toward the recessed portion 83 where the gate electrode wiring board 31 is arranged are removed not only by etching the other oxide film 88. It also needs to be removed.

However, in the known pressure contact type high withstand voltage semiconductor device, the gate oxide film 77, the gate electrode 78, the interlayer insulating film 79, and another oxide film 88 are formed so as to overlap the recessed portion 83, and the recessed portion 83 has a different structure. If the oxide film 88 is oversized in the thickness direction, the interlayer insulating film 79 and the oxide film 77 may be removed at the same time when the other oxide film 88 is etched. At this time, the gate electrode 78 is removed. Are exposed to the outside, and a pair of post electrodes 68a,
When 68b is pressure-welded to the pressure-contact type high breakdown voltage semiconductor device 61,
There is a problem that a short circuit easily occurs between the gate electrode 78 and the emitter electrode 81.

On the other hand, another oxide film 8 is formed on the emitter electrode 81.
It is conceivable that the manufacturing process of the termination region 65 and the manufacturing process of the semiconductor active region 63 may be separated so that 8 is not formed. However, if separate manufacturing processes are used, the manufacturing process of the pressure contact type high breakdown voltage semiconductor device 61 may be performed. However, there is a problem in that the manufacturing cost needs to be increased and the manufacturing equipment needs to be increased.

The present invention is to eliminate the above-mentioned problems, and an object thereof is to short-circuit between the second main electrode and the control electrode when the first and second main electrodes are pressed by the pair of post electrodes. It is an object of the present invention to provide a pressure contact type high withstand voltage semiconductor device that does not cause the above-mentioned problems and does not increase the manufacturing process.

[0021]

In order to achieve the above object, the present invention provides a semiconductor active region having one or more pn junctions, and an external exposure provided on one surface side of the semiconductor active region. A first main electrode having a surface, a second main electrode having an externally exposed surface provided on the other surface side of the semiconductor active region, and a second main electrode provided on the other surface side, and each is externally insulated by an insulating layer. A control electrode and a control electrode wiring board conductively connected to the control electrode, and one or more guard rings on the other surface side of the semiconductor active region, the guard ring being disposed so as to surround the semiconductor active region. The post electrodes are pressed against the externally exposed surfaces of the first and second main electrodes, and the terminal electrode plate is pressed against the control electrode pads conductively connected to the control electrode wiring board. Main train In the pressure contact type high breakdown voltage semiconductor device for conducting conductive connection between the post electrode and the control electrode pad corresponding to the terminal electrode plate, the second main electrode on the other surface side of the semiconductor active region is not arranged. A recess is formed in a portion, the control electrode and the control electrode wiring board are respectively disposed on the bottom of the recess in an insulating manner, the second main electrode is disposed outside the recess, and a part of the bottom is formed on the bottom of the recess. A first means extending to the portion is provided.

In order to achieve the above object, the present invention further comprises a semiconductor active region having one or more pn junctions,
A first main electrode having an externally exposed surface provided on one surface side of the semiconductor active region, a second main electrode having an externally exposed surface provided on the other surface side of the semiconductor active region, and the other And a control electrode wiring board which is respectively provided on the front surface side of the semiconductor active area and is externally insulated by an insulating layer, and a control electrode wiring board conductively connected to the control electrode, and the semiconductor active area on the other surface side of the semiconductor active area. A control electrode, which is composed of one or more guard rings disposed so as to surround the control electrode, presses the post electrodes to the externally exposed surfaces of the first and second main electrodes, and is conductively connected to the control electrode wiring board. The terminal electrode plate is pressed onto the pad, and the first,
In a pressure contact type high breakdown voltage semiconductor device for conducting conductive connection between the terminal electrode plate and the post electrode corresponding to the second main electrode, the control electrode pad, and the second main electrode on the other surface side of the semiconductor active region. The control electrode and the control electrode wiring board are respectively insulated and arranged on the non-arranged parts of the electrodes, and an auxiliary layer thicker than the second main electrode and the control electrode wiring board is provided above the externally exposed surface of the second main electrode. The main electrode plates are arranged so as to be jointed, and second means is provided on the externally exposed surface of the auxiliary main electrode plate by press-contacting the post electrode plates to electrically connect them.

[0023]

In the first means, a recess is formed in the surface of the semiconductor active region where the second main electrode (e.g., emitter electrode) is not disposed, and a control electrode wiring board (e.g., gate) is formed on the bottom of the recess. The electrode wiring board) is arranged, and the control electrode (for example, the gate electrode) is arranged so as to extend to the bottom surface of the recess. In addition, the second main electrode (eg, emitter electrode) is arranged outside the recess, and part of the second main electrode (eg, emitter electrode) is arranged to extend to the bottom surface of the recess. Then, when the oxide film provided on the second main electrode (for example, the emitter electrode) is removed by etching, the second main electrode (for example, the emitter electrode) is the oxide film of the portion arranged outside the recess. Only the oxide film is removed to leave the oxide film extending to the bottom surface of the recess.

As described above, according to the first means, the insulating layer of the control electrode (for example, the gate electrode) and the control electrode wiring board (for example, the gate electrode wiring board) is removed by etching, and the control electrode (for example, the gate electrode) is removed. The gate electrode) and the control electrode wiring board (for example, the gate electrode wiring board) are not exposed. Further, when the exposed portion of the second main electrode (eg, emitter electrode) is pressed by the post electrode, the control electrode (eg, gate electrode) or the control electrode wiring board (eg, gate electrode wiring board) touches the post electrode. The second main electrode (for example, the emitter electrode) and the control electrode (for example, the gate electrode) and the control electrode wiring board (for example, the gate electrode wiring board) are not short-circuited.

In the second means, the control electrode wiring board (eg, gate electrode wiring board) is arranged on the surface portion of the semiconductor active region where the second main electrode (eg, emitter electrode) is not arranged, and A control electrode (for example, a gate electrode) is arranged so as to extend to a lower portion of the surface portion. Further, the auxiliary main electrode, which is thicker than the second main electrode (eg, emitter electrode) and the control electrode wiring board (eg, gate electrode wiring board), is located above the externally exposed surface of the second main electrode (eg, emitter electrode). The plates are arranged so as to be joined to each other so that the post electrode plates are pressed against the externally exposed surface of the auxiliary main electrode plate.

As described above, according to the second means, when the second main electrode (for example, the emitter electrode) is pressed onto the auxiliary main electrode plate by the post electrode, the thickness of the auxiliary main electrode plate causes The control electrode (eg, gate electrode) or the control electrode wiring board (eg, gate electrode wiring board) contacts the post electrode, and the second main electrode (eg, emitter electrode), the control electrode (eg, gate electrode) or the control electrode A wiring board (for example, a gate electrode wiring board) will not be short-circuited. Further, when the post electrode is pressed, the post electrode does not come into contact with the insulating film covering the surface of the control electrode wiring board (for example, the gate electrode wiring board), and the insulating film is not damaged by insulation.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view showing the structure of a first embodiment of a pressure contact type high breakdown voltage semiconductor device according to the present invention, showing an example in which an IGBT is configured as the pressure contact type high breakdown voltage semiconductor device. It is a thing. In this case, FIG. 1 shows a cross section of a part of the semiconductor active region including the termination region, and shows a cross sectional structure corresponding to the line AA ′ portion shown in FIG. is there.

In FIG. 1, 1 is an n drift layer and 2 is a p layer.
High-concentration layer, 3 p-well layer, 30 p-channel layer, 4 n-emitter layer, 5 gate oxide film, 6 gate electrode (control electrode), 7 interlayer insulating film (oxide film), 8 collector Electrode (first main electrode), 9 is emitter electrode (second main electrode),
Reference numeral 10 is a gate wiring board (control electrode wiring board), 11 is a second oxide film, 12 is a polyimide resin film, 13 is an oxide film, 14 is a p guard ring region, 15 is an n channel stopper region, and 16 is a field made of aluminum. The electrode 17 is a recess.

The semiconductor active region in this IGBT is
The n drift layer 1, the p high-concentration layer 2 provided on the entire one surface of the thick n drift layer 1, the p channel layer 30 selectively provided on the other surface of the n drift layer 1, two emitter layers 4 selectively provided in the p-well layer 3, and p
A gate oxide film 5 provided so as to cover the surfaces of the channel layer 30 and the emitter layer 4, a gate electrode 6 selectively arranged on the gate oxide film 4, and an interlayer provided so as to cover the gate electrode 6. An insulating film 7, a collector electrode 8 in low ohmic contact with the entire surface of the p high-concentration layer 2, and an emitter electrode 9 provided on the interlayer insulating film 7 and partly in low ohmic contact with the p channel layer 30 and the emitter layer 4. A gate electrode wiring board 10 which is provided on the interlayer insulating film 7 and partially contacts the gate electrode 6 in low ohmic contact; a second oxide film 12 which covers an exposed portion of the gate electrode wiring board 10; and a second oxide film. And a polyimide resin film 12 that covers the upper surface. Here, a concave portion 17 is formed on the other surface side of the n drift layer 1 at the boundary portion of one semiconductor active region in which the emitter electrode 9 is not arranged on the surface. The recess 17 is formed by the p well layer 3 and the oxide film 1.
7 or gate oxide film 5, gate electrode 6, interlayer insulating film 7
Are each recessed toward the n drift layer 1 side, the gate electrode wiring board 10 is arranged on the bottom surface of the recessed portion, and a part of the gate electrode wiring board 10 passes through the opening of the interlayer insulating film 7 and the lower gate electrode 6 is formed. Conductively connected to. Most of the emitter electrode 9 is arranged exclusively outside the recess 17, and only the end of the emitter electrode 9 extends from the outside of the recess 17 to the bottom surface. Most of the emitter electrode 9 is composed of the second oxide film 1.
1 is exposed by etching away, but the second oxide film 11 remains only at the end of the emitter electrode 9 and is insulated from the outside.

The termination region in this IGBT is selectively provided on the n drift layer 1, the p high-concentration layer 2 provided on the entire one surface of the n drift layer 1, and the other surface of the n drift layer 1. Three p guard ring regions 14
A single n channel stopper region 15 selectively provided on the other surface of the n drift layer 1, an oxide film 13 covering the surfaces of the n drift layer 1 and the p guard ring region 14, and a surface of the oxide film 13. An interlayer insulating film 7, a field electrode 16 provided on the interlayer insulating film 7, a part of which is in low ohmic contact with the p guard ring region 14 or the n channel stopper region 15, and a second oxide film 11 covering the field electrode 16.
And a polyimide resin film 12 covering the second oxide film 11.

2A to 2D are explanatory views showing a part of the manufacturing process for manufacturing the periphery of the recess 17 in the IGBT shown in FIG.

In FIGS. 2A to 2D, the same components as those shown in FIG. 1 are designated by the same reference numerals.

The manufacturing process for manufacturing the periphery of the recess 17 will be described with reference to FIG.

First, as shown in FIG. 2A, an emitter electrode 9 and a gate electrode wiring board 10 made of aluminum are selectively formed on the interlayer insulating film 7. In this case, the emitter electrode 9 is configured such that most of the emitter electrode 9 is located outside the recess 17 and the ends thereof extend into the recess 17, and the gate electrode wiring board 10 is located at the bottom of the recess 17. It is formed.

Then, as shown in FIG. 2B, a second oxide film 11 is uniformly formed on the upper side of the emitter electrode 9, the gate electrode wiring board 10, and the like.

Next, as shown in FIG. 2C, the recess 17 is formed.
The second oxide film 11 on the emitter electrode 9 on the outer side of the is removed by etching. In this case, the second oxide film 11 on the emitter electrode 9 in the recess 17 is left.

Finally, as shown in FIG. 2D, a polyimide resin film 12 is formed on the remaining second oxide film 11 in the recess 17, and a series of manufacturing processes of this type is completed. .

Generally, in a pressure contact type high breakdown voltage semiconductor device having a termination region as shown in FIG. 1, when a substance having an electric charge adheres to the guard ring region 14, an inversion layer is formed on the adhered portion, and a required inversion layer is formed. The breakdown voltage may not be obtained. To prevent this, a thick second oxide film 11 may be formed to cover the entire upper side of the termination region. However, in the known pressure contact type high breakdown voltage semiconductor device, when the second oxide film 11 on the emitter electrode 9 is removed by etching, the gate electrode wiring board 10 and the recess 17 are formed.
There is a possibility that the interlayer insulating film 7 inside may be removed by etching. In this case, increase the thickness of the interlayer insulating film 7,
Although it is technically possible to etch away only the second oxide film 11 by adjusting the etching time, such control is very difficult. Further, as the pressure contact type high breakdown voltage semiconductor device has a higher breakdown voltage, the inversion layer is more likely to be formed because the resistivity of the n drift layer 1 increases.
It is necessary to further increase the thickness of the second oxide film 11. As described above, the thickness of the second oxide film 11 tends to increase as compared with the thickness of the interlayer insulating film 7, and the interlayer insulating film 7 and the second oxide film 11 having the same composition are etched by
It is difficult to effectively remove only the second oxide film 11 by etching.

Therefore, in the first embodiment shown in FIG. 1, the recess 17 is formed by etching, and the recess 1 is formed.
An oxide film 13 having a sufficient thickness as compared with the gate oxide film 6 is formed on the bottom surface of 7. This thick oxide film 1
3 is for preventing the gate electrode 6 and the n drift layer 1 from being short-circuited when the gate electrode 6 is formed. Next, an interlayer insulating film 7 is formed on the gate electrode 6, an opening for contact is provided in the interlayer insulating film 7, and a gate electrode wiring board 10 is formed thereon. After the gate electrode wiring board 10 is formed, the manufacturing process shown in FIGS. 2A to 2D is performed. By passing through such a manufacturing process, the number of processes does not increase as compared with the known manufacturing process.

That is, in the structure of the first embodiment, the recess 17 is formed in the unarranged portion of the emitter electrode 9, and the recess 1 is formed.
The gate electrode wiring board 10 is arranged on the bottom surface of the recess 7, and the emitter electrode 9 is arranged so as to extend from the outside of the recess 17 to the bottom of the recess 17. Then, when the second oxide film 11 on the emitter electrode 9 is removed by etching, the second oxide film 11 on the emitter electrode 9 arranged outside the recess 17 is removed.
Since the second oxide film 11 on the emitter electrode 9 extending to the bottom surface of the recess 17 is left, only the interlayer insulating film 7 and the gate insulating the gate electrode 6 are removed. The second oxide film 11 that insulates the electrode wiring board 10 is not removed by etching, and the gate electrode 6 and the gate electrode wiring board 10 are not exposed.

As described above, according to the first embodiment, when the exposed portion of the emitter electrode 9 is pressed by the post electrode as shown in FIG. 8, the gate electrode 6 and the gate electrode wiring board 10 are post-formed. The emitter electrode 9 and the gate electrode 6 and the gate electrode wiring board 10 are not short-circuited by touching the electrodes.

FIG. 3 is a sectional view showing the structure of the second embodiment of the pressure contact type high withstand voltage semiconductor device according to the present invention, in which an IGBT is also constructed as the pressure contact type high withstand voltage semiconductor device. Is shown. In this case,
7 shows a cross section of a part of the semiconductor active region.
FIG. 7A shows a cross-sectional structure corresponding to the line CC ′ in the drawing.

In FIG. 3, reference numeral 18 denotes an auxiliary emitter electrode plate (auxiliary main electrode plate) which is thicker than the emitter electrode 9 and the gate electrode wiring board 10, and the other components are the same as those shown in FIG. The same symbols are attached to the elements.

The difference between the structure of the first embodiment (hereinafter referred to as the former) and the structure of the second embodiment (hereinafter referred to as the latter) is that the former is large. The auxiliary emitter electrode plate 18 has a portion located outside the recess 17 and an end portion thereof extending to the bottom portion of the recess 17, whereas the latter is entirely located outside the recess 17. The former does not have such an auxiliary emitter electrode plate 18, whereas the latter has a position in which the auxiliary emitter electrode plate 18 is bonded to the upper side of the emitter electrode 9 and the second oxide film. Regarding the configuration of 11, the former is arranged so as to cover up to the end of the emitter electrode 9 extending to the bottom surface of the recess 17, whereas
The latter is only three points that extend from the concave portion 17 to the outside portion of the concave portion 17 and extend to the joint portion between the emitter electrode 9 and the auxiliary emitter electrode plate 18, and in addition, the first embodiment. There is no difference in structure between the third embodiment and the second embodiment. Although not shown in FIG. 3, also in the second embodiment, a termination region is formed around the semiconductor active area device as in the first embodiment.

FIGS. 4A to 4E are explanatory views showing a part of the manufacturing process for manufacturing the periphery of the recess 17 in the IGBT shown in FIG.

In FIGS. 4A to 4E, the same components as those shown in FIG. 3 are designated by the same reference numerals.

The manufacturing process for manufacturing the periphery of the recess 17 will be described with reference to FIG.

First, as shown in FIG. 4A, an emitter electrode 9 made of aluminum, a gate electrode wiring board 10 and a field electrode 16 (not shown) are selectively formed on the interlayer insulating film 7. At this time, the emitter electrode 9 is formed so as to be entirely on the outside of the recess 17, and the gate electrode wiring board 10 is formed so as to be on the bottom of the recess 17.

Subsequently, as shown in FIG. 4B, a second oxide film 11 is uniformly formed on the upper side of the emitter electrode 9, the gate electrode wiring board 10 and the like.

Next, as shown in FIG. 4C, the second oxide film 11 on the emitter electrode 9 is removed by etching except for a part near the recess 17. As a result, the second oxide film 11 on the end of the emitter electrode 9 near the recess 17 is formed.
Remains.

Then, as shown in FIG. 4D, the second end portion of the emitter electrode 9 which remains on the emitter electrode 9
Auxiliary emitter electrode plate 1 made of aluminum on the oxide film 11
8 is formed.

Finally, the polyimide resin film 12 is formed on the second oxide film 11 in the recess 17, and a series of manufacturing processes of this type is completed.

In the IGBT according to the second embodiment, the auxiliary emitter electrode plate 18 is bonded to the emitter electrode 9 and arranged.
It is characterized in that an emitter electrode having a substantially two-layer structure is formed. The end of the second oxide film 11 is formed on the emitter electrode 9, and the end of the second oxide film 11 is formed. Since the thick auxiliary emitter electrode plate 18 is formed on the second oxide film 1 on the emitter electrode 9 even when the auxiliary emitter electrode plate 18 is pressed by the post electrode.
1 is not destroyed, and, of course, the post electrode does not come into contact with the gate electrode 6 or the gate electrode wiring board 10 to cause a short circuit between the emitter electrode 9 and the gate electrode 6 or the gate electrode wiring board 10. Further, in the second embodiment, since the thickness of the gate electrode wiring board 10 is considerably smaller than the thickness of the emitter electrode 9 and the auxiliary emitter electrode plate 18 superposed on each other, the depth of the recess 17 formed by etching is small. Can be made shallower than the depth of the recess 17 of the first embodiment.

Therefore, the second embodiment is easy to manufacture, and the steps of the p well layer 3, the oxide film 13, the gate electrode 6, and the interlayer insulating film 7 in the recess 17 are reduced, and the processing accuracy is improved. It is possible to improve the size and reduce the size of the gate electrode wiring board 10.

Next, FIG. 5 is a sectional view showing the structure of the third embodiment of the pressure contact type high breakdown voltage semiconductor device according to the present invention.
It shows an example in which is configured. Also in this case, FIG. 5 shows a partial cross section of the semiconductor active region.
FIG. 7A shows a cross-sectional structure corresponding to the line CC ′ in the drawing.

In FIG. 5, the same components as those shown in FIG. 3 are designated by the same reference numerals.

The difference between the structure of the second embodiment and the structure of the third embodiment (hereinafter, referred to as the latter) is that the former is the same as the second embodiment, but the second embodiment is the same as the latter. Whereas the third embodiment is formed, the concave portion 1 is formed.
7 is not formed, that is, the p-well layer 3 and the oxide film 1
3, the gate electrode 6 and the interlayer insulating film 7 are each flat, and there is no difference in structure between the second embodiment and the third embodiment. In addition,
Although not shown in FIG. 5, also in the third embodiment, as in the first embodiment, the termination region is formed around the semiconductor active area device.

The IGBT according to the third embodiment has a second
Similar to the above embodiment, the auxiliary emitter electrode plate 18 is bonded to the emitter electrode 9 to form an emitter electrode having a two-layer structure, and the end of the second oxide film 11 is characterized. Part is formed on the emitter electrode 9, and
A thick auxiliary emitter electrode plate 1 is formed on the edge of the second oxide film 11.
8 is formed, the second oxide film 11 on the emitter electrode 9 is not destroyed by this pressure contact when the auxiliary emitter electrode plate 18 is pressure contacted by the post electrode. Also,
Also in the third embodiment, since the thickness of the gate electrode wiring board 10 is considerably smaller than the thickness of the emitter electrode 9 and the auxiliary emitter electrode board 18 superposed on each other, the emitter electrode and the gate electrode wiring board having the two-layer structure are formed. A step can be formed between the gate electrode 6 and the auxiliary emitter electrode plate 18 when the auxiliary emitter electrode plate 18 is pressed by the post electrode.
The post electrode does not come into contact with the gate electrode wiring board 10 and the emitter electrode 9 does not short-circuit with the gate electrode 6 or the gate electrode wiring board 10. Furthermore, in the third embodiment, the recess 1
Since it is not necessary to form the gate electrode wiring board 10 on the bottom surface portion of 7, there is an advantage that the manufacturing is easier than in the second embodiment.

In each of the above-described embodiments, an example in which an IGBT is configured as a pressure contact type high breakdown voltage semiconductor device has been described, but the pressure contact type high breakdown voltage semiconductor device according to the present invention is used in the case of configuring an IGBT. The present invention is not limited to the above, and can be similarly applied to the case of forming another device such as an insulated gate thyristor.

FIG. 6 is a circuit diagram showing an example of a case where a pressure contact type high breakdown voltage semiconductor device according to the present invention, for example, an IGBT is used to form an inverter device.

In FIG. 6, 19 is an IGB according to the present invention.
T, 20 are diodes, 21 and 22 are DC power supply terminals, 2
3, 24 and 25 are AC output terminals.

Then, the two IGBTs 1 connected in series are connected.
Three sets of 9 are connected between the DC power supply terminals 21 and 22, respectively, and a diode 2 is connected to each of the IGBTs 19.
0 is connected in parallel. Also, two IGBTs 19 of each group
Are connected to the AC output terminals 23, 24, and 25, respectively, to form an inverter device.

Since the operation of the inverter device having such a configuration is already well known, the description of the operation will be omitted, but since the insulated gate pressure contact type high withstand voltage semiconductor device according to the present invention is used as the IGBT 20, the operation is omitted. , Compared to the case where the inverter device is configured using the known current-driven high-voltage semiconductor device, the configuration of the gate drive circuit is simpler, and higher frequency switching operation is possible compared to the known inverter device of this type. In addition, an inverter device capable of processing a large amount of power can be obtained.

[0065]

As described above, according to the first aspect of the invention, the recess 17 is formed in the surface of the semiconductor active region where the second main electrode (for example, the emitter electrode) 9 is not arranged,
The control electrode wiring board (for example, gate electrode wiring board) 10 is arranged on the bottom surface of the recess 17, and the control electrode (for example, gate electrode) 6 is arranged to extend to the bottom surface of the recess 17, and the second main Electrode (eg, emitter electrode) 9
Is disposed outside the recess 17, and the second
The end of the main electrode (for example, the emitter electrode) 9 is arranged so as to extend to the bottom of the recess 17. Then, the second oxide film 11 provided on the second main electrode (eg, emitter electrode) 9
When etching away, the second main electrode (eg, emitter electrode) 9 is arranged so as to extend to the bottom surface of the recess 17 by removing only the second oxide film 11 on the portion outside the recess 17. The second oxide film 11 remains.

As described above, according to the first aspect of the present invention, the insulating layers 7 and 13 for externally insulating the control electrode (for example, the gate electrode) 6 and the control electrode wiring board (for example, the gate electrode wiring board) 10 are provided. Is removed by etching, so that the control electrode (for example, gate electrode) 6 and the control electrode wiring board (for example, gate electrode wiring board) 10 are not exposed, and the second main electrode (for example, emitter electrode) 9 The control electrode (eg, gate electrode) 6 and the control electrode wiring board (eg, gate electrode wiring board) 10 are in contact with the post electrode when the exposed portion of the electrode is pressed against the second electrode (eg, emitter electrode). ) 9 and control electrode (eg, gate electrode) 6
Also, there is an effect that a short circuit does not occur with the control electrode wiring board (for example, the gate electrode wiring board 10), and in addition, the number of manufacturing steps is not increased as compared with the known type. There is also an effect.

According to the second to fourth aspects of the present invention, a control electrode wiring board (eg, gate electrode wiring) is formed on the surface portion of the semiconductor active region where the second main electrode (eg, emitter electrode) 9 is not arranged. The plate 10 is arranged, and the control electrode (for example, the gate electrode) 6 is arranged so as to extend to the lower side portion of the surface part thereof, and the second main electrode (for example, the emitter electrode) 9 is arranged above the second main electrode 9. An auxiliary main electrode plate 18 having a thickness larger than that of the electrode (for example, emitter electrode) 9 or the control electrode wiring board (for example, gate electrode wiring board) 10 is jointly arranged.
The external exposed surface of the auxiliary main electrode plate 18 is pressed against the post electrode plate.

As described above, according to the second to fourth aspects of the present invention, when the second main electrode (for example, the emitter electrode) 9 is pressed onto the auxiliary main electrode plate 18 by the post electrode, the auxiliary main electrode is pressed. Depending on the thickness of the plate 18, the control electrode (eg, gate electrode) 6 or the control electrode wiring board (eg, gate electrode wiring board) 10 touches the post electrode, and the second main electrode (eg, emitter electrode) 9 and the control electrode (Eg, gate electrode) 6
And the control electrode wiring board (for example, the gate electrode wiring board) 10 can be prevented from causing a short circuit, and the post electrode can be controlled by the control electrode wiring board (for example, the gate electrode wiring board) when the post electrodes are pressed. There is also an effect that the second oxide film 11 covering the surface of 10 is prevented from contacting the second oxide film 11 to cause insulation damage to the insulating film, and moreover, as compared with this known type, There is also an effect that the number of manufacturing processes does not increase.

[Brief description of drawings]

FIG. 1 is a cross-sectional configuration diagram showing a configuration of a first embodiment of a pressure contact type high breakdown voltage semiconductor device according to the present invention.

FIG. 2 is a pressure-contact type high breakdown voltage semiconductor device (IGB shown in FIG.
It is explanatory drawing which shows a part of manufacturing process at the time of manufacturing the periphery of the recessed part in T).

FIG. 3 is a cross-sectional configuration diagram showing a configuration of a second embodiment of a pressure contact type high breakdown voltage semiconductor device according to the present invention.

4 is a pressure contact type high breakdown voltage semiconductor device (IGB shown in FIG. 3).
It is explanatory drawing which shows a part of manufacturing process at the time of manufacturing the periphery of the recessed part in T).

FIG. 5 is a cross-sectional configuration diagram showing the configuration of a third embodiment of the pressure contact type high breakdown voltage semiconductor device according to the present invention.

FIG. 6 is a pressure contact type high breakdown voltage semiconductor device (IGB according to the present invention;
It is a circuit diagram which shows an example at the time of comprising an inverter apparatus using T).

FIG. 7 is a plan view showing an example of the configuration of a known pressure contact type high breakdown voltage semiconductor device.

FIG. 8 is a cross-sectional configuration diagram showing an example of a known pressure contact type package that houses a pressure contact type high breakdown voltage semiconductor device (IGBT).

9 is a cross-sectional view showing a cross-sectional structure of the pressure contact type high breakdown voltage semiconductor device (IGBT) taken along the line CC ′ shown in FIG. 7.

10 is a cross-sectional view showing a cross-sectional structure of the pressure contact type high breakdown voltage semiconductor device (IGBT) taken along the line DD ′ shown in FIG. 7.

11 is a sectional view showing a sectional structure of a pressure contact type high breakdown voltage semiconductor device (IGBT) taken along a line EE ′ shown in FIG. 7.

[Explanation of symbols]

 1 n drift layer 2 p high concentration layer 3 p well layer 4 n emitter layer 5 gate oxide film 6 gate electrode (control electrode) 7 interlayer insulating film (oxide film) 8 collector electrode (first main electrode) 9 emitter electrode (first electrode) 2 main electrode) 10 gate wiring board (control electrode wiring board) 11 second oxide film 12 polyimide resin film 13 oxide film 14 p guard ring region 15 n channel stopper region 16 field electrode 17 recess 18 auxiliary emitter electrode plate (auxiliary main electrode) Plate) 30 p channel layer

Claims (4)

[Claims] 1. A semiconductor active region having one or more pn junctions, a first main electrode having an externally exposed surface provided on one surface side of the semiconductor active region, and the other of the semiconductor active regions. A second main electrode having an externally exposed surface provided on the surface side, a control electrode provided on the other surface side and externally insulated by an insulating layer, and a control electrode wiring board conductively connected to the control electrode. And one or more guard rings arranged on the other surface side of the semiconductor active region so as to surround the semiconductor active region, respectively on the externally exposed surfaces of the first and second main electrodes. The post electrode is pressed and the terminal electrode plate is pressed to the control electrode pad conductively connected to the control electrode wiring board, and the post electrode and the control electrode pad corresponding to the first and second main electrodes are connected to the front electrode. In the pressure contact type high breakdown voltage semiconductor device for conducting conductive connection with the terminal electrode plate, a concave portion is formed in an unarranged portion of the second main electrode on the other surface side of the semiconductor active region, and the control electrode and the The control electrode wiring board is disposed on the bottom surface of the recess so as to be insulated, the second main electrode is disposed outside the recess, and a part of the second main electrode is extended to the bottom surface of the recess. Pressure contact type high voltage semiconductor device. 2. A semiconductor active region having one or more pn junctions, a first main electrode having an externally exposed surface provided on one surface side of the semiconductor active region, and the other of the semiconductor active regions. A second main electrode having an externally exposed surface provided on the surface side, a control electrode provided on the other surface side and externally insulated by an insulating layer, and a control electrode wiring board conductively connected to the control electrode. And one or more guard rings arranged on the other surface side of the semiconductor active region so as to surround the semiconductor active region, respectively on the externally exposed surfaces of the first and second main electrodes. The post electrode is pressed and the terminal electrode plate is pressed to the control electrode pad conductively connected to the control electrode wiring board, and the post electrode and the control electrode pad corresponding to the first and second main electrodes are connected to the front electrode. In a pressure contact type high withstand voltage semiconductor device for conducting conductive connection with a terminal electrode plate, the control electrode and the control electrode wiring board are provided in an unarranged portion of the second main electrode on the other surface side of the semiconductor active region. Each of them is arranged in an insulating manner, and an auxiliary main electrode plate thicker than the thickness of the second main electrode and the control electrode wiring board is jointly arranged above the externally exposed surface of the second main electrode. A pressure contact type high breakdown voltage semiconductor device characterized in that the surface thereof is pressure-contacted with the post electrode plate to electrically connect them. 3. The control electrode and the control electrode wiring board are respectively insulated and arranged on a bottom surface portion of a recess provided on the other surface side of the semiconductor active region. Pressure contact type high voltage semiconductor device. 4. The control electrode wiring board is externally insulated by an insulating layer that reaches a part of a joint portion between the second main electrode and the auxiliary main electrode board. 3. The pressure contact type high breakdown voltage semiconductor device according to any one of 3 above.