JPH08162649A - Semiconductor device having tunnel junction layer - Google Patents

Abstract

PURPOSE: To provide a semiconductor device having a tunnel junction with a large peak current value. CONSTITUTION: A semiconductor device has a tunnel junction layer 3 composed of a first compound semiconductor layer 31 of a first conductivity type, a second compound semiconductor layer 32 of a second conductivity type formed on the upper part of the first compound semiconductor layer 31, and a third compound semiconductor layer 33 of the second conductivity type formed on the upper part of the second compound semiconductor layer 32 and having a larger band gap Eg than that of the second compound semiconductor layer 32. The impurity concentration of the third compound semiconductor layer 33 is set to 0.8×10<19> to 1×10<19> cm<-3> .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a compound semiconductor tunnel junction layer, and particularly to a novel semiconductor device having a tunnel junction structure as a part of a compound semiconductor device having a complicated laminated structure. Regarding structure and its optimization.

[0002]

2. Description of the Related Art Solar cells are expected to play an important role in view of the energy problems facing humanity and the emission of carbon dioxide (CO ₂ ). It is receiving attention because of its conversion efficiency. Further, the InGaP / GaAs solar cell has radiation resistance and is expected to be applied to space applications. In order to further increase the conversion efficiency of solar cells, a so-called tandem cell type solar cell structure in which two to three solar cells are connected in series is adopted. In order to electrically connect the upper cell (top cell) and the lower cell (bottom cell) of such a tandem cell type solar cell, a GaAs tunnel junction layer 3 as shown in FIG. 5 is used.

In FIG. 5, a GaAs cell 2 is used as a lower cell (bottom cell) and an upper cell (top cell) is used.
For this, an In _0.5 Ga _0.5 P cell 4 is used. Further, a GaAs tunnel junction layer 3 is provided between the lower cell and the upper cell in order to electrically connect them in series. The GaAs bottom cell 2 is formed on the Zn-doped p ⁺ GaAs substrate 11 (p <1 × 10 ¹⁹ cm ⁻³ ). And the GaAs bottom cell 2 is p
⁺ Thickness of 3.5 μm formed on the GaAs substrate 11,
A pGaAs base layer 22 having an impurity density of 1 to 4 × 10 ¹⁷ cm ⁻³ , and an n ⁺ GaAs emitter layer 2 provided on the pGaAs base layer 22 having a thickness of 0.1 μm and an impurity density of 1.0 × 10 ¹⁸ cm ^−3.
3, the thickness of the upper part is 0.2 μm, and the impurity density is 1 ×
It is composed of 10 ¹⁸ cm ⁻³ n ⁺ AlGaAs window layer 29. A pn junction is formed between the emitter layer 23 and the base layer 22. The GaAs tunnel junction layer 3 is n ⁺ Al which is the uppermost layer of the lower cell (GaAs bottom cell) 2.
An n ⁺⁺ GaAs layer 31 having a thickness of 20 nm and an impurity density of 1 × 10 ¹⁹ cm ⁻³ formed on the GaAs window layer 29 and a p ⁺⁺ GaAs having a thickness of 20 nm and an impurity density of 1.0 × 10 ¹⁹
And the layer 32. On top of this, pIn having a thickness of 0.8 μm and an impurity density of 1 to 4 × 10 ¹⁷ cm ⁻³ is formed.
_0.5 Ga _0.5 P base layer 42; n ⁺ In _0.5 Ga _0.5 P emitter layer 43 having a thickness of 0.1 μm and an impurity density of 1 × 10 ¹⁸ cm ⁻³ ; and a thickness of 40 nm, an impurity density of 1 × 10 ¹⁸
The In _0.5 Ga _0.5 P top cell 4 having the cm ⁻³ n ⁺ AlInP window layer 44 deposited in this order is formed.

GaAs forming the tunnel junction layer 3
The p ⁺⁺ / n ⁺⁺ junction is set to a thin thickness (20 nm) that almost completely expands the depletion layer in order to minimize light absorption here and increase light transmission to the lower cell 2. Has been done. PI above the GaAs tunnel junction layer 3
The doping of the nGaP base layer 42 is 1-2 × 10 ¹⁷ c
At about m ⁻³ , the impurity density is lower than that of the p ⁺⁺ GaAs layer 32. Another conventional technique is pInGa in FIG.
A thickness of 0.1 between the P base layer 42 and the p ⁺⁺ GaAs layer 32.
P ⁺ InGaP back surface electric field layer (hereinafter referred to as B
(Referred to as SF layer) to form a potential barrier against minority carriers to prevent back surface recombination loss. In this case as well, the impurity density of the BSF layer is 4 × 10.
It is about ¹⁷ cm ^−3, which is lower than that of the p ⁺⁺ GaAs layer 32.

[0005]

[Problems to be Solved by the Invention] p ⁺⁺ Ga in FIG.
Zinc is usually used as the dopant of the As layer 32, the pInGaP layer 42, or the p ⁺ InGaP-BSF layer (not shown). The structure shown in FIG.
Vapor phase epitaxial growth is carried out at a substrate temperature of around 700 ° C. using such a method. At such a substrate temperature (growth temperature), zinc diffuses during the growth of each layer of the upper cell on the tunnel junction layer 3. However, the impurity density of the p ⁺⁺ GaAs layer 32 is reduced, and as a result, the peak current I _{p of the} tunnel diode is reduced, and the peak current density J _p = 40 mA / cm ² can only be obtained in the structure of FIG. There was a drawback.

The tandem cell type solar cell has been described above as an example, but the problem of diffusion of impurities such as Zn in the compound semiconductor forming the tunnel junction layer is not limited to the solar cell.
Similar problems occur in other semiconductor devices such as transistors and integrated circuits using tunnel injection.

The present invention has been made in view of the above points, and has a semiconductor device having a tunnel junction layer capable of maintaining a high impurity density in each layer constituting the tunnel junction layer and increasing the peak current I _p of the tunnel diode. It is to provide a novel structure of.

Another object of the present invention is to provide a semiconductor device having a tunnel junction layer in which the impurity density profile of the tunnel junction layer can be maintained at a designed value even when heat-treated at a high temperature of about 700 ° C. .

[0009]

In order to solve the above problems, the present invention provides a first compound semiconductor layer 31 of a first conductivity type and an upper portion of the first compound semiconductor layer 31 as shown in FIG. Second conductivity type second compound semiconductor layer 32 formed in
And a third compound semiconductor layer 33 formed on the second compound semiconductor layer 32 and having a second conductivity type and a larger forbidden band width (Eg) than the second compound semiconductor layer 32. The second compound semiconductor layer 32 has a tunnel junction layer 3 in a part thereof, and the second compound semiconductor layer 32 is a depletion layer formed by the pn junction formed between the second compound semiconductor layer 32 and the first compound semiconductor layer 31 and is almost completely depleted. The impurity density of the compound semiconductor layer 33 of No. 3 is 0.8 times or more the impurity density of the second compound semiconductor layer 32. The first conductivity type is, for example, an n-type as shown in FIG. 1, and the second conductivity type is a p-type which is a conductivity type opposite to the first conductivity type. In FIG. 1, p type and n type may be converted. This hetero tunnel junction layer is a semiconductor device included in, for example, a tandem solar cell as shown in FIG. 3 or a part of the tunnel injection HBT shown in FIG.

Preferably, the second compound semiconductor layer 32 is GaAs and the third compound semiconductor layer 33 is In _1-x Ga.
_x P. The third compound semiconductor layer 33 may be a compound semiconductor having a forbidden band width Eg larger than that of GaAs lattice-matched with GaAs, and Al other than In _{1- x} Ga _x P.
_1-x Ga _x As may be used.

Preferably, the dopant of the second and third compound semiconductor layers is zinc (Zn), and the impurity density of the third compound semiconductor layer 33 is 0.8 to 1.0 × 10.
That is ¹⁹ cm ^-3 .

Preferably, as shown in FIGS. 1, 3 and 4, the first compound semiconductor layer has a first conductivity type and has a forbidden band width (Eg) lower than that of the first compound semiconductor layer. The fourth compound semiconductor layers 29, 24, 99 of large In _1-x Ga _x P or Al _1-x Ga _x As are formed.

[0013]

According to the features of the present invention, the first and the second are conventionally used.
Since the third compound semiconductor layer having a large forbidden band width Eg and a high impurity density is formed on the tunnel junction layer 3 which is composed of only the compound semiconductor layers 31 and 32 of FIG. Even if the impurity (dopant) of the compound semiconductor layer 32 is a substance having a large diffusion rate such as zinc (Zn), Zn diffuses into other regions (layers) during the vapor phase growth, and the tunnel junction layer 3 The impurity density of is not reduced. That is, normally, in GaAs-based MOCVD, continuous epitaxial growth is performed at a substrate temperature of about 700 ° C. to form a multilayer structure. At such a temperature, impurities with a high diffusion rate, such as Zn, are deposited on another epitaxial growth film formed thereon. However, the presence of the third compound semiconductor layer 33, which is a feature of the present invention, can prevent this diffusion.

As a result, the steep and high impurity density impurity profile required for the tunnel junction can be realized, and the peak current I _p of the tunnel diode is also improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. The same reference numerals are used for the portions that overlap with FIG. FIG. 1 shows a sectional structure of a tunnel diode according to a first embodiment of the present invention.

In FIG. 1, Si-doped impurity density 2
On an n ⁺ GaAs substrate 18 of × 10 ¹⁸ cm ^-3 , a thickness of 0.3 μm and an impurity density of 2 × 10 ¹⁸ cm ^-3 of n ⁺ GaA.
s layer 19, thickness 0.1 μm, impurity density 3 × 10
An InGaP pseudo window layer 29 of ¹⁸ cm ⁻³ is formed, and a thickness of 10 nm and an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ of n ⁺⁺ Ga are formed thereon.
As layer 31, thickness 10 nm, impurity density 1 × 10 ¹⁹ cm
^-3 p ⁺⁺ GaAs layer 32, the thickness 0.1 [mu] m, the tunnel junction layer 3 made of p ⁺⁺ In _0.5 Ga _{0. 5} P layer 33 of impurity concentration 0.8 to 1 × 10 ¹⁹ cm ^-3 is formed , 0.1 to 0.3 μm in thickness, and an impurity density of 4 × 10 ¹⁷ c
m ⁻³ p ⁺ In _0.5 Ga _0.5 P pseudo-BSF layer 48, thickness 0.7 μm, pIn of impurity density 1.5 × 10 ¹⁷ cm ⁻³
_0.5 Ga _0.5 P pseudo base layer 49, and thickness 0.3 μ
A p ⁺ GaAs contact layer 59 having m and an impurity density of 1 × 10 ¹⁹ cm ⁻³ is formed. An Au plating layer 72 having a thickness of about 1 μm is formed as an upper metal electrode layer on the surface of the p ⁺ GaAs contact layer 59, and the n ⁺ GaAs substrate 18 is formed.
An Au plating layer having a thickness of about 1 μm is formed as a lower metal electrode layer 8 on the back surface of the. If an n ⁻ GaAs traveling layer having a traveling angle (3/2) π radian is formed under the tunnel junction layer 3, that is, below the n ⁺⁺ GaAs layer 31, a tunnel injection transit time effect element is also formed. it can.

FIG. 2 shows the forward IV characteristics of the tunnel diode according to the first embodiment of the present invention, which is p ⁺⁺ In _0.5 G.
When the impurity density of the a _0.5 P layer 33 is 1 × 10 ¹⁹ cm ⁻³ , the peak current density J _p = 200 mA / cm ^2, which is five times or more that of the conventional technique. For reference, in the structure of FIG. 1, the p ⁺⁺ In _0.5 Ga _0.5 P layer 33 has an impurity density of 2 ×
In the case of 10 ¹⁸ cm ^-3 , J _p = 80 mA / cm ² .

The structure shown in FIG. 1 has a structure of metalorganic vapor phase epitaxy (MO
CVD method), CBE (Chemical Beam E)
Pitaxy method, MBE (Molecular Be)
amEpitaxy method, MLE (Molecular)
Layer ⁺ Epitaxy) method or the like to obtain n ⁺ Ga
Continuous epitaxial growth may be performed on the As substrate 18. The MOCVD method is a low pressure MO even if it is a normal pressure MOCVD method.
The CVD method may be used, but the reduced pressure MOCV is used because of the controllability of the film thickness.
The D method is preferable. For example, the n ⁺ GaAs substrate 18 is set to 6 in a reaction tube kept under a reduced pressure of 6.7 to 10 kPa.
It may be heated to 50 ° C., and the raw material gas and the dopant gas may be introduced while controlling the flow rate with a mass flow controller or the like. The substrate heating method may be infrared (IR) lamp heating, high frequency (RF) induction heating, or resistance heating, and the reaction tube may be vertical or horizontal. Group III source gases include triethylgallium (TEG), trimethylindium (TMI), trimethylaluminum (TM)
A), trimethylamine alane (TMAAl), etc., V
Phosphine (PH ₃ ) and arsine (AsH ₃ ) are used as a group source gas. Alternatively, tertiary butyl phosphine ((C ₄ H ₉ ) PH ₂ ; TBP), tertiary butyl arsine ((C ₄ H ₉ ) AsH ₂ ;
TBA) or the like may be used. As n-type dopant gas, monosilane (SiH ₄ ), disilane (Si ₂ H
₆ ), or diethyl selenium (DESe), diethyl tellurium (DETe) or the like may be used, but monosilane is preferable. As the p-type dopant gas, for example, diethyl zinc (DEZn) may be used. In addition, CBE
In the case of growing by the CVD method, the same source gas and dopant gas are used, the growth pressure is 1.3 × 10 ⁻³ Pa, and the substrate temperature is 5
It may be carried out at 20 ° C.

Further, p forming a tunnel diode
^{The ++} GaAs layer 32, the n ⁺⁺ GaAs layer 31, etc. can be controlled with extremely high precision by using the MLE method and growing one molecular layer in one cycle of gas introduction. For example, the substrate temperature 48
At 0 ° C., at a pressure of 6 × 10 ⁻⁴ Pa, TEG is introduced for 4 seconds, vacuum is exhausted for 3 seconds, AsH ₃ is introduced for 20 seconds, and then a gas exhaustion cycle of vacuum exhaust for 3 seconds is used. Can grow. In particular, the MLE method is suitable when it is necessary to control the mesoscopic scale of a tunnel diode or the like, and Zn diffusion is small at a low temperature of 480 ° C. In the same chamber, a thin film such as a tunnel diode has a MLE mode, another 0.3 μm,
A thick film of 0.7 μm can be grown more efficiently if grown in a switching mode such as growing in MOCVD mode. Growth pressure 7.6kPa decompression MOCV
In method D, the growth rate is typically about 2 to 3 μm / hr.

FIG. 3 shows InG according to the second embodiment of the present invention.
1 shows a structure of an aP / GaAs tandem cell type solar cell.
In FIG. 3, a GaAs cell 2 is used as the lower cell (bottom cell), and In is used as the upper cell (top cell).
_{A 0.5} Ga _0.5 P cell 4 is used. Further, a GaAs tunnel junction layer 3 is provided between the lower cell and the upper cell in order to electrically connect them in series.
More specifically, the GaAs bottom cell 2 is formed on a Zn-doped p ⁺ GaAs substrate 11 (p> 1 × 10 ¹⁹ cm ⁻³ ) with a thickness of 0.3 μm and an impurity density of 7.0 × 10.
It is formed on the ¹⁸ cm ⁻³ p ⁺ GaAs buffer layer 12. The GaAs cell 2 is formed on the p ⁺ GaAs buffer layer 12, has a thickness of 0.1 μm, and has an impurity density of 3.0 × 10 ¹⁸ cm ^{−3 and is made} of p ⁺ InGaP BSF layer 2.
1. Thickness of 3 .mu.m provided on top of the impurity density 2.
0 × 10 ¹⁷ cm ⁻³ pGaAs base layer 22, a thickness of 0.1 μm provided on the pGaAs base layer 22, and an impurity density of 2.0 × 10
¹⁸ cm ⁻³ n ⁺ GaAs emitter layer 23, and n ⁺ In with an upper portion thickness of 0.1 μm and an impurity density of 0.1 μm
_0.5 Ga _0.5 P window layer 24. A pn junction is formed between the emitter layer 23 and the base layer 22. The GaAs tunnel junction layer 3 has a thickness of 10 nm and an impurity density of 5 formed on the n ⁺ In _0.5 Ga _0.5 P window layer 24 which is the uppermost layer of the lower cell (GaAs bottom cell) 2.
X 10 ¹⁸ cm ^-3 or more of n ⁺⁺ GaAs layer 31 and a thickness of 10
nm, impurity density 1.0 × 10 ¹⁹ cm ^-3 p ⁺⁺ GaAs
Layer 32, thickness 0.1 μm, impurity density 0.8-1 × 10
It is composed of a ¹⁹ cm ⁻³ p ⁺⁺ In _0.5 Ga _0.5 P layer 33. And on this upper part, the thickness is 0.1 to 0.3 μm.
With an impurity density of 4 × 10 ¹⁷ cm ⁻³ p ⁺ In _0.5 Ga
_0.5 P BSF layer 41; thickness 0.7 to 1.5 μm, impurity density, pIn _0.5 Ga _0.5 P of 1.5 × 10 ¹⁷ cm ⁻³
Base layer 42; thickness 50 nm, impurity density 3.0 × 10
¹⁸ cm ^-3 of n ⁺ In _0.5 Ga _0.5 P emitter layer 43; and the thickness 30 nm, the impurity density of 2 × 10 ¹⁸ cm ^-3 n ⁺
In _0.5 G deposited AlInP window layer 44 in this order
The a _0.5 P top cell 4 is formed. In _0.5 Ga
An n ⁺ GaAs layer 51 having a thickness of 0.3 μm for ohmic contact is formed on a part of the upper portion of the _0.5 P top cell 4, and an Au—Ge / Ni / Au layer 71 and an Au layer 72 thereon are formed on the n ⁺ GaAs layer 51. An upper metal electrode layer (surface electrode layer) 7 made of is formed. On the back surface of the p ⁺ GaAs substrate 11, an Au layer is formed as a lower metal electrode layer (back surface electrode layer) 8. In _0.5 Ga _0.5 P n ^{+ of} top cell 4
Although not shown in the drawing, the ZnS layer 6 is usually formed in the region of the surface of the AlInP window layer 44 other than the portion where the n ⁺ GaAs layer 51 and the upper metal electrode layer 7 thereabove are formed.
1. The antireflection film 6 made of the MgF ₂ layer 62 is formed. With such a structure, the peak current density of the tunnel junction layer 3 has an extremely large value of J _p = 200 mA / cm ² , the short-circuit photocurrent Isc as a tandem cell is also large, and therefore the conversion efficiency is extremely large and the fill factor ( The fill factor (FF) also becomes large.

FIG. 4 shows a tunnel injection type heterojunction bipolar transistor (HBT) according to a third embodiment of the present invention.
FIG. N having a thickness of 0.3 μm and an impurity density of 2 × 10 ¹⁸ cm ⁻³ is sequentially formed on the semi-insulating GaAs substrate 97.
⁺ In _0.5 Ga _0.5 P collector contact layer 98, thickness 0.1 μm, impurity density 1 × 10 ^{14 to} 3 × 10 ¹⁵ cm ⁻³
Of ^p - In _0.5 Ga _0.5 ^P drift layer 99, the thickness 10n
m, n ⁺⁺ GaAs layer 3 with an impurity density of 5 × 10 ¹⁸ cm ^-3
1, p ^{++ with} a thickness of 10 nm and an impurity density of 1 × 10 ¹⁹ cm ^-3
GaAs layer 32, thickness 0.1 μm, impurity density 0.8 to
1 × 10 ¹⁹ cm ⁻³ p ⁺⁺ InGaP layer 33, thickness 0.3
A p ⁺ GaAs contact layer 59 having a thickness of μm and an impurity density of 1 × 10 ¹⁹ cm ⁻³ is formed. The drift layer 99 is n ⁻
An In _0.5 Ga _0.5 P layer or an iIn _0.5 Ga _0.5 P layer may be used, and the impurity density may be selected so that the drift layer 99 is almost completely depleted. n ⁺⁺ GaAs layer 31,
Although the tunnel junction layer 3 is formed by the p ⁺⁺ InGaP layer 33, the n ⁺⁺ GaAs layer 31 becomes the actual emitter region of this HBT, and the p just under the n ⁺⁺ GaAs layer 31 is formed.
^- the upper portion of the In _0.5 Ga _0.5 P drift layer 99 becomes the virtual base region of the HBT. p ⁺ GaAs contact layer 59
A U-groove reaching the p ^- In _0.5 Ga _0.5 P drift layer 99 is formed from the surface of the Al.
The aAs layer 101 is formed, and Pt / Ti / Pt / Au is formed so as to be substantially included in the AlGaAs layer 101.
A base metal electrode 82 composed of layers is formed. The Ti / Pt / Au layer is p ⁺ Ga as the emitter metal electrode 81.
It is formed on the As contact layer 59. Further, as the collector metal electrode 83, AuGe / Ni / Ti / Au is used.
At the bottom of the U-groove where the layer reaches from the surface to the n ⁺ In _0.5 Ga _0.5 P collector contact layer 98, n ⁺ In _0.5
It is formed on and in contact with the Ga _0.5 P collector contact layer 98. In the structure of FIG. 4, the electric field strength of the tunnel junction layer 3 is controlled by the voltage applied to the base metal electrode 82, and the n ⁺⁺ GaAs layer 31 is used as the virtual emitter region of the HBT, and the virtual base above the p ⁻ InGaP drift layer 99. Electrons are injected into the area. The injected electrons are p ^- I
drifting due to the high electric field in the nGaP drift layer,
The n ⁺ In _0.5 Ga _0.5 P collector contact layer 98 is reached. The base metal electrode 82 and the emitter metal electrode 8
Polyimide or SiO ₂ / Si ₃ N between 1 and
An interlayer insulating film such as ₄ is formed. In order to integrate the tunnel implantation type HBT of FIG. 4, the element isolation region 103 may be formed by proton ion implantation. According to the third embodiment of the present invention, since the peak current of the tunnel junction layer 3 is large, the conversion conductance gm is large and amplification and oscillation in the submillimeter wave band can be performed with high efficiency. or,
Since InGaP has excellent radiation resistance, it is suitable for mounting on an artificial satellite, and can be used for amplification for satellite communication, an oscillating element, a logic circuit, and the like. FIG. 4 is an example, and it goes without saying that the structure of the present invention can be applied to other semiconductor elements such as a resonant tunnel transistor.

[0022]

According to the present invention, the third compound semiconductor region having a higher impurity density is formed above the first and second compound semiconductor layers originally required for the tunnel junction, so that the vapor phase growth is performed. The impurity density of the tunnel junction can be maintained at the high value initially designed, even after various high temperature processes essential to the manufacturing process of the semiconductor device. Therefore, the IV characteristics exhibited by this tunnel junction were good, and the peak current shown in the IV characteristics was a value five times or more that of the prior art. Therefore, a semiconductor device having various tunnel junctions such as a highly efficient tandem structure solar cell and a high-speed tunnel injection HBT can be easily manufactured, and reliability is improved.

According to the present invention, the diffusion of an impurity element having a high diffusion rate such as zinc (Zn) can be suppressed even during a high temperature process of 700 ° C., so that the process design for manufacturing a semiconductor device is facilitated and the productivity is improved. To do.

[Brief description of drawings]

FIG. 1 is a sectional view of a tunnel diode according to a first embodiment of the present invention.

FIG. 2 is a diagram showing forward IV characteristics of the tunnel diode according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a tandem cell type solar cell according to a second embodiment of the present invention.

FIG. 4 is a tunnel injection type H according to a third embodiment of the present invention.
It is sectional drawing of BT.

FIG. 5 is a cross-sectional view of a conventional tunnel diode.

[Explanation of symbols]

2 GaAs bottom cell (lower cell) 3 GaAs tunnel junction layer 4 In _0.5 Ga _0.5 P top cell (upper cell) 7 upper metal electrode layer (front electrode layer) 8 lower metal electrode layer (back electrode layer) 11 p ⁺ GaAs substrate 12 p ⁺ GaAs buffer layer 18 n ⁺ GaAs substrate 19 n ⁺ GaAs layer 21 p ⁺ In _0.5 Ga _0.5 P BSF layer 22 p GaAs base layer 23 n ⁺ GaAs emitter layer 24 n ⁺ In _0.5 Ga _0.5 P window layer 29 n ⁺ In _0.5 Ga _0.5 P pseudo window layer 31 n ⁺⁺ GaAs layer 32 p ⁺⁺ GaAs layer 33 p ⁺⁺ In _0.5 Ga _0.5 P layer 41 p ⁺ In _0.5 Ga _0.5 P-BSF layer 42 pIn _0.5 Ga _0.5 P base layer 43 n ⁺ InGaP emitter layer 44 n ⁺ AlInP window layer 48 p ⁺ In _0.5 Ga _0.5 P pseudo BSF layer 49 pIn _0.5 Ga _0.5 P pseudo base layer 51 n ⁺ GaAs layer 59 p ⁺ GaAs contact layer 71 Au-Ge / Ni / Au film 72 Au plating film 81 Emitter metal electrode 82 Base metal electrode 83 Collector metal electrode 97 Semi-insulating GaAs substrate 98 n ⁺ In _0.5 Ga _0.5 P collector contact Layer 99 p ^- In _0.5 Ga _0.5 P drift layer 101 AlGaAs layer 102 interlayer insulating film 103 element isolation region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/73 31/04 H01L 29/72 31/04 EY

Claims (5)

[Claims] 1. A first compound semiconductor layer of a first conductivity type, a second compound semiconductor layer of a second conductivity type formed on the first compound semiconductor layer, and a second compound semiconductor. A heterojunction layer formed of a third compound semiconductor layer of a second conductivity type and having a band gap larger than that of the second compound semiconductor layer, the heterojunction layer being formed on the upper portion of the layer; Of the compound semiconductor layer is almost completely depleted in a depletion layer formed by a tunnel junction formed between the compound semiconductor layer and the first compound semiconductor layer, and the impurity density of the third compound semiconductor layer is equal to that of the second compound semiconductor layer. A semiconductor device having a tunnel junction layer, characterized in that it has an impurity density of 0.8 times or more. 2. The first and second compound semiconductor layers are made of GaAs, and the third compound semiconductor layer is made of In _1-x G 2.
The semiconductor device having a tunnel junction layer according to claim 1, wherein the semiconductor device is a _x P. 3. The dopant of the second and third compound semiconductor layers is zinc (Zn), and the impurity density of the third compound semiconductor layer is 0.8 to 1.0 × 10 ¹⁹ cm ⁻³ . The semiconductor device having the tunnel junction layer according to claim 1. 4. A first underlayer of the first compound semiconductor layer is provided.
2. A semiconductor device having a tunnel junction layer according to claim 1, wherein a fourth compound semiconductor layer having a conductivity type of 4 and a band gap larger than that of the first compound semiconductor layer is formed. 5. A semiconductor device having a tunnel junction layer according to claim 1, which is a tandem cell type solar cell in which a top cell and a bottom cell are connected in series by the heterojunction layer.