JPH07282598A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device capable of performing a pseudo burn-in impressing a high electric electric field on gate oxidized films of all memory cells while selecting all word lines by one operation with a low power consumption. CONSTITUTION:In this device, a power switching transistor QPB is made to be in an off-state and all address decode signals DW00 to DWi0, MW0 to MWi are made to be in selection states by the high level of a pseudo burn-in test control signal BT. Thus, through currents do not flow in ratio circuits coupled with inputs of respective inverters INV0 to INVi and all word lines WD0 to WDi are driven together to selection levels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for enabling pseudo burn-in in a device test thereof, for example, detecting an initial failure of a gate oxide film in a select transistor of a memory cell. Enables SRAM (Static Random Access
It is related to effective technology when applied to memory).

[0002]

2. Description of the Related Art In a semiconductor memory device such as SRAM, in order to speed up a word line switching operation in response to a change in address, a ratioless circuit is used as a circuit form of a circuit for selectively driving a word line. It is a good idea to use a ratio circuit.

FIG. 5 shows a part of a row main decoder of SRAM studied by the present inventor. The four word lines WD0 to WD3 typified in the figure have the address decode signals DWL00 to DW when the address decode signal MW0 is set to the high level selection level.
It is driven to the selection level corresponding to the one set to the high level from L03. For example, the address decode signal MW
When 0 and DWL00 are set to the high level, a current flows through the insulated gate field effect transistors (hereinafter also simply referred to as MOS transistors) QP00, QN00 and Q0. This allows transistors QP00 and QN
When the inverter INV0 receives the low-level voltage obtained at the coupling node with 00, the word line WD0
Are driven to the word line selection level. At this time, the low-level voltage level generated at the coupling node is made higher than the ground potential by the resistance voltage division by the ON resistance of the MOS transistors QP00, QN00, Q0. Therefore, it is not necessary for the input signals of the inverters INV0 to INV3 to fully swing between the pair of power supply voltages, and the charging / discharging time of the signal at the time of switching the word line can be shortened accordingly, which is a point of speeding up the word line switching operation. Is more advantageous than the ratioless circuit type.

By the way, one of the breakdowns of elements in a MOS transistor is breakdown of a gate oxide film. This is accelerated when foreign substances are mixed into the gate oxide film or pinholes are formed during the manufacturing process.
Further, the progress of breakdown becomes more remarkable with time as the electric field strength formed between the gate and the source is stronger. Such destruction of the gate oxide film is described in "LSI Handbook", page 677, published by Ohm Co. on November 30, 1984. Therefore, it is desirable to detect the defects such as pinholes existing in the gate oxide film as the initial defects of the device.

[0005]

The inventor of the present invention has found that the SRAM
In order to reduce the test cost of the semiconductor memory device such as, for example, at the initial test stage of the manufacturing process such as a wafer probing test, a defect of the gate oxide film included in the select transistor of the memory cell, which is not yet revealed, is detected. I examined that. That is, all the word lines of the semiconductor memory device can be selected at the same time, and a high electric field is applied to all the memory cells at once between the gate and the source of the selection MOS transistor, so that the defects of the gate oxide film which are not revealed are unsatisfactory. Manifest. However, in the test stage in the early stage of the manufacturing process as described above, all the word lines of the semiconductor memory device are collectively packaged in order to detect the defect of the gate oxide film included in the memory cell of the semiconductor memory device including the ratio circuit. It has been found that there are the following problems when making a selection.

For example, an SRAM part of which is shown in FIG.
Supplies a low level voltage to the word line inverter to be brought into the selected state, so that a through current is generated in the ratio circuit coupled to the input of the inverter. Therefore, when all the word lines are in the selected state, the sum of the above-mentioned through currents becomes an extremely large value, and reaches 70 A in a 4 Mbit SRAM, for example. Such a large current cannot be supplied by a test apparatus used for a test in the early stage of the manufacturing process such as a wafer probing test, and it is impossible to select all word lines. Therefore, it is impossible to detect defects inherent in the gate oxide film of the select transistor of the memory cell in the test in the early stage of the manufacturing process, which is effective in reducing the test cost of the semiconductor memory device.

An object of the present invention is to use a ratio circuit in consideration of speeding up the operation of selectively driving a normal word line, and select all the word lines at once by selecting all the word lines at once. Another object of the present invention is to provide a semiconductor memory device capable of applying a high electric field to the gate oxide film of the selection transistor with low current consumption.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

When the pseudo burn-in test control signal is set to the activation level, the row address decoder forces all the row address decode signals to the selection level.
The circuit for selectively driving the word line is formed by a ratio circuit form in which a load transistor and a switching transistor controlled by the row address decode signal are arranged in series between a pair of operating power supplies, and the semiconductor memory device is It is provided for each of the constituent word lines. A power switch transistor, which is turned off in synchronization with the activation of the pseudo burn-in test control signal, is provided between the load transistor of the circuit for selectively driving the word line and the operating power supply. It is provided in.

The power switch transistor is shared by all load transistors forming a circuit for selectively driving the word line.

Further, the data line load transistor provided for each data line is turned off when the pseudo burn-in test control signal is set to the activation level.

Further, when the pseudo burn-in test control signal is set to the activation level, all the column address decode signals are forced to the non-selection level by the column address decoder.

[0014]

According to the above means, when the pseudo burn-in test control signal is set to the activation level, the power switch transistor disconnects the load transistor of the circuit for selectively driving the word line from the operating power supply. It
When the pseudo burn-in test control signal is set to the activation level, the row address decoder sets all the row address decode signals to the selection level. Therefore, all word lines are driven to the selected level without generating a through current in the circuit for selectively driving the word lines.

The sharing of the power switch transistor by all the load transistors of the circuit for selectively driving the word line minimizes the expansion of the circuit scale of the semiconductor memory circuit.

When the pseudo burn-in test control signal is set to the activation level, the data line load transistor is turned off to stop the current supply to the data line.

Further, when the pseudo burn-in test control signal is set to the activation level, all column address decode signals are set to the non-selection level. As a result, all the column selection switch transistors are turned off, and the complementary common data line and the data line are cut off.

[0018]

1 is a circuit block diagram of an SRAM which is an embodiment of a semiconductor memory device according to the present invention. The SRAM shown in the figure is not particularly limited,
It is formed on one semiconductor substrate by a known semiconductor integrated circuit manufacturing technique. In the SRAM, for example, N
A channel type MOS transistor (hereinafter also simply referred to as NMOS) is formed on a P type well region formed on an N type semiconductor substrate, and a P channel type MOS transistor (hereinafter also simply referred to as PMOS) is formed on an N type semiconductor substrate. To be done. The P-type well region as the body gate of the NMOS transistor is coupled to the ground terminal of the circuit, and the N-type semiconductor substrate as the common body gate of the PMOS transistor is coupled to the power supply terminal of the circuit. The configuration in which the MOS transistor forming the memory cell is formed in the well region is α
This is effective in preventing undesired inversion of information stored in the memory cell caused by lines or the like.

The SRAM of this embodiment comprises a plurality of static memory cells MC arranged in a matrix.
The selection terminals of the memory cells arranged in the same row are commonly connected to the corresponding word lines WD0 to WDi, and the data input / output terminals of the memory cells arranged in the same column are respectively connected to the corresponding pair of complementary data lines. D0, BD0-Dn, BDn
Connected to.

Word lines WD0 to WDi shown in FIG.
Are selectively driven by the row predecoder 12 and the row main decoder 14 based on the row address signal Ai of a plurality of bits supplied via the external row address input terminal 13.

Complementary data lines D0 and BD0 shown in FIG.
One of Dn and BDn is a data line load circuit FQ.
0 to FQn, and column selection MOS on the other side
Via transistors DQ0, BD0-DQn, BDQn, they are commonly connected to complementary common data lines CD, BCD, respectively. The complementary data lines D0, BD0-Dn, BD
n is a column selection MOS based on a column address signal Am of a plurality of bits supplied from the external column address input terminal 16.
The transistors DQ0, BDQ0 to DQn, BDQn are selected by being switch-controlled by the column decoder 15.

Further, the complementary common data lines CD, BC
An input / output circuit 17 including a sense amplifier, a write amplifier, and a data input / output buffer (not shown) is connected to each D. The read data from the memory cell MC is amplified by the sense amplifier and applied to the data input / output terminal 18 via the data input / output buffer. The write data input from the data input / output terminal 18 is applied to the write amplifier via the data input / output buffer to drive the complementary common data lines CD and BCD.

FIG. 4 shows an example circuit diagram of the memory cell MC. The memory cell MC shown in the figure is, for example, a memory cell arranged at the intersection of the word line WD0 and the complementary data lines D0 and BD0.

In the memory cell MC, the memory MOS transistors Dr1 and D1 whose gates and drains are cross-connected to each other and whose sources are coupled to the ground potential Vss of the circuit are provided.
r2 and high resistances R1 and R2 made of a poly (polycrystalline) silicon layer provided between the drains of the memory MOS transistors Dr1 and Dr2 and the power supply terminal Vcc. Further, the memory MOS transistor Dr1 (Dr
2), a selection MOS transistor Tr1 (Tr2) is provided between the connection node of the high resistance R1 (R2) and the complementary data line D0 (BD0). Selection MOS above
The gates of the transistors Tr1 and Tr2 are connected to the corresponding word line WD0.

In the memory cell MC, the storage MOS
Although the transistors Dr1 and Dr2 and the resistors R1 and R2 form a kind of flip-flop circuit, the operating point in the information holding state is considerably different from that of the flip-flop circuit in the ordinary sense in order to suppress the power consumption. That is, in the memory cell MC, the resistor R1 is
The gate voltage of the storage MOS transistor Dr2 when the S-transistor Dr1 is turned off is set to a remarkably high resistance value such that it can be maintained at a voltage slightly higher than its threshold voltage. Similarly, the resistance R2 is also set to a high resistance value. In other words, the resistors R1 and R2
Is made high enough to compensate the drain leak current of the storage MOS transistors Dr1 and Dr2. That is, the resistors R1 and R2 are connected to the storage MOS transistor Dr.
It has a current supply capability to prevent the information charges accumulated in the gate capacitances (not shown) of 1 and Dr2 from being discharged.

According to this embodiment, the SRAM is a MOS-I.
Despite being manufactured by C technology, memory cells have N
It is composed of a MOS transistor and a polysilicon resistance element. Although it is possible to use a PMOS transistor instead of the polysilicon resistance element, the memory cell M of this embodiment using the polysilicon resistances R1 and R2.
The size of C can be made smaller than that of a memory cell using a PMOS transistor. That is, when the PMOS transistor is used, the selection MOS transistor Tr
1 and Tr2 need to be separated from each other by a relatively large distance, which causes a useless blank portion. However, if a polysilicon resistance element is used, the selection MOS transistor Tr1 or Tr2 is selected.
It can be formed integrally with the gate electrode and the size thereof can be reduced.

In the SRAM manufacturing process, for example, foreign matter may be mixed into the gate oxide film of the selection MOS transistor forming the memory cell or a pinhole may be formed, which is not yet actualized but causes a problem in the near future. It is required to remove the inherent ones.
Normally, burn-in selects MO for all memory cells
A high electric field is applied to the gate oxide film of the S-transistor, and the gate oxide film including the above-mentioned defect factors is deteriorated and detected in a short time. In this embodiment, all the word lines WD are supplied by the pseudo burn-in test control signal BT supplied from the outside.
0 to WDi are set to the selected state, and the power consumption associated therewith is kept low. This makes it possible to implement a pseudo burn-in in which a high electric field is applied to the gate oxide films of the selection MOS transistors Tr1 and Tr2 of the memory cell MC during the wafer probing test. This will be described in detail below.

In this embodiment, the operation mode for performing the above-mentioned pseudo burn-in (hereinafter simply referred to as the pseudo burn-in mode) is designated by the pseudo burn-in test control signal BT. The pseudo burn-in test control signal BT is
Although not particularly limited, it is a signal that can take a binary logical value supplied through the terminal 11, and a high level indicates the pseudo burn-in mode. If the pseudo burn-in test control signal BT is at low level, the S
This is an operation mode in which normal read / write operations of the RAM are possible (hereinafter simply referred to as normal mode). The burn-in control circuit 10 is also not particularly limited, but is a circuit for converting an external signal level into an internal signal level, for example, TTL.
This is a circuit for converting a level to a MOS level. When the pseudo burn-in test control signal BT is set to the high level, the burn-in control circuit 10 sets the burn-in control signal Bi to the high level. The burn-in control signal Bi is supplied to the row predecoder 12 and the row main decoder 1
4, data line load circuits FQ0 to FQn and column decoder 1
5 is supplied.

Row predecoder 12 shown in FIG. 2 decodes row address signal Ai supplied from external row address input terminal 13 to form a row address decode signal. The row address decode signal shown in the figure is, for example, first row address decode signals DWL00 and DWL obtained by decoding the lower 2 bits of the row address signal Ai.
01, DWL02, DWL03 to DWLi0, DWLi
1, DWLi2, DWLi3, and second row address decode signals MW0 to MWi obtained by decoding the remaining upper bits of the row address signal Ai.

In this embodiment, the row predecoder 12 is used.
Includes an OR gate (not shown), which outputs row address decode signals DWL00 to DWLi3 and MW0 to MWi based on the burn-in control signal Bi and a signal obtained by decoding the row address signal Ai. For example, when the burn-in control signal Bi supplied to the row predecoder 12 is at high level, the OR
All the row address decode signals DWL00 to DWLi3 and M regardless of the row address signal Ai by the gate.
W0 to MWi are set to a high level which is a selection level.
When the supplied burn-in control signal Bi is at low level, the row address decode signal DWL to be output is output.
00 to DWLi3 and MW0 to MWi are set to the levels obtained by decoding the row address signal Ai, respectively.

FIG. 1 shows a part of an example circuit diagram of the row main decoder 14. Word lines WD0-W will be described with reference to FIG.
The circuit part for driving D3 will be described, but the other parts are the same.

The row main decoder 14 shown in FIG.
Although not particularly limited, inverters INV0 to INV3 having outputs coupled to the word lines WD0 to WD3 are provided. The inverters INV0 to INV3 are drive circuits that selectively drive the corresponding word lines WD0 to WD3. Further, switching transistors QN00 to QN03 formed by NMOS transistors and PMOS
Load transistor QP0 formed by a transistor
A ratio circuit composed of 0 to QP03 is provided for each corresponding word line WD0 to WD3, and a connection node between the switching transistors QN00 to QN03 and the load transistors QP00 to QP03 is the inverter I.
They are connected to the inputs of NV0 to INV3, respectively. The gates of the load transistors QP00 to QP03 are ground terminals Vs.
connected to s. The sources of the respective switching transistors QN00 to QN03 are connected to the ground terminal Vss via the switching transistor Q0 formed by an NMOS transistor.

The switching transistors QN00-QN00
The first row address decode signals DWL00 to DWL03 are supplied to the gate of QN03, respectively. The second row address decode signal MW0 is supplied to the gate of the switching transistor Q0. Also for the other word lines WD1 to WDi, the above four first row address decode signals DWL10 to DWL13, DWL are respectively provided.
20 to DWL23, ..., DWLi0 to DWLi3 and one second row address decode signal MW1 to MWi are set as a unit and are similar to the above.

As described above, each inverter INV
Ratio circuits are provided in a one-to-one correspondence with 0 to INVi.
The sources of all the load transistors QP00 to QPi3 forming the ratio circuit are commonly connected to the power transistor QPB formed by the PMOS transistor only arranged in the row main decoder 14, and the power source is supplied via the power transistor QPB. It is connected to the terminal Vcc. A burn-in control signal Bi is supplied to the gate of the power transistor QPB.

The operation when the pseudo burn-in test control signal BT in the row main decoder 14 shown in FIG. 1 is at the low level, that is, the word lines WD0 to WD0 in the normal mode.
The WDi selecting operation will be described. When the pseudo burn-in test control signal BT is at low level, the burn-in control circuit 10 sets the burn-in control signal Bi to low level and the power switch transistor QPB is turned on. When the row address signal Ai is input from the external row address input terminal 13, the row predecoder 12 decodes the row address signal Ai. The first row address decode signals DWL00 to DWL03, DWL10 to DWL1 each having four lines as a unit are decoded according to the decoding result of the lower 2 bits of the row address signal Ai.
A corresponding one of the units of 3, ..., DWLi0 to DWLi3 is set as the selection level. For example, when the row address signal Ai is an address for selecting the word line WD0, the row address decode signal DWL0
0, DWL10, ..., DWLi0 are set to the selection level in parallel. Further, according to the remaining upper bits of the row address signal Ai, the second row address decode signal MW
One of 0 to MWi is set as the selection level. According to this example, the row address decode signal MW0 is set to the selection level. Therefore, the power switch transistor QPB in the ON state and the row address decode signal D of the selection level
Through the switching transistors QN00 and Q0 which are turned on by being supplied with WL00 and MW0, the power supply terminal Vcc and the ground terminal Vss are electrically connected and a through current flows. A low level voltage is obtained at the coupling node of the switching transistor QN00 and the load transistor QP00 by the through current, and is supplied to the inverter INV0. As a result, only the word line WD0 connected to the output of the inverter INV0 is driven to the high level which is the selection level.

In the above, the low level voltage generated at the coupling node is the power switch transistor Q.
The voltage level is set to a voltage level higher than the ground potential by the resistance voltage division by the ON resistance of PB, the load transistor QP00, and the switching transistors QN00 and Q0.
Therefore, the amplitude of the signal supplied to the inverter INV0 is made smaller than the level difference between the pair of power supply voltages. As a result, the circuit for selectively driving the word line by the ratio circuit as in the present embodiment responds to the input of the inverter INV0 necessary for making the word line in the selected state non-selected as compared with the circuit by the ratioless circuit. The charging time is shortened and the word line switching operation is speeded up.

In this embodiment, when the high level pseudo burn-in test control signal BT is supplied through the terminal 11, that is, in the pseudo burn-in mode, the burn-in control circuit 10 outputs the high level burn-in control signal Bi. . Therefore, the power switch transistor QPB is turned off. Further, the row predecoder 12 receives all the row address decode signals DWL00 to DWLi3 regardless of the row address signal Ai supplied thereto.
And MW0 to MWi are selection levels. As a result, all the switching transistors QN00 to QNi3 and Q0 to Qi are turned on, but since the power switch transistor QPB is turned off, a through current is included in the ratio circuit included in the row main decoder 14. Does not occur. At this time, all inverters INV0
Inputs of ~ INVi are conducted to the ground terminal Vss via the switching transistors QN00 to QNi3 and Q0 in the ON state. As a result, the low level ground voltage is supplied to all the inverters INV0 to INVi, and all the word lines WD0 to WDi are driven to the selection level. Therefore, all the word lines WD can be supplied without passing through current to the ratio circuit constituting the row main decoder 14.
0 to WDi are driven to the selection level, and all memory cells M
A high electric field can be applied to the gate oxide films of the C selection MOS transistors Tr1 and Tr2.

In the above, the power switch transistor QPB includes all the load transistors QP00 to QPi forming the ratio circuit in the pseudo burn-in mode.
The row main decoder 14 need not be the only one provided that the disconnection between the power supply terminal 3 and the power supply terminal Vcc is provided. For example, as in the row main decoder 14b whose part is shown in FIG. 3, the power switch transistor QPB0
0 to QPBi3 are the load transistors QP00 to Q
A configuration in which it is provided in one-to-one correspondence with Pi3 is also possible.

The complementary data lines D0, BD0-BDn,
The data line load circuits FQ0 to FQn are connected to Dn as PMOS transistors Q10 and Q1 as shown in FIG.
2 are provided respectively. All data line load circuits FQ
0 to FQn forming the PMOS transistor Q1
A burn-in control signal Bi is supplied to the gates of 0 and Q12. In normal mode, that is, burn-in control signal B
When i is low level, PMOS transistor Q10,
Q12 is switch-controlled to the ON state and the SRAM
Function as a data line load circuit of. In the pseudo burn-in mode, that is, when the burn-in control signal Bi is at high level, all the PMOS transistors Q10,
Q12 is turned off, and complementary data lines D0 and BD0
A through current flowing from BDn, Dn toward the memory cell MC is prevented. Even when all the word lines WD0 to WDi are collectively selected as in the above-described pseudo burn-in mode, this shoot-through current is less than the problematic shoot-through current that occurs in the conventional ratio circuit. In this embodiment, although weak, it is possible to prevent such a weak through current and reduce the power consumption in the pseudo burn-in mode.

The column decoder 15 shown in FIG. 1 receives the column address signal Am and the burn-in control signal Bi supplied from the external column address input terminal 16, though not particularly limited thereto. In the normal mode, based on the decoding result of the supplied column address signal Am, the complementary data lines D0,
A column address decode signal corresponding to a pair to be selected among BD0 to Dn and BDn is set to a selection level. In the pseudo burn-in mode, all column address decode signals are forced to the non-selection level regardless of the column address signal Am.

The column selection transistor DQ0 shown in FIG.
.. to DQn and BDQ0 to BDQn are not particularly limited, but column address decode signals corresponding to complementary data lines D0, BD0 to Dn, BDn connected to the respective gates are supplied from the column decoder 15 to respective gates. To be done. For example, when the low-level burn-in control signal Bi and the column address signal Am for selecting the complementary data lines D0 and BD0 are supplied to the column decoder 15, the column selection transistors DQ0 and BDQ0 are turned on to set the complementary data. Only lines D0 and BD0 are selected. When the high level burn-in control signal Bi is supplied to the column decoder 15, all the column selection transistors DQ0 to DQn and BDQ0 to BDQn are turned off. At this time, even if the data write operation is instructed and the complementary common data lines CD, BCD are driven by the write amplifier of the input / output device 17, all the complementary data lines D0, BD0-Dn, BDn are not selected. This prevents useless current from flowing toward the memory cell MC even if a write operation is instructed in the pseudo burn-in mode.

FIG. 6 is a time chart showing an example of the pseudo burn-in mode of the SRAM in this embodiment. In the SRAM of this embodiment, since the current path inside the row main decoder 14 is cut off by the power switch transistor QPB, even if all the word lines WD0 to WDi are driven to the high level, the value of the consumption current ΣI is substantially the same. Does not increase. However, the power switch transistor Q
In the conventional SRAM without PB, as indicated by the broken line in FIG.
Increases in synchronization with 0 to WDi being driven to a high level.

FIG. 7 shows a 4M device which does not have the means for preventing the through current in the pseudo burn-in mode.
In the bit SRAM, an example graph of the consumption current ΣI in a state in which all the word lines configuring the SRAM are driven to the selection level is shown. During the burn-in operation, a voltage of about 7V-8V is applied to the SRAM. The current ΣI consumed by the SRAM when a voltage of 8 V is applied is about 80 A according to the figure. In the above, the current ΣI is mostly consumed by the through current generated in the ratio circuit that selectively drives the word line. Therefore, in the SRAM of the present embodiment, which cuts off unnecessary current in the pseudo burn-in mode, the consumption current ΣI has a negligible small value.

According to this embodiment, there are the following effects.
In consideration of speeding up the operation of selectively driving the word lines WD0 to WDi in the normal mode, a ratio circuit including switching transistors QN00 to QNi3 and Q0 to Qi and load transistors QP00 to QPi3 is provided for each word line WD0 to WDi. . Further, a power switch transistor QPB is provided, and in the pseudo burn-in mode, the load transistors QP00 to QPi3 and the power supply terminal Vcc
Cut off between and. Therefore, in the pseudo burn-in mode, no shoot-through current flows in the ratio circuit even if all the word lines WD0 to WDi are selected. Thereby, it is possible to achieve both high speed operation of selectively driving the word lines WD0 to WDi in the normal mode and reduction of current consumption in the case of collectively selecting all the word lines WD0 to WDi in the pseudo burn-in mode.

In the pseudo burn-in mode, all row address decode signals DWL00 to DWLi3 and MW0 to MWi are set to the selection level by the row predecoder 12 regardless of the supplied row address signal Ai. As a result, all switching transistors QN00 to QN
i3 and Q0 to Qi are turned on, and the low level ground voltage is supplied to all the inverters INV0 to INVi. Therefore, in the pseudo burn-in mode, all word lines WD can be used even if a through current does not flow in the ratio circuit.
0 to WDi are driven to the selection level. As a result, a high electric field can be applied collectively to the gate oxide films of the selection MOS transistors Tr1 and Tr2 of all the memory cells MC with low current consumption.

The fact that all the word lines can be collectively selected with a low power consumption by the pseudo burn-in mode means that a device other than the burn-in dedicated tester, for example, the selection MOS transistors Tr1 of all the memory cells MC1 in the wafer probing test. A pseudo burn-in can be performed on the gate oxide film of Tr2. Therefore, it becomes possible to detect the non-revealed defects inherent in the gate oxide film earlier and reduce the test cost of the SRAM.

If the power switch transistor QPB is shared by all the load transistors QP00 to QPi3 forming all the ratio circuits, only one row main decoder 14 needs to be provided. Therefore, as compared with the case where a plurality of power switch transistors QPB are provided, the S
The circuit area of the RAM can be reduced.

The PMOS transistors Q10 and Q12 forming the data line load circuits FQ0 to FQn are turned off when the burn-in control signal Bi is at high level. Therefore, in the pseudo burn-in mode, the data line D
The path of the through current flowing from 0, BD0 to Dn, BDn toward the memory cell MC is cut off, and the current consumption can be further reduced.

Further, in the pseudo burn-in mode, all column selection switch transistors DQ0, BDQ0 to DQ are selected.
n and BQDn are turned off. Therefore, even if a write operation is instructed at this time, it is possible to prevent unnecessary current from flowing from the input / output circuit 17 to the memory cell MC via the complementary common data lines CD and BCD. Thereby, the current consumption in the pseudo burn-in mode can be further reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, the structure of the SRAM is not limited to this embodiment. Also, the number of power switch transistors,
The number of load transistors connected to one power switch transistor is not limited to this embodiment. Further, the power switch transistor is not limited to the P-channel type MOS transistor, but may be formed of an N-channel type MOS transistor by using the burn-in control signal supplied to the gate as a reverse phase signal.

Further, the operation of the data line load transistor is not limited to that of this embodiment. For example, the operation is controlled by the chip selection signal in the normal mode, and is turned off in the pseudo burn-in mode regardless of the chip selection signal. It may be one.

The instruction of the pseudo burn-in mode is, for example, T
The present embodiment is not limited to the case where the signal of the external signal level such as the TL level is supplied to the burn-in control circuit. For example, M
A signal having an internal signal level such as the OS level may be directly supplied to the row address decoder or the like without using the burn-in control circuit to instruct.

In the above description, SRA, which is the field of application behind the invention made mainly by the present inventor, is the background.
However, the present invention is not limited to this, and a dynamic random access memory or an electrically erasable programmable memory is used.
The technique is effective when applied to a semiconductor memory device such as a read-only memory or an on-chip memory of a semiconductor integrated circuit such as a microcomputer.

[0055]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, based on the state of the pseudo burn-in test control signal, all the word lines are driven to the selected level without passing any through current through the ratio circuit for selectively driving the word lines. It is possible to reduce power consumption when a high electric field is applied to the gate oxide films of the selection MOS transistors of all memory cells at once. Therefore, in a device such as a tester used for a wafer probing test, which has a relatively small current supply capability, in other words, in a device other than a burn-in dedicated tester, pseudo burn-in is performed on the gate oxide film of the selection MOS transistor of the memory cell. Is possible. As a result, the test cost of the semiconductor memory device can be reduced.

When the pseudo burn-in test control signal is at the inactive level, the word line is selected through the operation of the ratio circuit. Therefore, current consumption can be reduced when a high electric field is collectively applied to the gate oxide films of the selection MOS transistors of all memory cells without affecting the operation of selectively driving the normal word lines.

By sharing a power switch transistor for selectively supplying an operating current to the ratio circuit to all ratio circuits, the circuit scale of the semiconductor memory device is expanded or the chip area is increased by adding the power switch transistor. Can be minimized.

When the pseudo burn-in test control signal is at the activation level, the data line load transistors provided in the respective data lines are turned off,
It is possible to prevent unnecessary current from flowing to the data line via the data line load transistor.

Further, when the pseudo burn-in test control signal is at the activation level, the column address decoder forces all the column address decode signals to the non-selection level regardless of the column address signal. Therefore, all the column selection switch transistors are turned off, and even if a write operation is instructed at this time, no unnecessary current flows from the write circuit of the input / output device to the data line. This makes it possible to further reduce the current consumption during the pseudo burn-in.

[Brief description of drawings]

FIG. 1 is a block diagram of a row main decoder of an SRAM according to an exemplary embodiment of the present invention.

FIG. 2 is an example block diagram of an SRAM according to an embodiment of the present invention.

FIG. 3 is a block diagram of another example of a row main decoder of SRAM according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of an SRAM memory cell according to an embodiment of the present invention.

FIG. 5 is a block diagram of an example of a row main decoder of an SRAM in which a problem has been found during burn-in by the present inventor.

6 is an example time chart illustrating a pseudo burn-in mode of the SRAM shown in FIG.

7 is an explanatory diagram showing an example of a change in current consumption with respect to a power supply voltage when all word lines of the SRAM shown in FIG. 5 are selected.

[Explanation of symbols]

BT pseudo burn-in test control signal Bi burn-in control signal INV0 to INVi inverter QN00 to QNi3 switching transistor Q0 to Qi switching transistor QP00 to QPi3 load transistor QPB power switch transistor WD0 to WDi word line DWL00 to DWLi3 first row address decode signal MW0 to MWi Second row address decode signal 10 Burn-in control circuit 12 Row pre-decoder 14 Row main decoder 15 Column decoder Ai Row address signal Am Column address signal D0 to Dn, BD0 to BDn Complementary data line FQ0 to FQn Data line load circuit DQ0 DQn, BDQ0 to BDQn column selection transistor MC memory cell Tr1, Tr2 selection MOS transistor Dr1, Dr2 memory M OS transistor R1, R2 resistance I through current

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical location H01L 21/8244 27/11 H01L 27/10 381 (72) Inventor Norika Watanabe Nanae-cho, Kameda-gun, Hokkaido Nakajima 145 Hitachi Hokukai Semiconductor Co., Ltd. (72) Inventor Kazuo Yoshizaki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (5)

[Claims] 1. A memory cell array in which memory cells are arranged at intersections of a plurality of data lines and a plurality of word lines, and each word line is provided in a one-to-one correspondence between a pair of operating power supplies. A drive circuit for receiving the voltage at the series connection point of the load transistor and the switching transistor provided to drive the corresponding word line, and decoding the row address signal for selecting the word line, The row address decode signal to be supplied to the control terminal of the switching transistor is formed, and at the predetermined state of the pseudo burn-in test control signal supplied from the outside, all the row address decode signals are selected at the selected level regardless of the row address signal. Row address decoder forcibly applied to each load and each load in synchronization with the above predetermined state of the pseudo burn-in test control signal. A semiconductor memory device comprising: a power switch transistor for stopping the supply of power to the transistor. 2. A memory cell array in which memory cells are arranged at intersections of a plurality of data lines and a plurality of word lines, and each word line is provided in a one-to-one correspondence between a pair of operating power supplies. A drive circuit for driving the corresponding word line by receiving the voltage at the series connection point between the load transistor and the first switching transistor, and a plurality of the first switching transistors as one unit, respectively. Separately, a plurality of second switching transistors connected to one of the operating power supplies and a row address signal for selecting a word line are decoded, and the first unit is common to each of the above units and constitutes each unit. Row address decode signals to be separately supplied to the control terminals of the switching transistors of the above, and the control terminals of the respective second switching transistors. And a second row address decode signal to be separately supplied to each of the first and second row address decode signals in the predetermined state of the pseudo burn-in test control signal supplied from the outside. A row address decoder for forcing the row address decode signal of 1 to a selection level, and a power switch transistor for stopping the supply of power to each load transistor in synchronization with a predetermined state of the pseudo burn-in test control signal. A semiconductor memory device comprising: 3. The semiconductor memory device according to claim 1, wherein the power switch transistor is a transistor shared by all load transistors. 4. A data line load transistor, which is controlled to be in an off state in synchronization with the predetermined state of the pseudo burn-in test control signal, is provided in each data line. 4. The semiconductor memory device according to claim 1. 5. A column selection switch transistor, which is provided separately between each data line and a common data line, for selectively conducting both, and a column address signal for selecting the data line is decoded. The column address decode signal to be supplied to the control terminals of the respective column selection switch transistors is formed, and at the predetermined state of the pseudo burn-in test control signal supplied from the outside, all column address signals are irrespective of the column address signal. 5. The semiconductor memory device according to claim 1, further comprising: a column address decoder for forcing a code signal to a non-selection level of a column selection switch transistor by a column address.