JPH07161703A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain damage on a semiconductor device by a bias ECR plasma CVD method, and form a high reliability insulating film with excellent controllability which has an excellent step-covering form. CONSTITUTION:Firstly a bias ECR plasma CVD process is performed for a specified period by introducing film forming material gas and argon gas, and a silicon oxide film 3 having an overhang form to some extent is formed on a metal wiring 2 as shown by (A). Secondly the introduction of film forming gas is interrupted, and a sputter etching process is performed for a specified period. By primarily etching the overhang part of the silicon oxide film 3, a form shown by (B) is obtained. After that, the bias ECR plasma CVD process and the sputter etching are sequentially repeated, and an insulating film 3 having excellent step-covering form wherein the part between the metal wirings 2 and 2 is filled without voids and flattened as shown by (H) is finally formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device including a step of forming an insulating film such as an interlayer insulating film or a passivation film in a manufacturing process of a semiconductor integrated circuit device. In particular, the present invention relates to a method of manufacturing a semiconductor integrated circuit device, which is characterized by a method of forming an insulating film such as an interlayer insulating film or a passivation film by a bias ECR plasma CVD method.

[0002]

2. Description of the Related Art At present, in a manufacturing process of a semiconductor device typified by LSI (Large Scale Integrated Circuit), an ECR (Electron Cyclotron Resonance) plasma CVD method is actively studied as a means for forming an interlayer insulating film and a passivation film. Has been done. The ECR plasma CVD method is capable of forming a film at a low temperature, the amounts of energy of radicals and ions used are uniform, and the substrate is less damaged by plasma as compared with the conventional high frequency plasma CVD method. Furthermore, it has many advantages such as film formation in a high vacuum region.

Further, a high frequency bias is applied to the substrate and a gas such as argon is added to cause film formation and sputter etching by ions such as argon to occur at the same time as the film formation, whereby a bias ECR plasma CVD method with improved step coverage. Is proposed. Bias ECR plasma C
In the VD method, a high frequency bias is applied to the substrate, and the cations ionized by the ECR plasma are attracted by the self-bias effect of the ion sheath generated near the substrate,
This is a method that utilizes the effect of sputter etching with cations. Since sputter etching is more prominent in the inclined portion of the substrate surface, it is attracting attention as a method of preferentially etching the overetched portion of the insulating film and filling the metal wiring with no voids.

Generally, the bias ECR plasma CVD method is a competitive reaction due to simultaneous progress of film formation and etching.
The speed of sputter etching is proportional to the magnitude of high frequency power applied to the substrate. In order to obtain a sputter etching rate that opposes the high film formation rate that is one of the characteristics of the ECR plasma CVD method, a general bias ECR plasma CV is used.
The D method requires at least 600 high-frequency power applied to the substrate.
W, usually about 1 kW is used.

However, when such a high-frequency high-frequency bias is applied, the following problems occur due to the application of high high-frequency power even though the step coverage is improved.
One of the problems is that the metal wiring itself is etched by the sputtering of cations such as argon ions, which shortens the life of the wiring. Another problem is that charge-up on the surface of the insulating film occurs, local discharge occurs between the substrate surface and plasma, foreign matter is generated, and the surface property is significantly deteriorated. These problems become major problems in realizing laminated wiring. Further, the general bias ECR plasma CVD method has a problem that it is difficult to set the conditions because it is a competitive reaction due to simultaneous progress of film formation and sputter etching.

The following method has been proposed as a method for solving these problems. In the initial process of forming the insulating film, a high frequency bias is not applied or a low output high frequency bias is applied to prevent damage to the metal wiring, and then a higher output high frequency bias is applied to form the insulating film. (See Japanese Patent Laid-Open No. 3-280539). However, according to this method, damage to the metal wiring can be avoided, but charge-up on the surface of the insulating film does not occur in the step of forming the insulating film by applying a high-frequency bias of higher output, for example, 600 W output. There is an unavoidable problem of foreign matter generation and dielectric breakdown due to local discharge.

As another proposal, a step of performing only film formation without applying a high frequency bias to the substrate and without introducing a gas that becomes a sputtering gas such as argon gas, and a step of applying a high frequency bias and cations such as argon. In JP-A-3-52232, a method of repeating the step of performing only sputter etching has been proposed. However, since the method is a method in which the film forming step and the sputter etching step are separated and the film forming only step and the sputter etching only step are repeated, the step coverage due to the simultaneous progress of the film forming and the sputter etching. It does not take advantage of the improved bias ECR plasma CVD process feature. Therefore, the following problems occur. EC in general
In the case of the R plasma CVD method, it is well known that when the film is formed without applying a high frequency bias to the substrate, the shape of the insulating film on the metal wiring becomes an overhang shape. Cause voids in the space. In the case of the ECR plasma CVD method, the film formation rate is generally high, and a silicon oxide film of several thousand is used.
The value is Å / min to several μm / min. Therefore, as the element size of the semiconductor device and the miniaturization of the metal wiring progress, the problem of the generation of voids due to the overhang shape becomes decisive within a very short time after the start of the insulating film formation, and then the sputter etching is performed. However, it is impossible to eliminate the void. To solve this problem, a very short time after the film formation process is started, for example, the film formation rate is 1 μm / min, and the design rule line and space (L / S) is 0.5 μm / 0.5 μm. In some cases, it is necessary to keep the time under control for about 10 to 20 seconds, but even if the plasma state is unstable, the reproducibility is low and the process becomes very unstable.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has the features of the bias ECR plasma CVD method, yet suppresses damage to a semiconductor device and has an excellent step. It is characterized in that a highly reliable insulating film having a coating shape is formed with good controllability.

[0009]

According to the present invention, in the step of forming an insulating film, a gas serving as a film-forming raw material and an element which becomes an cation by ionization are applied while applying a low-power high-frequency bias to a substrate. A first step of simultaneously introducing a gas containing the same and performing film formation and sputter etching with cations, and applying a low-output high-frequency bias to the substrate,
A semiconductor device characterized by repeating a second step of introducing only a gas containing an element which is ionized and becomes a cation without introducing a gas as a film-forming raw material and performing only sputter etching by the cation. Is a manufacturing method. Thus, by repeating the film formation by the bias ECR plasma CVD process and the sputter etching process by positive ions, damage to the semiconductor device is suppressed, the metal wiring is filled without voids, and excellent step coverage is provided. An insulating film is formed.

In a preferred embodiment, the high frequency bias power is set to 50 to 500W. Preferred conditions in the present invention are that the film forming rate in the first step is A (Å / min), the film forming time per one time in the first step is t ₁ (minute), and the second step is When the etching rate is B (Å / min) and the etching time per one time in the second step is t ₂ (min), the following relational expression is set. 0.4 ≦ A · t ₁ / B · t ₂ ≦ 20

The ECR plasma CVD apparatus used in the present invention is an ECR plasma CVD apparatus capable of applying a high frequency bias to a substrate. Most of the high-frequency power supplies that are generally prepared have an output capability of 1 kW or more. However, in the present invention, the effect can be obtained with a low-frequency high-frequency bias. Therefore, it is sufficient to prepare a high-frequency power supply of 500 W class at most.

The gas used for sputter etching in the present invention may be any gas containing an element which is ionized to become cations. Usually, Ar (argon) gas is used because of its sputtering efficiency and easy handling. The most appropriate is to choose. Since He (helium) is also ionized to supply He ions, it can be used alone or as a mixed gas with Ar gas. The raw material gas used for forming the insulating film is preferably silane (SiH ₄ ) and oxygen when the film to be formed is a silicon oxide film, and is preferably silane and nitrogen when the film to be formed is a silicon nitride film.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a process of forming a silicon oxide film according to the present invention in order of steps. Silane and oxygen were used as film forming source gases, and argon was used as a gas for sputtering. In the figure, (A), (C),
(E) and (G) show the shapes after the so-called bias ECR plasma CVD process, which is performed by introducing both the film forming source gas and the sputtering gas. On the other hand, (B),
(D), (F), and (H) show the shapes after the sputter etching step performed by introducing only the sputtering gas. The output of the high frequency bias applied to the substrate in both steps was 250W.

First, when the bias ECR plasma CVD process is performed for a predetermined time, the silicon oxide film 3 on the metal wiring 2 on the substrate 1 has an overhang shape as shown in FIG. In normal bias ECR plasma CVD, a high-power high-frequency bias is applied so that such an overhang shape does not occur, but since the present invention has a sputter etching step later, some overhang shape can be tolerated.

Next, the introduction of the film forming source gas is stopped, and the process proceeds to the sputter etching process. The shape when the sputter etching step is performed for a predetermined time is such that the overhang portion is preferentially sputter-etched and the result is as shown in (B). When the bias ECR plasma CVD process is further performed thereafter, the shape shown in (C) is obtained, and when the sputter etching is further performed thereafter, the shape shown in (D) is obtained.

Thus, the bias ECR plasma CVD
By successively repeating the steps and the sputter etching step, finally, as shown in (H), an excellent step coverage shape in which the metal wirings 2 and 2 are filled without voids and flattened is also formed. The insulating film 3 having is formed. As described above, by repeating the bias ECR plasma CVD process and the sputter etching, it is possible to form the insulating film having excellent step coverage even with a low output high frequency bias while suppressing damage to the semiconductor device.

Example 1 An aluminum thin film of about 900 was formed on a 4-inch single crystal silicon wafer by a known method.
Formed to a thickness of 0Å, and line and space (L / S) = 0.7μm / 0.7μ by photoengraving and etching.
The substrate patterned to m was used. Bias ECR
The conditions of plasma CVD and sputter etching are as follows.

Bias ECR plasma CVD step SiH ₄ flow rate: 10 sccm O ₂ flow rate: 15 sccm Ar flow rate: 20 sccm Sputter etching step Ar flow rate: 20 sccm Both steps have a pressure of 1 mTorr, a substrate temperature of 150 ° C., a microwave power of 700 W and a high frequency ( 13.56 MHz) power is 250W.

The conditions of each process are set as described above, the unit time of the bias ECR plasma CVD process is 3 minutes, the unit time of the sputter etching process is 5 minutes, and the number of times of repeating these alternately is 8 times. . As a result, a silicon oxide film was obtained in which the space between the metal wirings was filled without voids and the surface property was flat.

(Embodiment 2) Same as Embodiment 1, but the line and space (L / S) of the substrate is 0.5 μm.
/0.5 μm, the unit time of the bias ECR plasma CVD process was 2 minutes, the unit time of the sputter etching process was 6 minutes, and the number of repetitions was 8 times. as a result,
A silicon oxide film was obtained in which the metal wiring was filled in without voids and the surface property was flat.

The first step, the bias ECR plastic
Zuma CVD process deposition rate is A (Å / min), once
Film formation time, that is, the unit time of the first step is t
₁(Minutes) Second step, sputter etch
Etching rate of the etching process is B (Å / min), once
Etching time, that is, the unit time of the second step
t ₂(Minutes)

FIG. 2 shows the bias ECR plasma CVD while changing the output of the high frequency bias applied to the substrate.
The film-forming speed at the time of forming a silicon oxide film by the method is shown. The film forming rate when the high frequency bias power is 0 is the film forming rate when the bias is not applied, and is about 800 Å / min. On the other hand, the film forming rate A when the high frequency bias power of 250 W is applied can be read from the graph as about 600 Å / min. Further, from this result, it is considered that the apparent etching rate B obtained by applying the high frequency bias of 250 W is 800-600 = 200 (Å / min). Here, first the product A · t ₁ the deposition rate A and the unit time t ₁ step, the ratio A and the product B · t ₂ between the etching rate B and the unit time t ₂ of the second step Evaluate the repetition cycle of both processes by t ₁ / B · t ₂ .

Table 1 shows the results including the measurements of Examples 1 and 2 and changing the conditions, and evaluating whether or not the metal wiring can be embedded without any space.

[0024]

[Table 1]

In the condition column, for example, (5,3) × 5 is the first
Unit time for the process is 5 minutes, unit time for the second process is 3
It shows that the number of repetitions is 5 minutes. The smaller the line and space (L / S) is, the more difficult it is to form a good insulating film. In the table, ○ indicates the result that the interlayer film between the metal wirings can be embedded without any scratch, and the mark x indicates Shows the result of occurrence.

[0026]

According to the present invention, by repeating the bias ECR plasma CVD process and the sputter etching process with a low-power high-frequency bias, damage to the semiconductor device can be suppressed, and the metal wiring can be embedded without voids. In addition, it is possible to obtain an insulating film having a flat surface property and excellent step coverage. Further, the process of the present invention is a bias ECR plasma CVD process and a sputter etching process, and various wiring dimensions can be dealt with by optimizing parameters that are easy to control, such as the time and the number of repetitions. Is easy to obtain and has excellent controllability.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a silicon oxide film forming process in one example.

FIG. 2 is a diagram showing a film forming rate with respect to a high frequency bias power in one example.

[Explanation of symbols]

 1 Silicon substrate 2 Metal wiring 3 Silicon oxide film

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[Procedure amendment]

[Submission date] September 2, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

Further, a high frequency bias is applied to the substrate and a gas such as argon is added to cause film formation and sputter etching by ions such as argon to occur at the same time as the film formation, whereby a bias ECR plasma CVD method with improved step coverage. Is proposed. Bias ECR plasma C
In the VD method, a high frequency bias is applied to the substrate, and the cations ionized by the ECR plasma are attracted by the self-bias effect of the ion sheath generated near the substrate,
This is a method that utilizes the effect of sputter etching with cations. Since sputter etching appears more prominently in the inclined portion of the substrate surface, the over-etched portion of the insulating film is preferentially etched to form voids between the metal wirings (used in this specification as "void"). It is attracting attention as a method of embedding without using.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

In a preferred embodiment, the high frequency bias power is set to 50 to 500W. Preferred conditions in the present invention are that the film forming rate in the first step is A (Å / min), the film forming time per one time in the first step is t ₁ (minute), and the second step is When the etching rate is B (Å / min) and the etching time per one time in the second step is t ₂ (min), the following relational expression is set. 0.4 ≦ A · t ₁ / B · t ₂ ≦ 2.0

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/768

Claims (3)

[Claims] 1. An EC capable of applying a high frequency bias to a substrate
In a method of manufacturing a semiconductor device including a step of forming an insulating film on a substrate by R plasma CVD method, in the step of forming the insulating film, a gas used as a film forming raw material while applying a low-power high-frequency bias to the substrate. And a gas containing an element which is ionized to become cations at the same time, so that film formation and sputter etching by cations are simultaneously performed, and while applying a low-power high-frequency bias to the substrate, A semiconductor device characterized by repeating a second step of introducing only a gas containing an element which is ionized and becomes a cation without introducing a gas as a film-forming raw material and performing only sputter etching by the cation. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the power of the high frequency bias applied to the substrate is in the range of 50 to 500 W. 3. The film forming rate in the first step is A (Å /
Min), and the film formation time for each of the first steps is t
₁ (min) and the etching rate in the second step is B
3. The semiconductor device according to claim 1, wherein the condition is set such that the following relational expression is satisfied, where (Å / min) and an etching time per one time of the second step are t ₂ (min). Manufacturing method. 0.4 ≦ A · t ₁ / B · t ₂ ≦ 20