JP2603989B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology effective when applied to dry etching of a silicon oxide film.

[Conventional technology]

For the current status and trends of dry etching technology and equipment used in the manufacturing process of semiconductor devices, for example,
It is described in “Industrial Materials, November 1985, Separate Volume”, pages 119 to 124, issued by the Industrial Research Institute, Inc. on November 10, 1985.

In the process of forming wiring of a semiconductor integrated circuit, when a fine contact hole is formed by drilling a silicon oxide film such as a SiO ₂ film or a polysilicon film on a silicon single crystal substrate, planar plasma etching (PPE) is mainly used.
And a dry etching technique such as reactive ion etching (RIE).

In order to perform the planar plasma etching or the reactive ion etching, a parallel plate type dry etching apparatus for applying a high frequency to a counter electrode of a semiconductor wafer (hereinafter, referred to as a wafer) has been used. Further improvements are the triode method, in which another electrode is added to a parallel plate electrode, the magnetron discharge method, in which a magnetic field is provided on the cathode, or the ECR method, which uses the interaction between a magnetic field and microwaves. Etching equipment is also used.

As a reaction gas for etching a silicon oxide film using the above dry etching apparatus, CHF ₃ (+ O ₂ ), CHF ₃ + C ₂ F _{6 and the} like are generally known, and high-pressure single Ar + CF ₄ + CHF obtained by adding argon (Ar) or helium (He) to CF ₄ + CHF ₃ system gas
_{A 3-} system gas or a He + CF ₄ + CHF _3- system gas is used.

[Problems to be solved by the invention]

2. Description of the Related Art As semiconductor integrated circuits have become denser and more highly integrated, there has been a demand for an etching technique capable of performing high-precision and fine processing, and various etching characteristics such as shape controllability, uniformity, and selectivity. Is required to be further improved.

In consideration of the above points, the present inventor uses an Ar + CF ₄ + CHF ₃ -based reaction gas or a He + CF ₄ + CHF ₃ -based reaction gas in a high-pressure (several Torr) single wafer processing apparatus in etching a silicon oxide film. If they did, they found the following problems.

That is, the Ar + CF ₄ + CHF ₃ -based reaction gas has the advantage of a high etching rate, but has poor shape controllability due to a small effect of protecting the side wall of the contact hole, and thus the cross-sectional shape of the contact hole is barrel-shaped or inverted. As a result, the contact hole becomes
There is a disadvantage that the step coverage when the Al film is applied is reduced.

On the other hand, when He + CF ₄ + CHF ₃ type reaction gas is used,
Since the sidewall protection effect of the carbon-based polymer is recognized, the shape controllability of the contact hole is better than that of the above-mentioned Ar + CF ₄ + CHF ₃ -based reaction gas, but on the other hand, the etching rate is low and the selectivity to silicon is low. However, it has disadvantages such as low etching uniformity and poor etching uniformity.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of improving the etching characteristics of a silicon oxide film.

The above and other objects and novel features of the present invention are:
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, when a predetermined portion of the silicon oxide film is processed by dry etching, a method using a reaction gas consisting of CF ₄ + CHF ₃ + Ar + He is used.

[Action]

According to the above-described means, it is possible to improve various etching characteristics such as shape controllability, uniformity, and selectivity when processing a silicon oxide film.

〔Example〕

1A to 1D are cross-sectional views of a main part of a semiconductor wafer showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of a dry etching apparatus used in the present embodiment. FIG. 3 is a graph showing the relationship between the amount of He added to the reaction gas used in the present embodiment and the taper angle of the contact hole.

The dry etching apparatus used in the present embodiment is a parallel plate type dry etching apparatus 1 using an anode coupling method, and a main part thereof is a processing chamber whose inside is maintained at a predetermined degree of vacuum as shown in FIG. 2 and gas supply sources 3a to 3c for supplying a reaction gas to the processing chamber 2.

In the center of the inside of the processing chamber 2 made of a stainless steel plate or the like coated on its surface with a fluororesin, a disk-shaped cathode electrode 4 also serving as a wafer stage and a disk-shaped anode electrode 5 are spaced apart by a predetermined distance. They are arranged in parallel.

The cathode electrode 4 is maintained at a predetermined temperature by an external temperature controller 6, while the anode electrode 5
Is connected to an external high-frequency power supply 7, and a high-frequency voltage is applied between the power supply 7 and the cathode electrode 4.

A load lock chamber 8 is provided outside the side wall of the processing chamber 2, and a semiconductor wafer 10 stored in a loader 9 is mounted on the cathode electrode 4 of the processing chamber 2 via a robot hand (not shown) or the like. Is to be placed.

An exhaust pipe 11 is connected to the bottom of the processing chamber 2 so that the gas in the processing chamber 2 is exhausted.

In the center of the anode electrode 5, external gas supply sources 3a to 3c
Connected to the gas supply pipe 12, CF ₄ , CHF ₃ , Ar
Reaction gas containing the four gases of He and He
Is supplied to the processing space between the anode electrode 5 and the cathode electrode 4.

The gas supply sources 3a to 3c are each filled with a CF ₄ / CHF ₃ mixed gas, Ar gas, and He gas in individual containers, and the mixing ratio and the supply amount are controlled by opening and closing the valves 13a to 13c. It is set to a desired value.

Next, a dry etching step of the semiconductor wafer 10 using the parallel plate type dry etching apparatus 1 will be described.

As shown in FIG. 1 (a), prior to the dry etching step, first, a semiconductor wafer 10 made of a silicon single crystal having a predetermined resistivity is steam-oxidized at, for example, about 1000 ° C., and the surface thereof is made of SiO _2. After the film (silicon oxide film) 14 is formed, a predetermined integrated circuit element (not shown) is formed in the active region in accordance with a usual method of a wafer process, and then, the surface of the SiO ₂ film 14 is formed by photoresist / etching. A resist mask 15 is formed.

Thereafter, the semiconductor wafer 10 is transferred to the loader 9 of the parallel plate type dry etching apparatus 1, and is placed on the cathode electrode 4 of the processing chamber 2 via the load lock chamber 8.

Next, after the pressure inside the processing chamber 2 is reduced to, for example, about several Torr, a predetermined amount of a reaction gas composed of CF ₄ + CHF ₃ + Ar + He is supplied to the processing chamber 2 from the gas supply sources 3a to 3c.

Next, when a high-frequency voltage is applied between the anode electrode 5 and the cathode electrode 4, dry etching is started by the reaction gas which has been turned into plasma, and a contact hole for establishing conduction with the substrate at a predetermined position of the SiO ₂ film 14. 16 are formed (FIG. 1 (b)).

At this time, by using a reaction gas composed of CF ₄ + CHF ₃ + Ar + He, the sectional shape of the contact hole 16 can be made a forward tapered shape, that is, a downward tapered shape.

That is, as shown in FIG. 3, when He is added to the CF ₄ + CHF ₃ + Ar-based reaction gas, the taper angle θ of the contact hole 16 decreases as the amount of He added increases, and the cross-sectional shape of the contact hole 16 decreases. Changes from a reverse taper or upward taper to a forward taper or downward taper.

The magnitude of the taper angle θ at this time also depends on the pressure in the processing chamber 2, and the lower the pressure, the smaller the taper angle θ tends to be.

At that time, since Ar was added to the reaction gas used in this example, even when the addition amount of He was increased,
The defects of the CF ₄ + CHF ₃ + He-based reaction gas, such as a decrease in the etching rate, a decrease in the selectivity to silicon, and a non-uniform etching, hardly occur.

After the forward tapered contact hole 16 is formed in this manner, a conductive film made of Al or an Al alloy is deposited on the surface of the semiconductor wafer 10 by using, for example, a magnetron sputtering method. By patterning the film, a first layer wiring 17 electrically connected to the substrate via the contact hole 16 is formed (FIG. 1 (c)).

Next, SiO _{2 was} deposited on the first layer wiring 17 by CVD.
After the formation of the interlayer insulating film 18 made of, dry etching is performed in the processing chamber 2 of the parallel plate type dry etching apparatus 1 to form an interlayer connection hole 19 reaching the first layer wiring 17.

Also in this case, the cross-sectional shape of the interlayer connection hole 19 can be made to be a forward taper by using a reaction gas composed of CF ₄ + CHF ₃ + Ar + He.

Next, in the same manner as in the case where the first layer wiring 17 is formed,
By depositing a conductive film on the surface of the interlayer insulating film 18 and patterning the conductive film, the first layer wiring is formed through the interlayer connection hole 19.
A second layer wiring 20 electrically connected to 17 is formed.

Finally, on the surface of the second layer wiring 20, for example, a reduced pressure CV
A passivation film 21 made of silicon nitride (Si ₃ N ₄ ) or the like is applied by using the D method, and a predetermined portion thereof is opened to form an electrode pad 22 (FIG. 1 (d)).

As described above, according to the present embodiment, the following effects can be obtained.

(1). When the contact hole 16 and the interlayer insulating hole 20 are formed by the parallel plate type dry etching apparatus 1, CF ₄ + CHF
By performing dry etching using a reaction gas composed of ₃ + Ar + He, the cross-sectional shapes of the contact hole 16 and the interlayer insulating hole 20 are tapered forward without reducing the etching rate, the selectivity to silicon, and the uniformity of etching. Can be shaped.

(2). According to the above (1), the step coverage of the conductive film deposited on the contact hole 16 and the interlayer insulating hole 20 is improved, so that the reliability of the first layer wiring 17 and the second layer wiring 20 is improved.

(3). By the above (1), miniaturization of the first layer wiring 17 and the second layer wiring 20 is promoted.

(4). By the above (1), the yield of the dry etching process is improved.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, in the embodiment, the case where the present invention is applied to the process of forming a contact hole or an interlayer insulating hole is described, but the present invention can be applied to all processes of processing a silicon oxide film by dry etching.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, upon the silicon oxide film formed on the surface of the wafer processed by dry etching, CF ₄ and CHF _3, A
By using a reaction gas composed of r and He, various etching characteristics such as shape controllability, uniformity, and selectivity can be improved.

[Brief description of the drawings]

1A to 1D are cross-sectional views of a main part of a semiconductor wafer showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of a dry etching apparatus used in the present embodiment. FIG. 3 is a graph showing the relationship between the amount of He added to the reaction gas used in the present embodiment and the taper angle of the contact hole. DESCRIPTION OF SYMBOLS 1 ... Parallel plate type dry etching apparatus, 2 ... Processing chamber 2, 3a-3c ... Gas supply source, 4 ... Cathode electrode, 5 ...
... assode electrode, 6 ... temperature controller, 7 ... high frequency power supply, 8
...... load lock chamber, 9 ...... loader, 10 ...... semiconductor wafer, 11 ...... exhaust pipe, 12 ...... gas supply pipe, 13 a to 13 c ...... valves, 14 ...... SiO ₂ film (silicon oxide film), 15 ... resist mask, 16 ... contact hole, 17 ... first layer wiring, 18 ... interlayer insulating film (silicon oxide film), 19 ... interlayer insulating hole, 20 ... second layer wiring, 21 ... passivation Film, 22 ... electrode pad, θ ... taper angle.

Claims (2)

(57) [Claims] When a silicon oxide film formed on a surface of a semiconductor wafer is processed by dry etching, CF ₄ and C
And HF _3, a method of manufacturing a semiconductor device, which comprises using the Ar, the reaction gases consisting of He. 2. The method according to claim 1, wherein a parallel plate type dry etching apparatus of an anode coupling type is used.
The manufacturing method of the semiconductor device described in the above.