JPH0677247A - Formation of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to forum a shallow junction by a method wherein after Si, F and Ge are preimplanted in order, B or BF2 is implanted and an annealing is performed. CONSTITUTION:For example, <28>Si<+> ions are implanted in an Si substrate at a dose of 1X10<15>cm<-2> in 40keV, then, <19>F<+> ions are implanted at a dose of 2X10<15>cm<-2> in 25keV and moreover, <72>Ge<+> ions are implanted at a dose of 2X10<14>cm<-2> in 35keV to perform preimplantation of three times in all and an Si layer, an F impurity containing layer and a Ge impurity containing layer are formed in order on the Si substrate. After that, B is implanted at a dose of 1X10<15>cm<-2> in 10keV and a lamp annealing is performed for 30 seconds at 900 deg.C. Thereby, even in immediately after the implantation of the B and even in after the annealing, a channeling tale is inhibited from diffusing and a shallow junction of a depth of 0.15mum or thereabotus can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a shallow diffusion layer of a pMOS transistor.

[0002]

2. Description of the Related Art Conventionally, the source of a pMOS transistor
In the process of forming a drain, in order to form a shallow pn junction in a silicon substrate, after impurity atoms such as Si, Ar, F, As, and Ge are pre-injected once or twice, B or BF ₂ is reduced in energy. It was common to form a shallow pn junction by controlling the impurity profile by controlling the impurity profile by controlling the channeling tail.

[0003]

However, in the above-mentioned conventional method, since the channeling tail is suppressed immediately after the implantation of B or BF ₂ , shallow implantation can be performed, but after the subsequent annealing, the tail portion remains It was difficult to form a shallow pn junction by diffusion. That is,
FIG. 3 shows the concentration distribution of B when Si is pre-implanted once, B is then implanted, and then annealed. Immediately after B implantation, the depth is about 0.1 μm as shown by the solid line. While shallow implantation is possible, just after annealing, the tail portion diffuses and the depth becomes 0.2 μm or more as shown by the dotted line.

It is an object of the present invention to provide a method for forming a semiconductor device, which can suppress the diffusion of the channeling tail portion as described above and form a shallow junction even after heat treatment.

[0005]

According to the present invention, in the process of forming the source / drain of a pMOS transistor,
A method of forming a semiconductor device is characterized in that after Si, F, and Ge are sequentially pre-implanted, B or BF ₂ is implanted and then annealed.

[0006]

[Operation] According to the present invention, pre-implantation of Si, F, and Ge is performed.
First, Si is implanted to amorphize the deep portion, then F, which has the effect of reducing the leakage current, is implanted, and Ge is further implanted to amorphize the vicinity of the surface.
Alternatively, since BF ₂ is injected and diffused, the channeling tail of B or BF ₂ at the time of injection can be suppressed, and the diffusion of this tail part can also be suppressed to form a shallow junction and at the same time reduce the leakage current. can do.

[0007]

EXAMPLES Examples of the present invention will be described below.
First, ²⁸ Si ⁺ ions are implanted into a silicon substrate at an energy of 40 keV at a dose of 1 × 10 ¹⁵ cm ^-2 , and then ¹⁹ F ⁺ ions are implanted at 25 keV at a dose of 2 × 10 ¹⁵ cm ^-2 , and further ⁷² Ge ^+.
Ions were implanted at a dose of 2 × 10 ¹⁴ cm ^-2 at 35 keV, and a total of three pre-implantations were performed to sequentially form a Si layer, an F impurity-containing layer, and a Ge impurity-containing layer in the silicon substrate. The impurity profiles of F and Ge at that time are shown in FIG. Then, 1 × 10 ¹⁵ cm ^-2 of B was implanted at an energy of 10 keV and lamp annealing was performed at 900 ° C. for 30 seconds. The results of the concentration distribution immediately after the B implantation and after the annealing are shown in FIG.

As is apparent from FIG. 2, the diffusion of the channeling tail is suppressed immediately after the implantation of B and after the annealing, and it is understood that a shallow junction having a depth of about 0.15 μm can be realized. Thus, by implanting three types of ions with different energy doses, diffusion of the channeling tail is suppressed and a shallow junction is realized. In the above embodiment, only the case of B injection has been described, but the present invention is not limited to this, and even if BF ₂ is injected, the same action and effect can be obtained.

[0009]

As described above, according to the present invention, the pre-implantation is performed three times, the deep portion is first amorphized by Si implantation, then the leak current is reduced by F implantation, and Ge is further implanted near the surface. After amorphizing, B or
Since BF ₂ is injected and annealed, B or
It is possible to suppress the diffusion of the channeling tail portion of BF ₂ , form a shallow junction, and at the same time reduce the leakage current.

[Brief description of drawings]

FIG. 1 is a characteristic diagram showing F and Ge concentration distributions after pre-injection according to the method of the present invention.

FIG. 2 is a characteristic diagram showing B concentration distribution immediately after B implantation and after annealing according to the method of the present invention.

FIG. 3 is a characteristic diagram showing a B concentration distribution immediately after B implantation and after annealing by a conventional method.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location 8617-4M H01L 21/265 Z 8617-4MA

Claims (1)

[Claims] 1. A method for forming a semiconductor device, which comprises sequentially pre-implanting Si, F, and Ge, then implanting B or BF ₂ , and then annealing in the process of forming the source / drain of the pMOS transistor. .