JPH06151348A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To easily optimize an implantation condition and to easily obtain a shallow junction which is excellent in an electric characteristic. CONSTITUTION:Si<+> is implanted into a substrate 1, and an amorphous layer 2 is formed down to a depth of about 0.15mum from the surface of the substrate 1. Then, after B<+> (boron) as impurities has been implanted, Si<+> is then implanted. Then, the amorphous layer 2 is formed continuously down to a depth of about 0.3mum from the surface. When a heat treatment is executed at this time, the amorphous layer 2 is crystallized and a p-type region 3 is formed down to a depth of about 0.15mum from the surface. Consequently, the depth of a p-n junction in the n-type substrate 1 and the p-type region 3 becomes 0.15mum from the surface. A secondary defect 4 caused by an annealing operation is at a position of 0.3mum from the surface, and the secondary defect 4 appears only in a sufficiently deep position twice as deep as the junction depth.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an impurity is introduced into a semiconductor to activate it.

[0002]

2. Description of the Related Art Ion implantation is widely used as a technique for introducing impurities into semiconductors, for example, in the manufacture of LSI and MOS devices. Ion implantation is a technique of ionizing a target impurity element, further accelerating it to an energy of 10 to several 100 keV, and implanting it into a semiconductor substrate.
The impurity concentration can be precisely controlled over a wide range from 0.1 ppm to 10%, and unlike the thermal diffusion method, by utilizing a physical process that does not go through a thermal equilibrium state, various advantages can be obtained. is doing.

By the way, when ions are injected into a semiconductor crystal, a so-called channel surrounded by the crystal atoms is formed. Therefore, when the ions enter parallel to the channel axis, they do not collide with the crystal atoms. A channeling phenomenon of deeply entering occurs. In order to suppress the channeling at the time of implanting such ions, that is, impurity atoms, in the past, a pre-amorphization was performed by implanting Si.

[0004]

However, the amorphization for suppressing the channeling at the time of implanting impurity atoms is performed by using an As (arsenic) ion implant (IMPLA).
(NT) state, that is, the state immediately after As ion implantation, is effective, but during the subsequent heat treatment for activation, problems such as the generation of secondary defects due to recrystallization of the amorphous layer occur, and the electrical characteristics There was a problem that it had an adverse effect.

For example, in the case of pre-amorphization by Si implantation, when heat treatment is applied, high density secondary defects are generated at the amorphous / crystalline interface at the time of implantation, and when this defect layer is generated near the junction, junction leakage current is generated. It will increase. As a preventive measure, Si implantation is performed with high energy (150 k
A method of making the defect layer sufficiently deeper than the junction interface is conceivable. However, in this case, channeling occurs because the vicinity of the surface of the semiconductor layer is not amorphized, and recrystallization proceeds from both the substrate side and the surface side, and a new defect layer is induced at the bonding interface. I will end up.

In order to solve this, it is necessary to control the distribution of the amorphous layer of the semiconductor in consideration of recrystallization during activation. As a means therefor, a method of performing preamorphization by implanting Si before implanting impurity atoms (B (boron)) is divided into two steps: implantation with high energy and implantation with low energy. There is.
That is, by injection with high energy, amorphous /
It is intended to form a crystal interface in a sufficiently deep region and to make the surface amorphous by injection with low energy to prevent channeling and recrystallization near the surface.

However, this method has a drawback that the setting of the implantation conditions and the like becomes complicated because the amorphization by the two implantations of Si directly affects the implantation profile of the impurities. Although this method is effective for preamorphization, it is extremely difficult to control recrystallization of the amorphous layer formed by the action of the implanted impurities themselves, as in the case of As implantation. However, there was a drawback that its application range was limited.

The present invention solves the above-mentioned conventional problems, facilitates optimization of implantation conditions, and manufactures a semiconductor device capable of easily obtaining a shallow junction having excellent electric characteristics. It is intended to provide a way.

[0009]

In order to achieve the above-mentioned object, according to the present invention, ion implantation is carried out for the purpose of changing an amorphous layer region of a semiconductor layer after implantation of impurity atoms, and then heat treatment is carried out. It is characterized by that.

That is, in the first manufacturing example of the present invention, when implanting and activating impurity ions into the semiconductor layer, Si or Ge ions are implanted at least once after the implantation of the impurity ions (applied dose). (The amount range is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² in the case of Si, and 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² in the case of Ge), and the semiconductor layer is amorphous. The heat treatment is applied after the material has been turned into. According to the first manufacturing example, the problem caused by the amorphization of the semiconductor layer that occurs when ions with a large mass such as BF ₂ and As are implanted are solved, and the implantation conditions are easily optimized. be able to.

Further, in the second manufacturing example of the present invention, when impurity ions are implanted into the semiconductor layer to be activated, Si or Ge ion implantation is performed at least once before and after the impurity ion implantation. (Si or G
The applicable dose range of e is the same as in the case of the first manufacturing example),
Heat treatment is applied after the semiconductor layer is made amorphous. According to the second manufacturing example, the problem caused by the preamorphization can be solved and the implantation condition can be easily optimized.

The above-described processing method can be applied to the formation of the source / drain of a semiconductor device, for example, a MOS transistor. When this is applied to form the source / drain, a shallow junction having excellent electrical characteristics is formed. It becomes possible to do.

Further, the above-mentioned processing method can be applied to form a channel region of, for example, a MOS device. In this case, a channel region having excellent electric characteristics can be formed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1A to 1D are views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. Note that FIG.
In the example of the manufacturing process of 1), the case where the present invention is applied in combination with the preamorphization by Si implantation is shown.
First, as shown in FIG. 1A, the concentration is 1 × 10 ¹⁷ cm ^−3.
Injecting Si ⁺ into the n-type semiconductor substrate 1 of 70 k
Implant with eV and a dose of 1 × 10 ¹⁵ cm ^-2 . As a result, the amorphous layer 2 is formed to a depth of about 0.15 μm from the surface of the semiconductor substrate 1. Then, FIG. 1 (b)
As shown in FIG. 1B, B ⁺ (boron) as a p-type impurity has an energy of 10 keV and a dose of 5 in the layer 2 of FIG.
Inject at × 10 ¹⁴ cm ^-2 . Then, as shown in FIG. 1C, Si ⁺ implantation energy is 150 keV, 1 ×
When implanted at 10 ¹⁵ cm ^-2 , the amorphous layer 2 is continuously formed to a depth of about 0.3 μm from the surface. Here, when a heat treatment of lamp annealing (in a nitrogen atmosphere) is performed at a temperature of 1000 ° C. for 10 seconds, the amorphous layer 2 is crystallized and 0.15 from the surface as shown in FIG.
The p-type region 3 extends to a depth of about μm. Therefore, the depth of the pn junction between the n-type substrate 1 and the p-type region 3 is 0.15 μm from the surface. Further, the secondary defect 4 generated by annealing is located at a position of 0.3 μm from the surface, and the secondary defect 4
Appears only at a sufficiently deep position that is twice as deep as the junction depth. Therefore, the junction leakage current due to the secondary defect can be significantly reduced, and a shallow junction with no junction leakage current can be realized.

For comparison with the above manufacturing process, FIG.
As shown in FIGS. 1A to 1C, the semiconductor device was manufactured by omitting the step of FIG. That is, FIG.
As shown in (a) and (b), B ⁺ (boron) was implanted into the amorphous layer 2 under the same conditions and steps as in FIGS. Heat treatment of lamp annealing (in a nitrogen atmosphere) was performed at a temperature of 10 seconds. As a result, as shown in FIG.
The p-type region 3 is formed up to a depth of 15 μm, and the depth of the pn junction is 0.15 μm from the surface, while the secondary defect 4 also occurs at a position near 0.15 μm from the surface. As described above, when the step shown in FIG. 1C is omitted, the junction interface and the secondary defect position overlap with each other in the vicinity of 0.15 μm from the surface, and thus the secondary defect causes the junction leakage current to be rapidly increased. It will increase. Therefore, the process shown in FIG.
That is, it is understood that the Si ion implantation step after implanting the impurity atoms (B ⁺ ) is very important.

Although Si ions are implanted in the above-mentioned embodiment, the same effect can be obtained by using Ge instead of Si. In addition, as described above, the junction leakage current is often a problem, for example, in the pn junction between the source / drain of the MOS device and the substrate and in the channel region. Therefore, by applying the steps of FIGS. 1A to 1D to the formation of the source / drain or the channel region, the problem of the junction leak current in these regions can be avoided. Especially the source
When applied to the formation of a drain, a shallow pn junction having excellent electric characteristics can be formed. When applied to the formation of the channel region, the channel region having excellent electric characteristics can be formed.

[0017]

As described above, according to the first and third aspects of the present invention, when impurity ions are implanted into a semiconductor layer for activation, Si is not implanted after the impurity ions are implanted.
Alternatively, since Ge is ion-implanted at least once to amorphize the semiconductor layer and then heat treatment is applied, it is caused by the amorphization of the semiconductor layer that occurs when ions with a large mass such as BF ₂ and As are implanted. It is possible to solve the above problem and easily optimize the implantation conditions.

According to the second and third aspects of the invention, when implanting and activating the impurity ions into the semiconductor layer, at least Si or Ge ion implantation is performed before and after the impurity ion implantation. Since the heat treatment is performed once after the semiconductor layer is made amorphous, the problem caused by the preamorphization can be solved and the implantation conditions can be easily optimized.

Further, according to the invention of claim 4, since the source / drain of the MOS device is formed by using the method of claim 2, a shallow junction having excellent electric characteristics can be formed. You can

According to the fifth aspect of the invention, since the channel region of the MOS device is formed by using the method of the second aspect, it is possible to form the channel region having excellent electric characteristics. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a manufacturing process of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing an example of a manufacturing process for comparison with the example of a manufacturing process of the semiconductor device shown in FIG.

[Explanation of symbols]

 1 n-type semiconductor substrate 2 amorphous layer 3 p-type region 4 secondary defect

Claims (5)

[Claims] 1. When implanting and activating impurity ions into a semiconductor layer, Si or G is implanted after the impurity ions are implanted.
A method for manufacturing a semiconductor device, which comprises performing ion implantation of e at least once to amorphize the semiconductor layer, and then performing heat treatment. 2. When implanting and activating impurity ions into a semiconductor layer, before and after implanting impurity ions, S
A method of manufacturing a semiconductor device, which comprises performing ion implantation of i or Ge at least once to amorphize the semiconductor layer, and then performing heat treatment. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the applicable dose range of the ion implantation is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm in the case of Si.
^-2 , and in the case of Ge, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ c
A method of manufacturing a semiconductor device, wherein the semiconductor device is m ⁻² . 4. A method of manufacturing a semiconductor device, comprising forming a source / drain of a MOS device by using the method according to claim 2. 5. A method of manufacturing a semiconductor device, comprising forming a channel region of a MOS device by using the method according to claim 2.