JPH06232352A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, which realizes an addition of a capacitor to the device, such as a BiCMOSLSI, without increasing significantly the number of processes in the case where the capacitor is added. CONSTITUTION:An insulating film is formed on a semiconductor substrate 10, first conductive film 21 and 22 are formed, the laminated structures of the insulating film and the films 21 and 22 are processed, a dielectric film 3 is formed, second conductive films 41 and 42 are formed, the laminated structures of the insulating film and the first and second conductive films are processed, an insulating film is further formed according to the need and this insulating film is opened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device which enables provision of a semiconductor device including a highly accurate capacitor. The semiconductor device of the present invention relates to various semiconductor devices such as a MOS transistor, a bipolar transistor, and a semiconductor device having a bipolar transistor and a MOS transistor (hereinafter, such a transistor may be appropriately referred to as “BiCMOS transistor”). Can be used.

[0002]

2. Description of the Related Art In recent years, further large scale and high performance of LSI have been required, among which high integration of CMOS, low power consumption and BIP (bipolar transistor).
Has attracted attention because of its high speed. Particularly in fields requiring high performance, it is necessary to integrate the most advanced MOS technology and BIP technology, so-called LDD structure is adopted as the MOS structure, and so-called double polysilicon is used as the BIP structure. Structures have come to be adopted.

A conventional BiCMOS LSI manufacturing process will be described in detail with reference to FIGS. This figure is a cross-sectional top view of a silicon substrate of a bipolar transistor portion Tr1 and a P-channel MOS transistor portion Tr2 (see FIG. 8) having a double polysilicon structure.

Referring to FIG. On the substrate 1, the N ⁺ buried layer 7 and the diffusion layer are formed in the bipolar transistor portion Tr1 forming portion. The buried layer 7 and the diffusion layer are NP
It functions as a collector takeout for the N-transistor.

Next, a LOCOS oxide film 17 for element isolation is formed.
After the P ⁺ diffusion layer 13 is formed, the insulating film 1 is formed, and this insulating film 1 is used as the gate oxide film of the MOS transistor. LOCOS oxide film 17 is 400-500 nm
As the gate oxide insulating film, a film thickness of 10 to 20 nm is formed.

After that, 100 to 20 are formed on the entire surface by CVD.
After depositing Poly Si having a film thickness of about 0 nm to form the conductive film 2, the Poly Si / gate oxide laminated film in the base and emitter forming portions of the bipolar transistor portion is opened by the existing dry etching technique. .

As described above, the Poly Si film (conductive film 2)
Functions as a protective film for the gate oxide film when the opening is formed. Therefore, it is possible to prevent the gate oxide film from being contaminated and causing a breakdown voltage failure or the like in the resist stripping step when opening the gate oxide film.

Next, referring to FIG. 100 by CVD
Poly Si having a film thickness of up to 200 nm is formed as the second conductive film 4. Together with the Poly Si CVD film (second conductive film 2), the total Poly Si film thickness is 300 to 400 nm.

N is added to the gate electrode portion of the MOS transistor portion.
⁺ Ion implantation is carried out, after the P ⁺ ion implantation to the base electrode forming portion of the bipolar transistor portion, the gate electrode of the MOS transistor portion, leaving the base electrodes of the bipolar transistor part, the stacking in the existing dry etching technique Poly Si (first and second conductive films 2 and 4)
To process. Next, P ⁻ ions are implanted into the MOS transistor portion to form the LDD diffusion layer 14.

After that, 200 to 400 nm is formed by CVD.
SiO ₂ having a film thickness of ₂ is formed and anisotropically etched by the existing dry etching technique to form sidewall-shaped SiO ₂ spacers 16 for LDD.

At this time, since the base and emitter forming regions of the bipolar transistor are covered with PolySi, it becomes possible to protect these regions when forming the LDD SiO ₂ spacer by anisotropic etching. , Not exposed to over-etching. Therefore, problems such as deterioration of the device and reduction of the yield due to RIE damage do not occur. Next, P ⁺ ions are implanted into the MOS transistor portion to form the source / drain diffusion layer 15.

Next, referring to FIG. 300 by CVD
After forming the SiO ₂ film thickness of to 400 nm, the base of the bipolar transistor, SiO ₂ of the emitter formation region
The / Poly Si laminated film is removed by etching using the existing dry etching technique.

Then, by CVD, 400 to 600 nm
SiO ₂ having a thickness of ₂ is formed and anisotropically etched by the existing dry etching technique to form the SiO ₂ spacer 18 for separating the emitter and the base electrode. next,
Poly Si6 for emitter formation is formed by CVD and processed by the existing dry etching technique. The P
A base and an emitter are formed by ion implantation and diffusion into oli Si.

By the heat treatment at this time, P ⁺ is simultaneously diffused from the base extraction electrode to form a graft base, and at the same time, the source and drain diffusion layers of the MOS transistor portion are activated.

Next, referring to FIG. 300 by CVD
SiO ₂ having a film thickness of up to 400 nm is formed as the insulating film 5. After that, each electrode is formed using an existing wiring technique (not shown). In FIG. 8, Base, Em, and Col indicate electrode extraction portions of the base, emitter, and collector of the bipolar transistor portion Tr1, and S and D indicate electrode extraction portions of the source and drain of the MOS transistor portion Tr2.

On the other hand, in recent years, Acti has attracted attention as a technique for achieving high speed and low power consumption of a bipolar ECL gate.
From the viewpoint of application to a ve Pull-down circuit or the like,
There is a demand to add a highly accurate capacitance to the conventional BiCMOS LSI. In this case, an MI using SiN as a dielectric is used because of the large capacitance value per unit area and good controllability.
S capacitors are promising.

A conventional example of a process in which a highly accurate capacitor is added to a BiCMOS LSI will be described with reference to FIGS. 9 to 11 are cross-sectional top views of the silicon substrate of the MIS capacitor portion T1 and the P-channel MOS transistor portion T2.

Referring to FIG. This figure corresponds to FIGS. 5 to 7 described above. In this example, the MIS capacitor T
The N ⁺ diffusion layer 7 is formed in the first formation portion.

Referring to FIG. The insulating film 1 (SiO ₂ ) in the MIS capacitor T1 formation portion is removed by etching using the existing dry etching technique. Then, 30 by CVD
SiN having a film thickness of -60 nm is formed and processed by the existing dry etching technique to leave SiN as the dielectric film 4 in the MIS capacitor T1 formation portion.

Referring to FIG. 300 ~ by CVD
An insulating film 5 is formed by forming SiO ₂ having a film thickness of 400 nm. After that, each electrode is formed using an existing wiring technique (not shown).

However, the above method has the following problems. In order to form the MIS capacitor, it is necessary to add a new step of removing the insulating film in the MIS capacitor forming region by etching (FIG. 10). In the electrode forming step, it is necessary to separately form the contact on SiN forming the MIS capacitor from other contacts (FIG. 11). This is because S, which has a high selectivity with SiN in the existing dry etching technology.
This is because, since there is no iO ₂ etching condition, it is necessary to use HF-based solution etching for the contact opening on the MIS SiN, which is not suitable for fine processing.

[0022]

SUMMARY OF THE INVENTION According to the present invention, when a capacitor is added to a semiconductor device, for example, high performance Bi is used.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that realizes a high-performance capacitor without adding a large number of steps when a high-performance capacitor is added to the CMOSLSI, and realizes a high-performance, low-cost semiconductor device such as BiCMOSLSI. It is a thing.

[0023]

According to a first aspect of the present invention, there is provided a step of forming an insulating film on a semiconductor substrate, a step of forming a first conductive film, the insulating film and the first conductive film. A step of processing a laminated structure of films, a step of forming a dielectric film,
A step of forming a second conductive film, the insulating film and the first and second insulating films.
A method of manufacturing a semiconductor device, including the step of processing a laminated structure of a second conductive film, by which the above object is achieved.

According to a second aspect of the present invention, the step of forming an insulating film on a semiconductor substrate, the step of forming a first conductive film, and the processing of the laminated structure of the insulating film and the first conductive film are performed. A step of forming a dielectric film, a step of forming a second conductive film, a step of processing the laminated structure of the insulating film and the first and second conductive films, and a step of forming an insulating film. And a step of forming a wiring connection hole by opening the insulating film, which achieves the above object.

According to a third aspect of the present invention, the semiconductor device is a semiconductor device having a MOS transistor,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed at the same time as the gate insulating film of the MOS transistor, and thereby the above object is achieved.

According to a fourth aspect of the present invention, the semiconductor device is a semiconductor device having a MOS transistor,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is formed at the same time as the gate electrode of the MOS transistor, and thereby the above object is achieved.

According to a fifth aspect of the present invention, the semiconductor device is a semiconductor device having a MOS transistor,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is Poly Si or a laminated film containing Poly Si. .

A sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the semiconductor device is a semiconductor device including a bipolar transistor and a MOS transistor. Therefore, this achieves the above object.

Using this embodiment, for example, BiCMOS
When adding a high-precision capacitor to an LSI, this can be achieved without a significant additional correction of the process.

In the invention of the present application, the capacitor formation region can be embodied so as to be formed simultaneously with the formation of the active region of the bipolar transistor.

Further, by embodying the lead-out electrode of the capacitor so as to also serve as the conductive film of Poly Si or the like for forming the gate electrode, the above structure can be formed without adding steps.

[0032]

According to the method of the present invention, when a high-precision capacitor such as a BiCMOS LSI is added, this can be realized without a significant additional correction of the process. This will minimize the cost increase due to the addition of processes
A high-performance semiconductor device can be realized.

[0033]

EXAMPLES Specific examples of the present invention will be described below.
However, it should be understood that the present invention is not limited to the embodiments.

Example 1 Please refer to FIG. 1 to FIG. These figures are cross-sectional top views of the silicon substrate of the MIS capacitor T1 and the P-channel MOS transistor T2. The structure of the bipolar transistor forming portion is the same as that of the conventional example described with reference to FIGS.

In the manufacturing process of the BiCMOS transistor of this embodiment, an insulating film (for forming the insulating films 11 and 12) is formed on the semiconductor substrate 10, and a first conductive film (for forming the conductive films 21 and 22). Of the insulating film and the first conductive film (FIG. 1), the step of forming the dielectric film 3 (FIG. 2), and the second conductive film (conductive film 41). , 42 for forming), and a step of processing the laminated structure of the insulating film and the first and second conductive films (FIG. 3).
Furthermore, this embodiment includes a step of forming the insulating film 5 and a step of forming a wiring connection hole by opening the insulating film (FIG. 4).

More specifically, the following steps are performed in this embodiment. First, referring to FIG. The N ⁺ buried layer 7 and the diffusion layer are formed in the bipolar transistor portion.
The embedding layer 7 and the diffusion layer function as a collector extraction of the PNPTr (not shown).

Next, a LOCOS oxide film 17 for element isolation is formed.
After the P ⁺ diffusion layer 13 is formed, an insulating film is formed and patterned to form the gate oxide film 12. LOC
The OS oxide film 17 has a thickness of 400 to 500 nm, and the gate oxide film 12 has a thickness of 10 to 20 nm.

After that, 100 to 20 are formed on the entire surface by CVD.
After forming Poly Si with a film thickness of about 0 nm to form a conductive film (for forming the first conductive films 21 and 22), Poly of the capacitor forming region and the base of the bipolar transistor part and the emitter forming part (not shown) are formed. The Si / gate oxide film forming insulating film laminated film is opened by the existing dry etching technique.

At this time, the Poly Si film functions as a protective film for the gate oxide film when the opening is formed. Therefore, in the resist stripping process when opening the gate oxide film, it is possible to prevent the breakdown voltage from being generated due to the contamination of the gate oxide film.

Next, referring to FIG. 30 ~ by CVD
By forming SiN with a film thickness of 60 nm and processing it by the existing dry etching technique, SiN is left in the MIS capacitor forming portion to form the dielectric film 3.

Next, referring to FIG. 100 by CVD
Poly Si having a film thickness of up to 200 nm is formed to be a second conductive film. The total Poly Si film thickness is 300 to 400 nm in combination with the above Poly Si CVD.

After implanting N ⁺ ions into the portion corresponding to the gate electrode portion of the MOS transistor portion and P ⁺ ions into the portion forming the base electrode portion of the bipolar transistor forming portion, the capacitor extraction electrode, the gate electrode portion of the MOS transistor portion, and the bipolar portion. The base electrode (not shown) of the transistor part is left and the above-mentioned Po is formed by the remaining dry etching technique.
Process ly Si. Next, add P to the MOS transistor
^- by ion implantation to form an LDD diffusion layer 14.

Then, by CVD, 200 to 400 nm
SiO ₂ of LDD thickness is formed and anisotropically etched by the existing dry etching technique.
₂ Form the spacer 16.

At this time, since the base and emitter forming regions of the bipolar transistor are covered with PolySi, they are not exposed to over-etching when the LDD SiO ₂ spacer is formed by anisotropic etching ( (Not shown).

Next, P ⁺ ions are implanted into the MOS transistor portion to form the source / drain diffusion layer 15.

Referring to FIG. 300-4 by CVD
After forming SiO ₂ with a film thickness of 00 nm, the base and emitter forming regions of the bipolar transistor are formed with SiO ₂ / P.
The oli Si laminated film is removed by etching using the existing dry etching technique.

Then, by CVD, 400 to 600 nm
SiO ₂ having a film thickness of ₂ is formed and anisotropically etched by the existing dry etching technique to form the SiO ₂ spacer 18 for separating the emitter and base electrodes.

Next, a Pol for forming an emitter is formed by CVD.
y Si is formed and processed by the existing dry etching technique. A base and an emitter are formed by ion implantation and diffusion into the Poly Si.

By the heat treatment at this time, at the same time, P ⁺ is diffused from the base extraction electrode to form a graftate, and at the same time, the source and drain diffusion layers of the MOS transistor portion are activated. The steps for forming elements up to this point are basically the same as the steps described in the step of the related art.

After forming SiO ₂ with a film thickness of 300 to 400 nm by CVD to form the insulating film 5, each electrode is formed using the existing wiring technique (not shown).

At this time, unlike the conventional case, the capacitor electrode portion is covered with Poly Si that is a conductive film, so that SiN is not etched during anisotropic etching when forming the electrode window, and the capacitor electrode portion and other electrodes are not etched. Simultaneous formation is possible.

As described above, according to the present embodiment, when adding a high-precision capacitor to the BiCMOSLSI, the capacitor formation region is formed at the same time when the active region of the bipolar transistor is formed. The lead-out electrode of the capacitor is set to P for forming the gate electrode.
By also serving as a conductive film such as poly Si and covering the capacitor insulating film with the above-mentioned Poly Si or the like, it is possible to prevent the capacitor insulating film from being etched at the time of anisotropic etching at the time of forming an electrode window, and to prevent the other electrodes from being etched. It becomes possible to provide a means for adding the above-mentioned capacitor without significantly modifying the process by allowing the simultaneous formation of the above.

[0053]

According to the present invention, a high performance BiCMOS is provided.
When adding a capacitor to a semiconductor device, such as when adding a high-performance capacitor to an LSI, it is possible to provide a method for manufacturing a semiconductor device that realizes this without a significant increase in the number of steps. BiCMO
It is possible to realize a semiconductor device such as an SLSI.

[Brief description of drawings]

1A to 1C are sectional views showing steps of Example 1 in order (1).

2A to 2C are sectional views showing the steps of Example 1 in order (2).

FIG. 3 is a sectional view showing the steps of Example 1 in order (3).

FIG. 4 is a sectional view showing the steps of Example 1 in order (4).

FIG. 5 is a sectional view sequentially showing steps of the prior art (1) (1).

FIG. 6 is a sectional view sequentially showing the steps of the prior art (1) (2).

FIG. 7 is a sectional view sequentially showing the steps of the prior art (1) (3).

FIG. 8 is a sectional view sequentially showing the steps of the prior art (1) (4).

FIG. 9 is a sectional view sequentially showing the steps of the prior art (2) (1).

FIG. 10 is a sectional view sequentially showing the steps of the prior art (2) (2).

FIG. 11 is a sectional view sequentially showing the step of the prior art (2) (3).

[Explanation of symbols]

 11 insulating film 12 gate insulating film 21,22 first conductive film 3 dielectric film 41,42 second conductive film 5 insulating film

Claims (6)

[Claims] 1. A step of forming an insulating film on a semiconductor substrate, a step of forming a first conductive film, a step of processing a laminated structure of the insulating film and the first conductive film, and forming a dielectric film. And a step of forming a second conductive film, and a step of processing the laminated structure of the insulating film and the first and second conductive films. 2. A step of forming an insulating film on a semiconductor substrate, a step of forming a first conductive film, a step of processing a laminated structure of the insulating film and the first conductive film, and forming a dielectric film. A step of forming a second conductive film, a step of processing the laminated structure of the insulating film and the first and second conductive films, a step of forming an insulating film, and opening of the insulating film A method of manufacturing a semiconductor device, the method including the step of forming a wiring connection hole thereby. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a MOS transistor, and the insulating film is formed simultaneously with a gate insulating film of the MOS transistor. Production method. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a MOS transistor, and the conductive film is formed simultaneously with a gate electrode of the MOS transistor. Device manufacturing method. 5. The semiconductor device is a semiconductor device having a MOS transistor, and the conductive film is made of Poly Si.
Alternatively, the method of manufacturing a semiconductor device according to claim 1, wherein the laminated film includes Poly Si. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device including a bipolar transistor and a MOS transistor.