JPH06140484A - Probe card - Google Patents
Probe cardInfo
- Publication number
- JPH06140484A JPH06140484A JP4289947A JP28994792A JPH06140484A JP H06140484 A JPH06140484 A JP H06140484A JP 4289947 A JP4289947 A JP 4289947A JP 28994792 A JP28994792 A JP 28994792A JP H06140484 A JPH06140484 A JP H06140484A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- pga
- input
- layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、入出力端子がアレイ状
に配置されているパッケージに実装された形態のICの
検査用治具であるプローブカードに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe card which is an IC inspection jig mounted on a package in which input / output terminals are arranged in an array.
【0002】[0002]
【従来の技術】入出力端子がアレイ状に配置されている
パッケージに実装された形態のICの概略を図3,図4
を用いて説明する。図3(a)はピンをアレイ状に配置
された入出力端子11を有するピングリッドアレイ(P
GA)パッケージに実装されたIC12であり、図3
(b)は図3(a)を上下反転して示したものである。
図4はピンの替わりに、パッドを入出力端子31に用い
たパッドグリッドアレイ(PGA)パッケージに実装さ
れたIC32の形状を示す。図4(b)は図4(a)を
上下反転して示したものである。構造は図3のピンを入
出力端子11とするピングリッドアレイ(PGA)パッ
ケージに実装されたIC(以下ではPGA−ICと呼
称)12と同様であるので、以下の説明はピンを用いた
(図3)タイプで代表する。2. Description of the Related Art An outline of an IC mounted in a package in which input / output terminals are arranged in an array is shown in FIGS.
Will be explained. FIG. 3A shows a pin grid array (P) having input / output terminals 11 in which pins are arranged in an array.
GA) IC12 mounted in a package, as shown in FIG.
FIG. 3B is an upside-down view of FIG.
FIG. 4 shows the shape of the IC 32 mounted in a pad grid array (PGA) package using pads as input / output terminals 31 instead of pins. FIG. 4B is an upside-down view of FIG. 4A. Since the structure is the same as that of the IC (hereinafter referred to as PGA-IC) 12 mounted in a pin grid array (PGA) package having the pins as the input / output terminals 11 of FIG. 3, the pins will be used in the following description. Figure 3) is represented by the type.
【0003】従来のPGA−ICの電気特性検査法を図
5を用いて説明する。図5の様なプリント配線板13を
用いたプローブカードの接続用パッド22にPGA−I
C12をバンプ等を用いてプリント配線板13に搭載
し、検査用パッド15とプローブコネクタとを電気的に
接触させ、直流電源、パルス発生器、パルス波形観測装
置等を接続して、電気特性検査を行っている。クロック
が数10MHzを越える高周波領域でのPGA−IC1
2の検査では、配線の展開部の信号線14の特性インピ
ーダンスを整合させ信号の反射歪みを抑える必要があ
る。また、終端用チップ抵抗16、ノイズ低減用のバイ
パスコンデンサ17をプリント配線板上に搭載する必要
がある。A conventional PGA-IC electrical characteristic inspection method will be described with reference to FIG. The PGA-I is attached to the connection pad 22 of the probe card using the printed wiring board 13 as shown in FIG.
The C12 is mounted on the printed wiring board 13 using bumps or the like, the inspection pad 15 and the probe connector are electrically contacted, and a DC power supply, a pulse generator, a pulse waveform observation device, etc. are connected, and an electrical characteristic inspection is performed. It is carried out. PGA-IC1 in the high frequency range where the clock exceeds several tens MHz
In the inspection of No. 2, it is necessary to match the characteristic impedance of the signal line 14 in the expanded portion of the wiring to suppress the reflection distortion of the signal. Further, it is necessary to mount the terminating chip resistor 16 and the noise reducing bypass capacitor 17 on the printed wiring board.
【0004】実際のPGA−IC12を検査する場合の
例として、364端子のPGA−IC12の概要を図6
(a)に示す。また、図6(b)はこのPGA−IC1
2の端子をプリント配線板13に引き出し線43を形成
して展開する場合の状態を示す。プリント配線板13で
は、図6(b)に示すように1.27mm千鳥配列のス
ルーホールでピン間1本の配列がほぼ限界である。した
がって、PGA−IC12の端子ピッチを1mm以下に
さらに小さくすることは困難であり、PGA−IC12
を小形化できない。また、図6(a)に示す364端子
のPGA−IC12を検査するには、仮に図6(b)の
ように信号端子41をグランド(GND)端子42で囲
う構造とすると、信号の展開に3層必要である。特性イ
ンピーダンスを制御するためストリップライン構造にす
ると、GND層も含め7層以上必要となり、さらに信号
端子数が増大するとピッチを拡げるか、層数を増やす必
要があり、実用的でない。具体的には、引き出し線間の
ピッチに現在のプリント配線板製造技術の限界を適用
し、多層化すれば引き出し信号線の展開は可能と考えら
れるが、必要な端子数を搭載するには展開面積が極めて
大きくなり実用的でない。FIG. 6 shows an outline of the PGA-IC12 having 364 terminals as an example of the case of inspecting the actual PGA-IC12.
It shows in (a). In addition, FIG. 6B shows the PGA-IC1.
2 shows a state in which a lead wire 43 is formed on the printed wiring board 13 to develop the second terminal. In the printed wiring board 13, as shown in FIG. 6B, the arrangement of one pin between the through holes in the zigzag arrangement of 1.27 mm is almost the limit. Therefore, it is difficult to further reduce the terminal pitch of the PGA-IC12 to 1 mm or less.
Cannot be miniaturized. Further, in order to inspect the PGA-IC 12 having 364 terminals shown in FIG. 6A, if the signal terminal 41 is surrounded by the ground (GND) terminal 42 as shown in FIG. Requires 3 layers. If a stripline structure is used to control the characteristic impedance, seven or more layers including the GND layer are required. If the number of signal terminals increases, the pitch must be expanded or the number of layers must be increased, which is not practical. Specifically, it is considered possible to develop the lead-out signal lines by applying the limits of the current printed wiring board manufacturing technology to the pitch between the lead-out lines, and using multiple layers, but it is necessary to install the necessary number of terminals. The area is so large that it is not practical.
【0005】また、プリント配線板13では微細加工が
できないため層間の厚さを薄く、また均一にできないこ
とから、その特性インピーダンスを高精度に制御できな
い欠点がある。In addition, since the printed wiring board 13 cannot be finely processed, the thickness between layers cannot be made thin and uniform, so that the characteristic impedance cannot be controlled with high precision.
【0006】加えて不都合なことに、終端用チップ抵抗
16、バイパスコンデンサ17はプリント配線板の表
面、または裏面にはんだ付けされており、それぞれ寸法
が数mm角と大きい。このため、寸法が数mm角と大き
いのでPGA−IC12の直近に置けないためPGA−
ICとチップ部品16,17とを接続する配線が必要と
なるだけでなく、ボンディングパッド18、ボンディン
グワイヤ19等が必要であり、不要なインダクタンス、
容量が付加されることになり、高周波特性の劣化をもた
らす。したがって、プリント配線板13の引き出し線1
4および43は、高速信号伝搬に影響を与える電気特性
の高精度な制御ができないため、検査に数Gb/s程度
までのパルス波形観測が可能な同軸プローブを使用した
としても、引き出し線14の伝搬時にパルス波形が大き
く歪み、直流または、高々100Mb/s程度までのパ
ルス波形観測しかできない。In addition, disadvantageously, the terminating chip resistor 16 and the bypass capacitor 17 are soldered to the front surface or the back surface of the printed wiring board, and their dimensions are as large as several mm square. For this reason, since the size is as large as several mm square, it cannot be placed in the immediate vicinity of the PGA-IC 12, so PGA-
Not only wiring for connecting the IC and the chip components 16 and 17 is required, but also a bonding pad 18, a bonding wire 19 and the like are required, and unnecessary inductance,
Capacitance is added, resulting in deterioration of high frequency characteristics. Therefore, the lead wire 1 of the printed wiring board 13
In Nos. 4 and 43, the electrical characteristics that affect high-speed signal propagation cannot be controlled with high precision, so even if a coaxial probe capable of observing a pulse waveform up to several Gb / s is used for inspection, The pulse waveform is greatly distorted during propagation, and only DC or pulse waveforms up to about 100 Mb / s can be observed.
【0007】[0007]
【発明が解決しようとする課題】上述したように、従来
技術においては検査治具のパッドピッチを小さくできな
いため、展開スペースを確保するためにPGA−ICパ
ッケージを小形化できない問題があった。また、比較的
端子数の少ないPGA−ICを検査する場合にも、10
0Mb/s以上の高周波領域の検査が困難であった。As described above, the conventional technique has a problem that the pad pitch of the inspection jig cannot be made small, so that the PGA-IC package cannot be made small in order to secure a space for development. Also, when inspecting a PGA-IC with a relatively small number of terminals, 10
It was difficult to inspect a high frequency region of 0 Mb / s or more.
【0008】本発明の目的は、従来技術での上記した問
題を解決し、PGA−ICの高速・高周波領域の検査を
可能とする検査用治具を提供することにある。An object of the present invention is to solve the above-mentioned problems in the prior art and to provide an inspection jig capable of inspecting a PGA-IC in a high speed / high frequency region.
【0009】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明においては、入出力端子がアレイ状に配置さ
れているパッケージに実装された形態のICの検査用治
具であるプローブカードにおいて、セラミック基板と、
この基板上に形成された配線層とを具え、上記配線層
は、樹脂絶縁膜と、この膜内に形成されたグランド層
と、特性インピーダンスがグランド層までの樹脂絶縁膜
厚により制御されて形成された引き出し信号線とで構成
され、上記配線層の表面に形成されて被検査ICの入出
力端子と接続する接続用パッドと、配線層またはセラミ
ック基板の表面に形成されて検査用信号の入出力端子と
なるプローブパッドとが上記引き出し信号線により電気
的に接続され、終端用の薄膜抵抗およびノイズ低減用の
薄膜バイパスコンデンサが、上記配線層またはセラミッ
ク基板の表面に形成されている、構成とする。In order to achieve the above object, in the present invention, a probe card which is an IC inspection jig mounted in a package in which input / output terminals are arranged in an array. In, a ceramic substrate,
A wiring layer formed on the substrate, wherein the wiring layer is formed by a resin insulation film, a ground layer formed in the film, and a characteristic impedance controlled by the resin insulation film thickness up to the ground layer. Connection lead pad formed on the surface of the wiring layer and connected to the input / output terminals of the IC to be inspected, and the input of the inspection signal formed on the surface of the wiring layer or the ceramic substrate. A probe pad serving as an output terminal is electrically connected by the lead-out signal line, and a thin film resistor for termination and a thin film bypass capacitor for noise reduction are formed on the surface of the wiring layer or the ceramic substrate. To do.
【0010】[0010]
【作用】本発明は、PGA−ICの検査用治具におい
て、信号等の入出力端子と、両者を電気的に接続する樹
脂絶縁膜を用いたストリップライン構造、あるいはマイ
クロストリップライン構造、あるいはコプレーナ構造、
あるいはこれらの混在した構造の特性インピーダンスを
制御した信号線と、PGA−ICに必要な電圧を供給す
る給電線とから構成され、また、特性インピーダンスと
整合した高周波特性の良い薄膜終端抵抗を内蔵し、さら
に、必要な部位には高周波特性の良い電源ノイズ低減用
の薄膜バイパスコンデンサを内蔵することを特徴とした
プローブカードであり、高密度、多端子PGA−ICの
高速・高周波領域の電気特性検査を容易に行うことが可
能になる。According to the present invention, in a PGA-IC inspection jig, a stripline structure, a microstripline structure, or a coplanar structure, which uses an input / output terminal for signals and the like and a resin insulating film for electrically connecting the two, is used. Construction,
Alternatively, it is composed of a signal line that controls the characteristic impedance of these mixed structures and a power supply line that supplies the voltage required for the PGA-IC, and also has a built-in thin film terminating resistor that matches the characteristic impedance and has good high-frequency characteristics. In addition, the probe card is characterized by having a built-in thin film bypass capacitor for reducing power supply noise with good high-frequency characteristics in the required parts. It is a high-density, multi-terminal PGA-IC high-speed / high-frequency region electrical characteristic test. Can be easily performed.
【0011】[0011]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【0012】図1に本発明によるプローブカードの一実
施例を示す。図1(a)は平面図であり、(b)は断面
図である。ただし、図1(b)においては図示の便宜
上、パッドおよび入出力端子等の位置を図1(a)と変
えてある。プローブカード8はセラミック基板1上に形
成した樹脂絶縁膜2、引き出し信号線3およびグランド
層4から構成されるストリップライン構造の配線層5
と、配線層5の表面に形成された接続用パッド6および
検査用信号等の入出力端子となるプローブパッド7を有
し、接続用パッド6とプローブパッド7とがストリップ
ライン構造の信号線3により電気的に接続されている。
このプローブカード8を用い、PGA−ICの入出力端
子11を接続用パッド6にバンプ等を用いて直接接続
し、プローブパッド7に同軸プローブピンを電気的に接
触させて検査を行う。この時、押さえ治具でPGA−I
Cとプローブカード8とを固定してもよい。FIG. 1 shows an embodiment of the probe card according to the present invention. FIG. 1A is a plan view and FIG. 1B is a sectional view. However, in FIG. 1B, for convenience of illustration, the positions of the pads, the input / output terminals and the like are changed from those in FIG. 1A. The probe card 8 is a wiring layer 5 having a stripline structure including a resin insulating film 2 formed on a ceramic substrate 1, lead-out signal lines 3 and a ground layer 4.
And a connection pad 6 formed on the surface of the wiring layer 5 and a probe pad 7 serving as an input / output terminal for an inspection signal or the like, and the connection pad 6 and the probe pad 7 have a strip line structure. Are electrically connected by.
Using this probe card 8, the input / output terminal 11 of the PGA-IC is directly connected to the connection pad 6 by using a bump or the like, and the coaxial probe pin is electrically contacted with the probe pad 7 for inspection. At this time, press PGA-I
C and the probe card 8 may be fixed.
【0013】本実施例では、配線層5の樹脂絶縁膜とし
て低誘電率なポリイミド樹脂、信号線導体として低抵抗
率な銅を用いている。銅ポリイミド配線、薄膜抵抗、薄
膜コンデンサはフォトリソグラフィにより形成する。例
えば、ポリイミド樹脂絶縁膜を用いた配線層は、信号線
幅25μm、信号線間隙75μm、程度の高密度配線が
形成できるため、高密度多端子PGA−ICの検査が可
能である。また、信号線3の特性インピーダンスを任意
の値に容易に、かつ、高精度に制御することが可能であ
る。図2に信号線の幅を30μm、厚さを5μmとした
時の、ポリイミド樹脂絶縁膜厚(信号線とグランド層間
の間隙)と特性インピーダンスとの関係を示す。従来技
術に比べ樹脂絶縁膜2の膜厚を制御することにより、材
質、引き出し信号線3の幅等に依存することなく所望の
特性インピーダンスが高精度に得られる。さらに、プロ
ーブパッド7も上記配線層5と同様にフォトリソグラフ
ィで形成するため、狭間隔ピッチで高精度に配置するこ
とができる。また、PGA−ICの形状に依存すること
なく任意の大きさにプローブカード8を形成でき、か
つ、プローブカード8のPGA−IC搭載領域を除く全
面にプローブパッド7を配置できる。また、セラミック
基板1上には信号線の特性インピーダンスと整合した薄
膜終端抵抗9が形成されており、信号の反射歪みを低減
する目的で終端抵抗が必要なPGA−ICの端子(ピン
またはパッド)と接続する接続用パッド6と、薄膜終端
抵抗9とを信号線3で接続してある。本発明では薄膜終
端抵抗9も上記配線層5と同様にフォトリソグラフィで
形成するため、薄膜終端抵抗9がセラミック基板上に形
成でき、小形、かつ最短距離で接続用パッド6とグラン
ド層4との間に挿入できることから不要なインダクタン
ス、容量を無視できる程度に小さくでき、高精度に信号
線とインピーダンス整合をとることが可能である。ま
た、数100μm角で50Ω程度の抵抗を形成できるこ
とから高密度に薄膜終端抵抗9を形成できる。高速・高
周波領域の測定を妨害していた信号の反射歪みを低減で
きることから、PGA−IC動作時の信号線のより高精
度な特性インピーダンス制御が可能である。In this embodiment, a polyimide resin having a low dielectric constant is used as the resin insulating film of the wiring layer 5, and copper having a low resistivity is used as the signal line conductor. The copper polyimide wiring, thin film resistor, and thin film capacitor are formed by photolithography. For example, a wiring layer using a polyimide resin insulating film can form a high-density wiring having a signal line width of 25 μm and a signal line gap of 75 μm, so that a high-density multi-terminal PGA-IC can be inspected. Further, the characteristic impedance of the signal line 3 can be easily controlled to an arbitrary value and highly accurately. FIG. 2 shows the relationship between the polyimide resin insulation film thickness (gap between the signal line and the ground layer) and the characteristic impedance when the width of the signal line is 30 μm and the thickness is 5 μm. By controlling the film thickness of the resin insulating film 2 as compared with the conventional technique, a desired characteristic impedance can be obtained with high accuracy without depending on the material, the width of the lead-out signal line 3, and the like. Further, since the probe pads 7 are also formed by photolithography similarly to the wiring layer 5, the probe pads 7 can be arranged with a narrow interval pitch with high accuracy. Further, the probe card 8 can be formed in an arbitrary size without depending on the shape of the PGA-IC, and the probe pad 7 can be arranged on the entire surface of the probe card 8 excluding the PGA-IC mounting region. In addition, a thin film termination resistor 9 matching the characteristic impedance of the signal line is formed on the ceramic substrate 1, and a PGA-IC terminal (pin or pad) that requires a termination resistor for the purpose of reducing signal reflection distortion. The connection pad 6 for connection with the thin film termination resistor 9 is connected with the signal line 3. In the present invention, the thin film terminating resistor 9 is also formed by photolithography similarly to the wiring layer 5, so that the thin film terminating resistor 9 can be formed on the ceramic substrate, and the connecting pad 6 and the ground layer 4 can be formed in a compact and shortest distance. Since it can be inserted between them, unnecessary inductance and capacitance can be reduced to a negligible level, and impedance matching with the signal line can be achieved with high accuracy. Further, since a resistance of about 50Ω can be formed in a square of several 100 μm, the thin film termination resistor 9 can be formed with high density. Since it is possible to reduce the reflection distortion of the signal that interferes with the measurement in the high speed / high frequency region, it is possible to control the characteristic impedance of the signal line with higher accuracy during the PGA-IC operation.
【0014】また、セラミック基板1は電源用配線を有
しており、配線層5に形成されている不図示の給電線を
介してPGA−ICに必要な電圧を供給している。この
給電線には、電源ノイズ低減用の薄膜バイパスコンデン
サ10が配線層上、あるいはセラミック基板上に形成さ
れている。ここで、バイパスコンデンサ10はPGA−
ICの接続用パッド6の直近に挿入することが重要であ
るが、本発明ではバイパスコンデンサ10も上記配線層
5と同様にフォトリソグラフィで形成でき、かつ1mm
角で数100pFの容量が可能なことから、薄膜バイパ
スコンデンサ10を配線層上、あるいはセラミック基板
上に高密度に形成でき、最短距離で接続用パッド6とグ
ランド層4との間に挿入できる。したがって、小形、高
密度、かつ大容量のバイパスコンデンサが容易に形成で
き、高速・高周波領域の測定を妨害していた電源ノイズ
を低減できる。Further, the ceramic substrate 1 has wiring for power supply, and supplies a required voltage to the PGA-IC through a power supply line (not shown) formed in the wiring layer 5. A thin film bypass capacitor 10 for reducing power source noise is formed on the power supply line on a wiring layer or on a ceramic substrate. Here, the bypass capacitor 10 is PGA-
It is important to insert the IC in the immediate vicinity of the connection pad 6 of the IC, but in the present invention, the bypass capacitor 10 can be formed by photolithography similarly to the wiring layer 5 and can be formed by 1 mm.
Since the capacitance of several hundred pF is possible at each corner, the thin film bypass capacitor 10 can be formed on the wiring layer or the ceramic substrate with high density and can be inserted between the connection pad 6 and the ground layer 4 in the shortest distance. Therefore, a small-sized, high-density and large-capacity bypass capacitor can be easily formed, and the power supply noise that has hindered the measurement in the high speed / high frequency region can be reduced.
【0015】以上述べた、銅ポリイミド配線、薄膜抵
抗、薄膜コンデンサ等をフォトリソグラフィにより形成
する技術により、小形・多端子PGA−ICの高速・高
周波領域の検査が可能である。The above-described technique of forming the copper polyimide wiring, the thin film resistor, the thin film capacitor and the like by photolithography enables the inspection of the small multi-terminal PGA-IC in the high speed / high frequency region.
【0016】上記図1の実施例では、特性インピーダン
スの制御が容易なストリップライン構造の1層の信号線
3を用いて接続用パッド6とプローブパッド7とを電気
的に接続しているが、多層のストリップライン構造の信
号線を用いてもよく、また、特性インピーダンス制御が
可能な他の構造であるマイクロストリップライン構造、
あるいは、コプレーナ構造等の信号線を用いても良い、
さらに、上記ストリップライン構造とマイクロストリッ
プライン構造との混在、あるいは、ストリップライン構
造とコプレーナ構造との混在した構成の信号線で接続し
ても良い。In the embodiment of FIG. 1 described above, the connection pad 6 and the probe pad 7 are electrically connected by using the one-layer signal line 3 having a stripline structure whose characteristic impedance can be easily controlled. A signal line having a multilayer stripline structure may be used, and a microstripline structure which is another structure capable of controlling characteristic impedance,
Alternatively, a signal line such as a coplanar structure may be used,
Furthermore, the stripline structure and the microstripline structure may be mixed or the stripline structure and the coplanar structure may be mixed.
【0017】また、本実施例ではプローブパッド7をプ
ローブカード表面に配置したが、セラミック基板1内の
配線(およびヴィア)を介してセラミック基板1の裏面
に配置しても良い。さらに、セラミック基板の縁部、あ
るいは裏面にプローブパッド7の代わりに同軸コネクタ
を配置し、同軸ケーブルを直接接続して検査系装置と接
続しても良い。また、樹脂絶縁膜2として低誘電率なテ
フロン等を用いてもよく、信号線3等の導体材料として
金、Ni等の金属を用いても良い。なお、上記実施例は
PGA−IC検査用の場合を説明したが、本発明はQF
P−IC等の実装形態のICの検査用にも適用できる。Further, although the probe pad 7 is arranged on the front surface of the probe card in this embodiment, it may be arranged on the rear surface of the ceramic substrate 1 via the wiring (and the via) in the ceramic substrate 1. Further, a coaxial connector may be arranged instead of the probe pad 7 on the edge portion or the back surface of the ceramic substrate, and the coaxial cable may be directly connected to be connected to the inspection system device. Further, Teflon or the like having a low dielectric constant may be used as the resin insulating film 2, and metal such as gold or Ni may be used as the conductor material of the signal line 3 or the like. In addition, although the above-mentioned embodiment explained the case for PGA-IC inspection, the present invention is not limited to QF
It can also be applied to the inspection of an IC in a mounting form such as a P-IC.
【0018】[0018]
【発明の効果】PGA−ICの検査用治具において、配
線板に搭載する形態のPGA−ICの端子と接続する接
続用パッドと、信号等の入出力端子と、両者を電気的に
接続する樹脂絶縁膜を用いたストリップライン構造、あ
るいはマイクロストリップライン構造、あるいはコプレ
ーナ構造、あるいはこれらの混在した構造の特性インピ
ーダンスを制御した信号線とから構成されるプローブカ
ードを用いることにより、PGA−ICの端子形状、配
置等に依存することなく多端子のPGA−ICの高速・
高周波領域の電気特性検査が容易に行うことが可能とな
る。また、PGA−ICを配線板に搭載する形態で検査
できるため、実用時に近い検査が可能である。INDUSTRIAL APPLICABILITY In a PGA-IC inspection jig, a connection pad connected to a terminal of a PGA-IC mounted on a wiring board, an input / output terminal for signals, etc. are electrically connected to each other. By using a probe card composed of a stripline structure using a resin insulating film, a microstripline structure, a coplanar structure, or a signal line whose characteristic impedance is controlled in a structure in which these are mixed, a PGA-IC High-speed PGA-IC with multiple terminals, independent of terminal shape, layout, etc.
It becomes possible to easily perform the electrical characteristic inspection in the high frequency region. Further, since the PGA-IC can be inspected in the form of being mounted on the wiring board, the inspection close to that in practical use is possible.
【図1】本発明の一実施例を示す図で(a)は平面図、
(b)は断面図である。FIG. 1A is a plan view showing an embodiment of the present invention, FIG.
(B) is a sectional view.
【図2】樹脂絶縁膜厚と引き出し信号線の特性インピー
ダンスとの関係を示す図である。FIG. 2 is a diagram showing a relationship between a resin insulation film thickness and a characteristic impedance of a lead-out signal line.
【図3】ピンを入出力端子とするPGA−ICの(a)
は斜視図、(b)は(a)を上下反転して示した斜視図
である。FIG. 3 (a) of a PGA-IC having pins as input / output terminals
Is a perspective view, and (b) is a perspective view showing (a) inverted upside down.
【図4】パッドを入出力端子とするPGA−ICの
(a)は斜視図、(b)は(a)を上下反転して示した
斜視図である。FIG. 4A is a perspective view of a PGA-IC using pads as input / output terminals, and FIG. 4B is a perspective view of FIG.
【図5】従来のプローブカードを示す図で(a)は平面
図、(b)は断面図である。5A and 5B are diagrams showing a conventional probe card, in which FIG. 5A is a plan view and FIG. 5B is a sectional view.
【図6】364端子のPGA−ICの端子配置例を示す
図で、(a)は平面図、(b)は端子を引き出し線に展
開する場合の状態を拡大して示す図である。6A and 6B are diagrams showing a terminal arrangement example of a PGA-IC having 364 terminals, FIG. 6A is a plan view, and FIG. 6B is an enlarged view showing a state in which the terminals are developed into lead lines.
1…セラミック基板 2…樹脂絶縁膜 3…引き出し信号線 4…グランド層 5…配線層 6…接続用パッド 7…プローブパッド 8…プローブカード 9…薄膜終端抵抗 10…薄膜バイパスコンデンサ 11…入出力端子 12…PGA−IC 13…プリント配線板 14…引き出し信号線 15…検査用パッド 16…終端用チップ抵抗 17…バイパスコンデンサ 18…ボンディングパッド 19…ボンディングワイヤ 20…グランド端子 21…グランド線 22…接続用パッド 31…入出力端子 32…PGA−IC 41…信号端子 42…グランド端子 43…展開引き出し線 DESCRIPTION OF SYMBOLS 1 ... Ceramic substrate 2 ... Resin insulating film 3 ... Lead-out signal line 4 ... Ground layer 5 ... Wiring layer 6 ... Connection pad 7 ... Probe pad 8 ... Probe card 9 ... Thin film termination resistor 10 ... Thin film bypass capacitor 11 ... Input / output terminal 12 ... PGA-IC 13 ... Printed wiring board 14 ... Lead-out signal line 15 ... Inspection pad 16 ... Termination chip resistor 17 ... Bypass capacitor 18 ... Bonding pad 19 ... Bonding wire 20 ... Ground terminal 21 ... Ground wire 22 ... Connection Pad 31 ... Input / output terminal 32 ... PGA-IC 41 ... Signal terminal 42 ... Ground terminal 43 ... Development lead wire
Claims (1)
ッケージに実装された形態のICの検査用治具であるプ
ローブカードにおいて、 セラミック基板と、この基板上に形成された配線層とを
具え、 上記配線層は、樹脂絶縁膜と、この膜内に形成されたグ
ランド層と、特性インピーダンスがグランド層までの樹
脂絶縁膜厚により制御されて形成された引き出し信号線
とで構成され、 上記配線層の表面に形成されて被検査ICの入出力端子
と接続する接続用パッドと、配線層またはセラミック基
板の表面に形成されて検査用信号の入出力端子となるプ
ローブパッドとが上記引き出し信号線により電気的に接
続され、 終端用の薄膜抵抗およびノイズ低減用の薄膜バイパスコ
ンデンサが、上記配線層またはセラミック基板の表面に
形成されている、 ことを特徴とするプローブカード。1. A probe card, which is an IC inspection jig mounted in a package in which input / output terminals are arranged in an array, comprises a ceramic substrate and a wiring layer formed on the substrate. The wiring layer includes a resin insulating film, a ground layer formed in the film, and a lead-out signal line formed by controlling the characteristic impedance by the resin insulating film thickness up to the ground layer, The lead-out signal includes the connection pad formed on the surface of the wiring layer and connected to the input / output terminal of the IC to be inspected, and the probe pad formed on the surface of the wiring layer or the ceramic substrate and serving as the input / output terminal of the inspection signal. A thin film resistor for termination and a thin film bypass capacitor for noise reduction, which are electrically connected by wires, are formed on the surface of the wiring layer or ceramic substrate. , A probe card characterized by the following.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4289947A JPH06140484A (en) | 1992-10-28 | 1992-10-28 | Probe card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4289947A JPH06140484A (en) | 1992-10-28 | 1992-10-28 | Probe card |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06140484A true JPH06140484A (en) | 1994-05-20 |
Family
ID=17749801
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4289947A Pending JPH06140484A (en) | 1992-10-28 | 1992-10-28 | Probe card |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06140484A (en) |
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0708338A2 (en) * | 1994-10-17 | 1996-04-24 | Nihon Denshizairyo Kabushiki Kaisha | Probe card for high temperature application |
JPH08254545A (en) * | 1995-02-03 | 1996-10-01 | Hewlett Packard Co <Hp> | Voltage probe of many leads |
JPH10282144A (en) * | 1997-04-07 | 1998-10-23 | Micronics Japan Co Ltd | Probe unit for testing flat-plate-shaped body to be inspected |
JPH1152011A (en) * | 1997-08-06 | 1999-02-26 | Jsr Corp | Inspection device |
JPH11148951A (en) * | 1997-11-18 | 1999-06-02 | Pfu Ltd | Impedance measuring device and its wiring |
JPH11160356A (en) * | 1997-11-25 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Probe card for wafer collective measurement and inspection and ceramic multilayer interconnection board as well as their manufacture |
JP2000187057A (en) * | 1998-12-21 | 2000-07-04 | Noozeru Engineering Kk | Inspection device for semiconductor device |
JP2002055144A (en) * | 2000-05-23 | 2002-02-20 | Tektronix Inc | Signal detector, and method of detecting signal |
JP2005524855A (en) * | 2002-05-08 | 2005-08-18 | フォームファクター,インコーポレイテッド | High performance probe system for testing semiconductor wafers |
US7255575B2 (en) | 2004-04-27 | 2007-08-14 | Yoshiei Hasegawa | Electrical connecting apparatus |
KR100771476B1 (en) * | 2006-06-16 | 2007-10-30 | 가부시키가이샤 니혼 마이크로닉스 | Electric Connecting Device |
CN100346467C (en) * | 2005-07-19 | 2007-10-31 | 钰创科技股份有限公司 | Circuit rewiring method and circuit structure |
EP1873826A2 (en) * | 2005-04-18 | 2008-01-02 | Murata Manufacturing Co., Ltd. | Electronic component module |
JP2008510966A (en) * | 2004-08-19 | 2008-04-10 | フォームファクター, インコーポレイテッド | How to make wire bond probe cards in multiple ways at once |
JP2008197118A (en) * | 2001-07-11 | 2008-08-28 | Formfactor Inc | Method of manufacturing probe card |
JP2009177011A (en) * | 2008-01-25 | 2009-08-06 | Ferrotec Ceramics Corp | Conductive member, and component and equipment using it |
JP2010151560A (en) * | 2008-12-25 | 2010-07-08 | Japan Electronic Materials Corp | Probe card |
US7764075B2 (en) | 2002-05-08 | 2010-07-27 | Formfactor, Inc. | High performance probe system |
US7764073B2 (en) | 2005-04-18 | 2010-07-27 | Kabushiki Kaisha Nihon Micronics | Electrical connecting apparatus |
JP2011085572A (en) * | 2009-10-19 | 2011-04-28 | Samsung Electro-Mechanics Co Ltd | Probe substrate and method for manufacturing the same |
JP2012189607A (en) * | 2005-01-07 | 2012-10-04 | Formfactor Inc | Apparatus for increasing operating frequency of system for testing electronic devices |
JP5107431B2 (en) * | 2008-09-05 | 2012-12-26 | 日本発條株式会社 | Probe card |
JP2016153796A (en) * | 2016-03-31 | 2016-08-25 | スリーエム イノベイティブ プロパティズ カンパニー | Ic device testing socket |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63122140A (en) * | 1986-11-12 | 1988-05-26 | Hitachi Ltd | Semiconductor element inspecting device and manufacture thereof |
JPH01123157A (en) * | 1987-11-09 | 1989-05-16 | Hitachi Ltd | Probe head for semiconductor lsi inspecting apparatus and preparation thereof |
JPH04266043A (en) * | 1990-10-31 | 1992-09-22 | Hughes Aircraft Co | Apparatus and method for test of integrated circuit |
-
1992
- 1992-10-28 JP JP4289947A patent/JPH06140484A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63122140A (en) * | 1986-11-12 | 1988-05-26 | Hitachi Ltd | Semiconductor element inspecting device and manufacture thereof |
JPH01123157A (en) * | 1987-11-09 | 1989-05-16 | Hitachi Ltd | Probe head for semiconductor lsi inspecting apparatus and preparation thereof |
JPH04266043A (en) * | 1990-10-31 | 1992-09-22 | Hughes Aircraft Co | Apparatus and method for test of integrated circuit |
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0708338A3 (en) * | 1994-10-17 | 1996-07-31 | Nihon Denshizairyo Kk | Probe card for high temperature application |
EP0708338A2 (en) * | 1994-10-17 | 1996-04-24 | Nihon Denshizairyo Kabushiki Kaisha | Probe card for high temperature application |
JPH08254545A (en) * | 1995-02-03 | 1996-10-01 | Hewlett Packard Co <Hp> | Voltage probe of many leads |
JPH10282144A (en) * | 1997-04-07 | 1998-10-23 | Micronics Japan Co Ltd | Probe unit for testing flat-plate-shaped body to be inspected |
JPH1152011A (en) * | 1997-08-06 | 1999-02-26 | Jsr Corp | Inspection device |
JPH11148951A (en) * | 1997-11-18 | 1999-06-02 | Pfu Ltd | Impedance measuring device and its wiring |
JPH11160356A (en) * | 1997-11-25 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Probe card for wafer collective measurement and inspection and ceramic multilayer interconnection board as well as their manufacture |
JP2000187057A (en) * | 1998-12-21 | 2000-07-04 | Noozeru Engineering Kk | Inspection device for semiconductor device |
JP2002055144A (en) * | 2000-05-23 | 2002-02-20 | Tektronix Inc | Signal detector, and method of detecting signal |
JP2008197118A (en) * | 2001-07-11 | 2008-08-28 | Formfactor Inc | Method of manufacturing probe card |
US7764075B2 (en) | 2002-05-08 | 2010-07-27 | Formfactor, Inc. | High performance probe system |
JP2005524855A (en) * | 2002-05-08 | 2005-08-18 | フォームファクター,インコーポレイテッド | High performance probe system for testing semiconductor wafers |
US8614590B2 (en) | 2002-05-08 | 2013-12-24 | Charles A. Miller | High performance probe system |
US7255575B2 (en) | 2004-04-27 | 2007-08-14 | Yoshiei Hasegawa | Electrical connecting apparatus |
JP2008510966A (en) * | 2004-08-19 | 2008-04-10 | フォームファクター, インコーポレイテッド | How to make wire bond probe cards in multiple ways at once |
JP2012189607A (en) * | 2005-01-07 | 2012-10-04 | Formfactor Inc | Apparatus for increasing operating frequency of system for testing electronic devices |
EP1873826A4 (en) * | 2005-04-18 | 2010-08-25 | Murata Manufacturing Co | Electronic component module |
US7764073B2 (en) | 2005-04-18 | 2010-07-27 | Kabushiki Kaisha Nihon Micronics | Electrical connecting apparatus |
EP1873826A2 (en) * | 2005-04-18 | 2008-01-02 | Murata Manufacturing Co., Ltd. | Electronic component module |
CN100346467C (en) * | 2005-07-19 | 2007-10-31 | 钰创科技股份有限公司 | Circuit rewiring method and circuit structure |
KR100771476B1 (en) * | 2006-06-16 | 2007-10-30 | 가부시키가이샤 니혼 마이크로닉스 | Electric Connecting Device |
JP2009177011A (en) * | 2008-01-25 | 2009-08-06 | Ferrotec Ceramics Corp | Conductive member, and component and equipment using it |
JP5107431B2 (en) * | 2008-09-05 | 2012-12-26 | 日本発條株式会社 | Probe card |
JP2010151560A (en) * | 2008-12-25 | 2010-07-08 | Japan Electronic Materials Corp | Probe card |
JP2011085572A (en) * | 2009-10-19 | 2011-04-28 | Samsung Electro-Mechanics Co Ltd | Probe substrate and method for manufacturing the same |
JP2016153796A (en) * | 2016-03-31 | 2016-08-25 | スリーエム イノベイティブ プロパティズ カンパニー | Ic device testing socket |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH06140484A (en) | Probe card | |
US4764723A (en) | Wafer probe | |
EP0702797B1 (en) | Integrated circuit probing apparatus including a capacitor bypass structure | |
KR100733945B1 (en) | Contact structure having silicon finger contactor and its producing method | |
US7388389B2 (en) | Electronic probe apparatus | |
JP3376731B2 (en) | High frequency printed circuit board and probe card using the same | |
JPS6369247A (en) | Prober | |
JPS60260861A (en) | Probe | |
Tsai | Package inductance characterization at high frequencies | |
JP4427645B2 (en) | Contact probe, measurement pad used for the contact probe, and method of manufacturing the contact probe | |
JP2004347591A (en) | Probe card for integrated circuit | |
JPH11248748A (en) | Probe card | |
EP0016087A1 (en) | Probe and interface device for integrated circuit wafers | |
JP3457599B2 (en) | Semiconductor device | |
WO1986006495A1 (en) | A coplanar waveguide probe | |
JP3971627B2 (en) | Method for evaluating characteristics of intermediate layer circuits | |
US20010050177A1 (en) | Connection structure of coaxial cable to electric circuit substrate | |
JP2001242195A (en) | Contact structure | |
JPH07122602A (en) | High frequency probe and probe circuit | |
JP2568495B2 (en) | Semiconductor device | |
JPH05144894A (en) | Probe card for tab-ic test | |
JPH09102521A (en) | Probe card | |
JPS594134A (en) | Probe card | |
JP3039807B2 (en) | Integrated circuit probe device having capacitor bypass structure | |
JPH06181246A (en) | Probing device |