JP3457599B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for mounting electronic parts which require high speed transmission.

[0002]

2. Description of the Related Art In recent years, electronic devices have become smaller and more sophisticated,
BGA (Ball Grid) is used as a package corresponding to the increase in operating speed and modularization.
Array Package) and CSP (Chip S)
Cale Package) and the like have been developed.

An example of a conventional BGA compatible with high-speed transmission will be described below with reference to the drawings.

FIG. 12 shows a conventional BGA compatible with high-speed transmission.
2 shows an example of the cross-sectional structure of FIG. In FIG.
1201 is a semiconductor element mounted on the BGA 1211,
1202 is a wire, 1203 is a molding resin, 1204
Is a solder resist, 1205 is a surface wiring, 1206 is a ground layer (hereinafter referred to as a GND layer), 1207 is a power layer, 1
Reference numeral 208 is a back surface wiring, 1209 is a via, and 1210 is a solder ball. The BGA1211 is configured as a whole.

In the BGA 1211, the semiconductor element 1201 is mounted on a base material which is a wiring board, and the semiconductor element 120 is connected to the surface wiring 1205 formed on the base material by a wire 1202.
No. 1 electrode pad is connected. As a result, the electrode pad of the semiconductor element 1201 is connected to the wire 1202 and the surface wiring 1.
It is electrically connected to the solder ball 1210 via 205, the via 1209, and the rear surface wiring 1208. further,
By electrically connecting to the outside through the solder ball 1210, it is possible to input to the electrode pad of the semiconductor element 1201. The base material on which the semiconductor element 1201 is mounted has a plurality of dielectric layers (BT resin or the like) laminated and wirings such as the surface wiring 1205, the GND layer 1206, the power supply layer 1207, and the back wiring 1208. It is a substrate, and a via 1209 electrically connects the upper and lower wirings to form a desired wiring path. The solder resist 1204 is used for the surface wiring 12 except for a portion near the periphery of the semiconductor element 1201 to which the wire 1202 is connected.
05 is formed on the surface of the base material. The surface wiring 1205 and the back wiring 1208 are respectively connected to the GND layer 12
06 and the power supply layer 1207 constitute a microstrip line, and each wiring itself is designed to have a desired characteristic impedance Z ₀ .

FIG. 13 shows a conventional BGA compatible with high-speed transmission.
2 shows an example of the surface wiring pattern of FIG. 121
Reference numeral 2 denotes a plating stub used in the electroplating process for forming wiring. The plating stub is used to electrically connect the wires between the BGAs in the process of forming a plurality of wires on the BGA at a time by electrolytic plating. It was left in the state of. For this reason, the plating stub can be used not only on the surface wiring layer but also on the backside wiring layer and GN.
It is formed in each layer such as the D layer and the power source layer.

FIG. 14 shows a conventional CSP compatible with high-speed transmission.
2 shows an example of the cross-sectional structure of FIG. In FIG.
1401 is a semiconductor device mounted on the CSP 1410,
1402 is a bump, 1403 is an underfill resin, 1
Reference numeral 404 is a surface layer wiring, 1405 is a ground layer (hereinafter referred to as a GND layer), 1406 is a power supply layer, 1407 is a backside wiring, 1
Reference numeral 408 is a via, and 1409 is an external pad. C as a whole
It constitutes SP1410.

In the CSP 1410, the semiconductor element 1401 is mounted on a base material which is a wiring board, and the semiconductor element 140 is bumped 1402 to the surface wiring 1404 formed on the base material.
No. 1 electrode pad is connected. As a result, the electrode pads of the semiconductor element 1401 are connected to the bump 1402 and the surface wiring 1.
It is electrically connected to the external pad 1409 via the 404, the via 1408 and the rear surface wiring 1407. Further, by electrically connecting to the outside through the external pad 1409, the data can be input to the electrode pad of the semiconductor element 1401. In addition, the base material on which the semiconductor element 1401 is mounted has a plurality of dielectric layers (alumina or the like) stacked, and the surface wiring 1404, the GND layer 1405, and the power supply layer 140.
6. The wiring board is formed with wiring such as the back wiring 1407, and the via 1408 electrically connects the upper and lower wirings to form a desired wiring path. The surface wiring 1404 and the back wiring 1407 constitute microstrip lines for the GND layer 1405 and the power supply layer 1406, respectively, and the wirings themselves are designed to have a desired characteristic impedance Z _0. ing.

FIG. 15 shows a conventional CSP compatible with high-speed transmission.
2 shows an example of the surface wiring pattern of FIG. 141
Reference numeral 1 denotes a plating stub used in an electrolytic plating process for forming wiring. The plating stub is used to electrically connect the wiring between the CSPs in the process of forming a plurality of wirings on the CSP by electrolytic plating at a time, and is cut off when the CSPs are separated into individual pieces. It was left in the state of. Therefore, C
The SP plating stub is also formed in each layer as in the BGA.

Here, when the length from the electrode pad of the semiconductor element 1201 or 1401 of the signal line on the BGA or CSP to the solder ball 1210 or the external pad 1409 is sufficiently shorter than the frequency band used, the signal line of the signal line is changed. The characteristic impedance can be arbitrary.

[0011]

At the time of high-speed transmission, for example, when the clock frequency is 3 GHz, there are quite a few cases in which a harmonic component of a rectangular wave requires about a 10th harmonic or more. In this case, the required frequency band is 30G
It becomes more than Hz. The wavelength of the sine wave of 30 GHz is 10 mm in air, and the effective wavelength λg on the BT resin (relative permittivity, about 4), which is a material of BGA, is about 5 mm, for example.

For example, in the case of BGA as an example, as shown in FIG. 12, in the conventional structure, the plating stub 1212, the solder ball 1210, and the electrode pad to which the plating stub 1212 is attached (hereinafter,
Call it a ball pad. ) Exists. The plating stub behaves as an open stub at high frequencies, and the ball pad usually also acts as a capacitance. Therefore, even if the transmission line on the package is designed as a microstrip line having a certain characteristic impedance Z ₀ , it is divided into blocks as shown in FIG. 16, and the influence of the plating stub and ball pad can be ignored. The transmission line does not always have the characteristic impedance as designed for the single transmission line. For this reason, only by matching the characteristic impedance of the signal line on the motherboard of the system and the characteristic impedance of only the line on the package,
There is a problem that the characteristic impedance of the entire package and the characteristic impedance of the signal line on the motherboard are inconsistent, the rectangular wave on the signal line fluctuates greatly, and the malfunction of the system is induced. Note that, for example, as shown in FIG. 17, the solder balls are sucked by using a suction jig and placed on a ball pad (not shown) integrally formed with the backside wiring. Formed by reflowing (ball set method).

Also in the case of CSP, the plating stub 1
411 behaves as an open stub in high frequency,
Further, the external pad 1409, like the ball pad of the BGA, usually behaves as a capacitance, and therefore has the same problem as the BGA described above.

In view of the above problems, the present invention has a structure for realizing a uniform characteristic impedance in the entire signal line on the package in a desired frequency range in a BGA or CSP package in which a semiconductor element is mounted, and a portion where the characteristic impedance is not uniform. It is an object of the present invention to provide a semiconductor device capable of minimizing signal distortion in a package portion by proposing a structure that limits a length range in which there is no problem in transmission even if there is a problem.

[0015]

According to the present invention, the characteristic impedance of the line on the package can be made constant or non-uniform, and the structure is as follows.

According to another aspect of the semiconductor device of the present invention, a semiconductor element having a plurality of electrode pads and an electric signal, electric power, or the like from the electrode pad of the semiconductor element, on which the semiconductor element is mounted, are output or externally output through conductor wiring. and a substrate provided with an external electrode pad input from, a semiconductor device having a plating stub conductor wiring substrate, Oyo plating stubs
And the external electrode pad at the highest frequency of the electrical signal
Plating stub length and external electrode to show capacitive
It is characterized in that the shape of the pad is set so that the characteristic impedance of the conductor wiring from the external electrode pad to the portion connected to the electrode pad of the semiconductor element is constant.
A semiconductor device according to claim 2 is the semiconductor device according to claim 1.
The semiconductor device electrode pad from the external electrode pad.
Out of the conductor wiring up to the
Alternatively, the presence of external electrode pads can
Place the conductor wiring beyond the range where the impedance changes.
The line width is changed from the external electrode pad to the electrode pad of the semiconductor element.
Characteristic impedance of all conductor wiring up to the connection part
Is set to a constant wiring width. Claim 3
The semiconductor device according to claim 1 is the semiconductor device according to claim 1.
Connect the external electrode pad to the electrode pad of the semiconductor element
Of the conductor wiring up to the
Characteristic impedance of conductor wiring due to the presence of partial electrode pads
The length of the conductor wiring beyond the range in which the
A multiple of half the effective wavelength of the highest frequency of the air signal
The same length and the characteristic wiring of the conductor wiring seen from the external electrode pad
Presence of pedestal and plating stubs or external electrode pads
The range in which the characteristic impedance of the conductor wiring changes
If the characteristic impedance of the conductor wiring in the excess part is the same
Load such as plating stub or external electrode pad
Characteristic impedance of conductor wiring changes due to the presence of
By forming it at the end of the conductor wiring that exceeds the range
Connection from external electrode pad to electrode pad of semiconductor element
The characteristic impedance is uniform in all conductor wiring up to the
It is characterized in that it is set to be constant. Claim 4
The semiconductor device is the semiconductor device according to claim 1,
Part that connects from the electrode pad to the electrode pad of the semiconductor element
Of the conductor wire to the minute, plating-out stub or external electrodes
The presence of the pad changes the characteristic impedance of the conductor wiring.
The length of the conductor wiring that exceeds the range
And the same length as a multiple of half the effective wavelength of the highest frequency
The characteristic impedance of the conductor wiring seen from the external electrode pad
And the presence of plating stubs or external electrode pads
Exceeds the range in which the characteristic impedance of the conductor wiring changes
The characteristic impedance of the part of the conductor wiring will be the same.
By providing such a load inside the semiconductor element,
Part that connects from the electrode pad to the electrode pad of the semiconductor element
The characteristic impedance is constant for all conductor wires up to
It is characterized by doing so. The semiconductor according to claim 5.
The device is the semiconductor device according to claim 1, wherein an external electrode is provided.
From the pad to the part that connects to the electrode pad of the semiconductor element
Of the conductor wiring of the plating stub or external electrode pad
Characteristic impedance of conductor wiring changes due to the presence of
The electrical signal has the length of the conductor wiring that exceeds the range.
The same length as a multiple of half the effective wavelength of the highest frequency
Characteristic impedance of the conductor wiring seen from the electrode pad
Conductor placement due to the presence of plating stubs or external electrode pads
Of the part that exceeds the range in which the characteristic impedance of the line changes
Negative impedance that is the same as the characteristic impedance of the conductor wiring
By holding the load on the electrode pad of the semiconductor element,
Connection from external electrode pad to electrode pad of semiconductor element
Characteristic impedance is constant for all conductor wiring up to the part
It is characterized in that

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023] The semiconductor device according to claim 6, wherein a semiconductor element having a plurality of electrode pads, output or external electrical signals from the electrode pads of the semiconductor device mounted with semiconductor elements, a power, etc. to the outside through the conductor wirings A semiconductor device having a base material provided with an external electrode pad for input from a semiconductor device having a plating stub on the conductor wiring of the base material, wherein the conductor wiring from the external electrode pad to a portion connected to the electrode pad of the semiconductor element among them, the length of the conductor wiring portion exceeding the scope of varying the characteristic impedance of the conductive wire by the presence of the plating stub or external electrode pads, the characteristic impedance is not
The length is such that even if there is a uniform portion, there is no problem in transmission.
It is characterized in that it is configured to be less than a quarter of the effective wavelength of the highest frequency of the electric signal.

According to the present onset light as described above, by which the configuration in which the characteristic impedance of the conductor wire to the part to be connected to the electrode pads of the semiconductor element from the external electrode pad is constant, BGA mounting the semiconductor element In a CSP package, a uniform characteristic impedance can be realized in the entire signal line on the package in a desired frequency range, and signal distortion in the package portion can be minimized.

Further, according to this onset bright, the length of the conductor wiring portion exceeding the scope of varying the characteristic impedance of the conductive wire by the presence of the plating stub or external electrode pads, the effective wavelength of the highest frequency electrical signal has It is less than 1/4 of that of BGA and C equipped with semiconductor elements.
In the SP package, even if there is a portion where the characteristic impedance is not uniform in the desired frequency range, there is no problem in transmission, and the signal distortion in the package portion can be minimized.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. In the following embodiments, as an example of the semiconductor device of the present invention, a BGA compatible with high-speed transmission is used.
Will be described. In addition, in FIG. 1, FIG. 6, FIG. 9 to FIG. 11 used in the following description, the solder register 1204 (FIG.
2) is not shown.

[First Embodiment] FIG. 1 is a schematic cross-sectional view of a high-speed transmission compatible BGA according to a first embodiment of the present invention. 1, 1 is a semiconductor element, 2 is a wire, 3 is a BGA substrate, 4 is a signal line, 5 is a via, 6 is a plating stub, 7 is a ball pad (external electrode pad), 8 is a solder ball, and 9 is The GND layer 10 indicates a power supply layer. The ball pad 7, which is an electrode pad to which the solder ball 8 is attached, is made of the same material as the backside wiring (not shown) and is integrally formed at the same time. On this ball pad 7,
For example, the solder balls 8 are formed by the ball setting method shown in FIG.

Here, the signal line 4 constitutes a microstrip line with respect to the GND layer 9 or the power supply layer 10 and is designed to have a certain characteristic impedance. At this time, the ball pad 7 and the plating stub 6 affect the microstrip line and change the characteristic impedance of the microstrip line. Such electrical influence of the ball pad 7 and the plating stub 6 does not extend to a certain range of the microstrip line and beyond that range. As described above, the electrical influence of the ball pad 7 and the plating stub 6 in the embodiment of the present invention means that the presence of these changes the characteristic impedance of the signal line 4 constituting the microstrip line. .

FIG. 2 is a block diagram of FIG. 16 using a SPICE simulator, in which TDR (Time) when all the influences of ball pads and plating stubs on the BGA line are exerted.
Domain reflection (time domain reflection) waveform is estimated, and FIG. 3 is an estimation result of the TDR waveform when there is a range where the influence is not exerted. The TDR waveforms in FIGS. 2 and 3 are BGs with plating stubs, ball pads, transmission lines, vias, and wire pads.
This is a simulation of the reflection waveform of the step function propagating through the BGA upper line and reflected at the open end when a step function that rises rapidly from the ball pad part is applied under the condition that the wire pad part of the upper line A is open. is there. The input / output impedance of the measuring instrument is 50 here.
The voltage waveform is set to Ω, and the voltage waveform when 50 Ω is simply connected to the terminal end is the ideal 50 Ω termination waveform in FIGS. It is displayed in order to calculate the impedance of the changed portion when the voltage value in this case is 50Ω.

In FIG. 2 and FIG. 3, the portion indicated as the probe portion represents the reflection waveform observed on the measurement probe that is assumed in the actual measurement. For this reason, the BGA line starts from the portion where the 50Ω termination ideal waveform after the portion labeled as the probe portion starts to change, and the voltage value at each time represents the impedance of each transmission line as it is. The entire transmission line is constant at about 30Ω, and in FIG. 3, it is about 30Ω at the portion near the ball pad and the plating stub (under the influence of the ball pad and the plating stub).
Then, it was estimated that it exceeded 50 Ω at a slightly distant place. The portion where the voltage at the right end sharply rises indicates that the impedance rises to infinity at the open end.

In the case of FIG. 2, it can be seen that the impedance of the transmission line is low and constant due to the influence of the ball pad and the like. This refers to a portion where the voltage is constant around 180 mV. However, since the step function is also simulated with a slight slope, the slope appears to be constant until it becomes constant, and it looks like a bathtub, but it is considered that the whole line is almost constant. Therefore, a desired uniform impedance line can be formed by limiting the range of the microstrip line (signal line 4) within the range where the ball pad 7 and the plating stub 6 are electrically affected.

Here, the line such as the plating stub 6 shows capacitive, inductive, short circuit, and open depending on the frequency used. The input impedance of the open stub (plating stub) is shown by the equation 1.

[0033]

[Equation 1]

In Equation 1, Z _in is the input impedance of the open stub (plating stub), Z ₀ is the characteristic impedance of the open line, l (ell) is the line length, and here the length of the open stub (plating stub), β Is a phase constant, and β = 2π / λ (λ is a wavelength).

Here, it will be explained that β = 2π / λ. The general solution of the voltage V and the current I on the infinitely long distributed constant line is expressed by the equation 2.

[0036]

[Equation 2]

Γ is a propagation constant. Further, Z is a series impedance (usually inductive), and Y is a parallel admittance (usually capacitive), which can be expressed as in Equation 3.

[0038]

[Equation 3]

R, L, C and G are resistance, inductance, capacitance and parallel conductance per unit length,
ω is the angular frequency. If these are used to express γ,
become.

[0040]

[Equation 4]

Since the transmission line generally has a small loss, α and β in the equation 4 are approximated to the equation 5.

[0042]

[Equation 5]

In the lossless line, α = 0. The square root of LC represents the phase velocity, and the phase constant β is given by the equation 6.

[0044]

[Equation 6]

The relationship between tan βl and βl to l is shown in FIG. 4, and as a result, the characteristic of the input impedance Z _in is as shown in Table 1.

[0046]

[Table 1]

From Table 1, as described above, the plating stub 6
It can be seen that the lines, etc. exhibit capacitive, inductive, short circuit (Z _in = 0), open (Z _in = ∞).

In the base band system (digital system), the rectangular wave contains various frequency components as described above. In particular, in order to have the characteristics shown in FIG. The plating stub 6 and the like need to show capacity. Plating stub 6, ball pad 7
However, in order to show the capacitance in the desired frequency range, it suffices to show the capacitance at the highest frequency in the desired frequency range.
The length of the plating stub 6 and the shape of the ball pad 7 are set. The ball pad 7 is usually circular and its shape is symmetric with respect to the feeding point when the feeding point is in the center, and therefore exhibits a capacitive characteristic. Inductivity occurs when the shape is asymmetric with respect to the feeding point, and when the feeding point is circular and the center is the feeding point, it can be said that the dimension of the ball pad 7 with respect to the feeding point does not become inductive. .

As described above, by keeping the characteristic impedance of the transmission line on the BGA constant, the distortion of the signal waveform on the package transmission line can be removed, and the malfunction of the system can be eliminated.

[Second Embodiment] FIG. 5 shows a second embodiment of the present invention.
FIG. 9 is a plan view schematically showing a case where the wiring pattern on the outermost surface of the high-speed transmission compatible BGA in the embodiment is viewed from directly above. FIG. 6 is a schematic cross-sectional view of a high-speed transmission compatible BGA according to the second embodiment. 5 and 6,
1 is a semiconductor element, 2 is a wire, 5 is a via, 6 is a plating stub, 7 is a ball pad, 8 is a solder ball, and 9 is GN.
D layer, 10 is a power supply layer, 53 is a BGA base material, 54 is a signal line in a range where the plating stub 6 and the ball pad 7 are electrically affected, and 55 is a plating stub 6 and the ball pad 7 are not electrically affected. The range signal lines are shown. Here, it is assumed that the ball pad 7 and the plating stub 6 are formed so as to show capacitance in a desired frequency range, as in the first embodiment.

In the present embodiment, the signal line 55 within a range where the plating stub 6 and the ball pad 7 are not electrically affected.
Indicates that the impedance of the signal line 54 is low in the range where the electrical influence of the plating stub 6 and the ball pad 7 is exerted, so that the impedance of the signal line 55 has a desired wiring width that matches the impedance of the signal line 54. It is set. Here, the wiring width of the signal line 55 is set wider than the wiring width of the signal line 54. As a result, the signal line 54
And the signal line 55 have the same impedance, and the impedance on the BGA can be a constant value.

As described above, by making the characteristic impedance of the transmission line on the BGA constant, the distortion of the signal waveform on the package transmission line can be removed and the malfunction of the system can be eliminated.

[Third Embodiment] Before describing the configuration of the third embodiment, an example of the idea of the present embodiment will be described with reference to FIG.

As shown in FIG. 7, the characteristic impedance Z
_{When the} load Z _L is connected to the end of the transmission line having ₀ , the impedance Z _in seen from the point separated from the load Z _L by L
Is given by equation 7.

[0055]

[Equation 7]

From Equation 7, L = λ / 2, λ, 3λ / 2, ...
··· In, Z _in = Z _L. That is, Z _L is halved at an arbitrary frequency on the transmission line having an impedance of Z _0.
The impedance Z _in viewed from the position of the multiple of the effective wavelength is Z _L.

FIG. 8 is a plan view schematically showing a case where the wiring pattern on the outermost surface of the BGA compatible with high-speed transmission according to the third embodiment of the present invention is viewed from directly above. It is the same as FIG. 6 except that the two connection portions and the end portion of the signal line 85 in the vicinity thereof are different. In FIG.
Reference numeral 1 is a semiconductor element, 2 is a wire, 5 is a via, 6 is a plating stub, 83 is a BGA base material, 84 is a plating stub 6, and a signal line in a range in which the ball pad 7 (see FIG. 6) is electrically affected. Is a signal line in a range where the plating stub 6 and the ball pad 7 are not electrically affected, and 86 is a capacitive load formed at the end of the signal line 85 in a range where the plating stub 6 and the ball pad 7 are not electrically affected. Indicates. The capacitive load 86 is connected near the tip of the signal line 85 (range in which the capacitance extends to the entire signal line), and a circuit pattern having a capacitive shape such as a line with a large wiring width or a circular pad is formed on the surface layer. Alternatively, it may be formed in an inner layer and connected, or an external component such as a chip capacitor or a thin film capacitive element may be used. The line length of the signal line 85 is set to a length that is a multiple of ½ of the effective wavelength of the highest frequency of the desired frequency band. Here, it is assumed that the ball pad 7 and the plating stub 6 are formed so as to exhibit capacitance in a desired frequency range, as in the first embodiment.

The impedance of the signal line 84 in the range where the plating stub 6 and the ball pad 7 are electrically affected is lower than the impedance of the signal line 85 where the plating stub 6 and the ball pad 7 are not electrically affected. , Signal line 8
A desired load 86 for matching the impedance of No. 5 with the impedance of the signal line 84 is formed at the end of the signal line 85, and the line length of the signal line 85 is half the effective wavelength of the highest frequency of the desired frequency band. By setting the length to be a multiple of, the signal line 84 and the signal line 85 have the same impedance, and the impedance on the BGA can be a constant value. Here, the line length of the signal line 85 is set with respect to the effective wavelength of the highest frequency because it is assumed that the characteristics of signal transmission are determined at the highest frequency of rising and falling. Is. Note that the impedance of the signal line 84 alone is high impedance, but the impedance of the signal line 84 to be matched here with the impedance of the signal line 85 is an electrical effect of the plating stub 6 and the ball pad 7. The characteristic impedance of the conductor wiring as viewed from the external electrode pad.

As described above, by keeping the characteristic impedance of the transmission line on the BGA constant, the distortion of the signal waveform on the package transmission line can be removed, and the malfunction of the system can be eliminated.

[Fourth Embodiment] FIG. 9 is a schematic cross-sectional view of a high speed transmission compatible BGA according to a fourth embodiment of the present invention. In FIG. 9, 2 is a wire, 5 is a via, 6 is a plating stub, 7 is a ball pad, 8 is a solder ball,
9 is a GND layer, 10 is a power supply layer, 91 is a semiconductor element, and 93
BGA base material, 94 plating stub 6, ball pad 7
Signal line in the range where the electric influence of the plating stub 6 and the ball pad 7 does not reach the electric line, and 96 represents a capacitive load provided in the semiconductor element 91. The capacitive load 96 is, for example, the semiconductor element 91.
The capacitor may be a parallel plate capacitor having an insulating layer sandwiched therein, and may be connected to the wire 2 through the line of the semiconductor element 91. Further, the pad connected to the wire 2 may be one electrode of the capacitor, and below it. It may be a parallel plate capacitor in which the other electrode is formed with the insulating layer sandwiched therebetween. Here, it is assumed that the ball pad 7 and the plating stub 6 are formed so as to exhibit capacitance in a desired frequency range, as in the first embodiment.

The impedance of the signal line 94 in the range in which the plating stub 6 and the ball pad 7 are electrically influenced is lower than the impedance of the signal line 95 in the range in which the plating stub 6 and the ball pad 7 are not electrically affected. The capacitive load 96 in the semiconductor element 91 is set to a desired capacitance value so that the impedance of the signal line 95 matches the impedance of the signal line 94. The line length of the signal line 95 is set to a length that is a multiple of ½ of the effective wavelength of the highest frequency of the desired frequency band, as in the signal line 85 in the third embodiment. As a result, the signal line 94
And the signal line 95 have the same impedance, and the impedance on the BGA can be a constant value.

As described above, by keeping the characteristic impedance of the transmission line on the BGA constant, the distortion of the signal waveform on the package transmission line can be removed, and the malfunction of the system can be eliminated.

[Fifth Embodiment] FIG. 10 is a schematic cross-sectional view of a high speed transmission compatible BGA according to a fifth embodiment of the present invention. In FIG. 10, 2 is a wire, 5 is a via, 6
Is a plating stub, 7 is a ball pad, 8 is a solder ball, 9 is a GND layer, 10 is a power supply layer, 1001 is a semiconductor element, 1003 is a BGA base material, 1004 is the plating stub 6 and the ball pad 7 have an electrical effect. A signal line in a range 1005 indicates a signal line in a range where the plating stub 6 and the ball pad 7 do not have an electrical influence, and 1006 indicates an electrode pad provided on the semiconductor element 1001. here,
Similar to the first embodiment, it is assumed that the ball pad 7 and the plating stub 6 are formed so as to be capacitive in the desired frequency range.

In the fifth embodiment, the capacitive load in the fourth embodiment is not formed in the semiconductor element 1001, but the impedance of the signal line 1005 is changed by the capacitance of the electrode pad 1006 portion of the semiconductor element 1001. It has a structure that matches the impedance of the signal line 1004.

As described above, by making the characteristic impedance of the transmission line on the BGA constant, the distortion of the signal waveform on the package transmission line can be removed and the malfunction of the system can be eliminated.

[Sixth Embodiment] FIG. 11 is a schematic sectional view of a high-speed transmission compatible BGA according to a sixth embodiment of the present invention. In FIG. 11, 1 is a semiconductor element, 2 is a wire, 5 is a via, 6 is a plating stub, 7 is a ball pad,
8 is a solder ball, 9 is a GND layer, 10 is a power supply layer, 11
Reference numeral 03 is a BGA base material, 1104 is a signal line in a range where the plating stub 6 and the ball pad 7 are electrically affected.
Indicates a signal line in a range where the plating stub 6 and the ball pad 7 are not electrically affected. Here, it is assumed that the ball pad 7 and the plating stub 6 are formed so as to exhibit capacitance in a desired frequency range, as in the first embodiment.

In the sixth embodiment, the signal line 1 is in a range where the plating stub 6 and the ball pad 7 do not have an electrical influence.
The line length of 105 is less than a quarter of the effective wavelength of the highest frequency of the desired frequency band. By setting the wavelength to be less than 1/4 effective wavelength, it is possible to handle the signal line 1105 in a range where the electric influence of the plating stub 6 and the ball pad 7 does not affect as a lumped constant, and reduce the influence of impedance mismatch. be able to.

By reducing the impedance mismatch as described above, the distortion of the signal waveform on the package transmission line can be reduced, and the malfunction of the system can be eliminated.

In the first to sixth embodiments described above, BG
Although A has been described as an example, it is also applicable to all other array pad packages such as CSP. For example, in the case of CSP, the external pad 1409 (see FIG. 14) is the external electrode pad.

[0070]

As described above, according to the present invention, in a BGA or CSP package in which a semiconductor element is mounted, a uniform characteristic impedance is realized in the entire signal line on the package in a desired frequency range, or the characteristic impedance is By limiting the length range that does not cause a transmission problem even if there is a non-uniform portion, signal distortion in the package portion can be minimized.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a high-speed transmission compatible BGA according to a first embodiment of the present invention.

[Fig. 2] TD of signal line where electrical influence of ball pad and plating stub affects all lines by SPICE simulator
The figure which shows a R waveform estimation result.

FIG. 3 is a ball pad by a SPICE simulator,
The figure which shows the TDR waveform estimation result of the signal line which has the range where the electrical influence of a plating stub does not reach.

FIG. 4 is a diagram showing a relationship between tan β1 and β1 to β1.

FIG. 5 is a schematic plan view of a wiring pattern on the outermost surface of a high speed transmission compatible BGA according to a second embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a high speed transmission compatible BGA according to a second embodiment of the present invention.

FIG. 7 is a diagram showing the relationship between the input impedance and the wavelength at a point on the Z ₀ line when the load direction is observed when the load Z _L is connected to the line end of the characteristic impedance Z ₀ .

FIG. 8 is a schematic plan view of a wiring pattern on the outermost surface of a high speed transmission compatible BGA according to a third embodiment of the present invention.

FIG. 9 is a sectional configuration diagram of a high-speed transmission compatible BGA according to a fourth embodiment of the present invention.

FIG. 10 is a cross-sectional configuration diagram of a high speed transmission compatible BGA according to a fifth embodiment of the present invention.

FIG. 11 is a cross-sectional configuration diagram of a high speed transmission compatible BGA according to a sixth embodiment of the present invention.

FIG. 12 is a cross-sectional configuration diagram of a BGA compatible with high-speed transmission in a conventional example.

FIG. 13 is a diagram showing an example of a BGA surface layer wiring pattern corresponding to high-speed transmission in a conventional example.

FIG. 14 is a cross-sectional configuration diagram of a CSP compatible with high-speed transmission in a conventional example.

FIG. 15 is a diagram showing an example of a surface wiring pattern of a CSP compatible with high-speed transmission in a conventional example.

FIG. 16 is a signal line block diagram on a BGA including a plating stub.

FIG. 17 is a process drawing showing the method of forming solder balls.

[Explanation of symbols]

1 semiconductor element 2 wire 3 BGA base material 4 signal line 5 via 6 plating stub 7 ball pad 9 GND layer 10 power supply layer 53 BGA base material 54 signal wire 55 in the range affected by the plating stub 6 and ball pad 55 plating stub 6 , Signal line 83 in a range not affected by ball pad 7 BGA base material 84 plating stub 6, signal line in a range affected by ball pad 7 signal line 85 in a range not affected by plating stub 6, ball pad 7 86 Capacitive load 91 Semiconductor element 93 BGA base material 94 Signal line 95 in a range affected by the plating stub 6 and ball pad 7 Signal line 96 in a range not influenced by the plating stub 6 and ball pad 7 Within the semiconductor element 91 Formed capacitive load 1001 Semiconductor element 1003 BGA base material 1004 Plating stub 6, ball pad Signal line 1005 in the range of influence of the signal line 1006 of the plating stub 6 and the ball pad 7 Signal line 1006 in the range of no influence of the electrode pad 1103 formed on the semiconductor element 1001 BGA substrate 1104 Effect of the plating stub 6 and the ball pad 7 Signal line in the range 1105 Signal line in a range not affected by the plating stub 6 and ball pad 7

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-37201 (JP, A) JP-A-6-204357 (JP, A) JP-A-8-88294 (JP, A) JP-A-10- 214917 (JP, A) JP 10-308470 (JP, A) JP 10-326860 (JP, A) JP 11-214581 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/12

Claims (6)

(57) [Claims] 1. A semiconductor element having a plurality of electrode pads, and an external electrode on which the semiconductor element is mounted and which outputs or inputs electric signals, power, etc. from the electrode pad of the semiconductor element to the outside through conductor wiring. A semiconductor device having a base material provided with a pad, wherein the conductor wiring of the base material has a plating stub , wherein the plating stub and the external electrode pad are electrically connected to each other.
In order to be capacitive at the highest frequency of the signal,
Set the length of the plating stub and the shape of the external electrode pad.
The semiconductor device is characterized in that the characteristic impedance of the conductor wiring from the external electrode pad to the portion connected to the electrode pad of the semiconductor element is constant. 2. The semiconductor element from the external electrode pad
Of the conductor wiring up to the part connected to the electrode pad of
Due to the presence of plating stubs or external electrode pads
Exceeds the range in which the characteristic impedance of the conductor wiring changes
Set the wiring width of the part of the conductor wiring from the external electrode pad
Conductor layout up to the part that connects to the electrode pad of the semiconductor element
The wiring width is set so that the characteristic impedance is constant for all lines.
The semiconductor device according to claim 1, wherein: 3. The semiconductor element from the external electrode pad
Of the conductor wiring up to the part connected to the electrode pad of
Due to the presence of plating stubs or external electrode pads
Exceeds the range in which the characteristic impedance of the conductor wiring changes
The length of the conductor wiring of the part, the highest frequency that the electrical signal has
The same length as a multiple of one half of the effective wavelength
The characteristic impedance of the conductor wiring seen from the pole pad and
The presence of plating stubs or external electrode pads
Parts that exceed the range in which the characteristic impedance of body wiring changes
So that the characteristic impedance of the conductor wiring is the same
Load on the plating stub or external electrode pad.
The characteristic impedance of the conductor wiring changes depending on the presence
By forming it at the end of the conductor wiring that exceeds the range
From the external electrode pad to the electrode pad of the semiconductor element.
Characteristic impeder with all conductor wiring up to the part connected to the cable
2. The resistance is set to be constant.
The semiconductor device described. 4. The semiconductor element from the external electrode pad
Of until the portion where the electrode pads to connect conductor wiring, before
Due to the presence of plating stubs or external electrode pads
Exceeds the range in which the characteristic impedance of the conductor wiring changes
The length of the conductor wiring of the part, the highest frequency that the electrical signal has
The same length as a multiple of one half of the effective wavelength
The characteristic impedance of the conductor wiring seen from the pole pad and
The presence of plating stubs or external electrode pads
Parts that exceed the range in which the characteristic impedance of body wiring changes
So that the characteristic impedance of the conductor wiring is the same
By providing a load inside the semiconductor element,
From the external electrode pad to the electrode pad of the semiconductor element
Characteristic impedance of all conductor wiring up to the connection part
2. The method according to claim 1, characterized in that
Semiconductor device. 5. The semiconductor element from the external electrode pad
Of the conductor wiring up to the part connected to the electrode pad of
Due to the presence of plating stubs or external electrode pads
Exceeds the range in which the characteristic impedance of the conductor wiring changes
The length of the conductor wiring of the part, the highest frequency that the electrical signal has
The same length as a multiple of one half of the effective wavelength
The characteristic impedance of the conductor wiring seen from the pole pad and
The presence of plating stubs or external electrode pads
Parts that exceed the range in which the characteristic impedance of body wiring changes
So that the characteristic impedance of the conductor wiring is the same
Load to the electrode pad of the semiconductor element
The external electrode pad to the electrode of the semiconductor element.
Characteristic impedance can be obtained with all conductor wiring up to the part connected to the pad.
A claim characterized by making the dance constant
Item 1. The semiconductor device according to item 1. 6. A semiconductor element having a plurality of electrode pads, and an external electrode on which the semiconductor element is mounted and which outputs or inputs electric signals, electric power, etc. from the electrode pad of the semiconductor element to the outside through conductor wiring. A semiconductor device comprising a base material provided with a pad, wherein the conductor wiring of the base material has a plating stub, of the conductor wiring from the external electrode pad to a portion connected to the electrode pad of the semiconductor element , The length of the conductor wiring exceeds the range in which the characteristic impedance of the conductor wiring changes due to the presence of the plating stub or the external electrode pad, and there is a portion where the characteristic impedance is not uniform.
A semiconductor device characterized in that it has a length less than a quarter of the effective wavelength of the highest frequency of the electric signal , which is a length that does not cause a transmission problem even if present .