JPH0588912A - Multiprocessor simulator - Google Patents

Abstract

PURPOSE:To provide the multiprocessor simulator which selects an efficient communication network suitable for the number of processors and programs before system production and improves the efficiency of each processor. CONSTITUTION:A processor emulation means 22 executes the operation of a processor with one instruction cycle as the unit and measures various times of the execution state of the hardware level and the access state of each communication line. A memory management means 23 controls inter-processor communication based on a net list for the purpose of realizing the correspondence between a virtual storage 25 and a main storage 26. A parallelism analysis means 24 measures the execution time of the software level of each processor and operates the efficiency of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor simulator for simulating a program for operating a plurality of processors simultaneously.

[0002]

2. Description of the Related Art A program for operating a plurality of multiprocessors at the same time is usually created for a system in which the number of processors and the communication network between the processors are determined in advance. Therefore, the conventional multiprocessor simulator performs a simulation for confirming the correctness of the program created for each processor, and has a function for predicting the efficiency of the entire system including the communication network. There wasn't.

[0003]

Since the conventional multiprocessor simulator does not have the function of predicting the efficiency of the entire system including the communication network, it is suitable for the number of processors and programs before the system is manufactured. It was difficult to select an efficient communication network, and it was difficult to improve the efficiency of each processor.

The present invention has been made in view of the above circumstances, and an efficient communication network suitable for the number of processors and programs can be selected before the system is manufactured, and the efficiency of each processor can be improved. The purpose is to provide a multiprocessor simulator.

[0005]

According to the present invention, a processor emulation means for executing the operation of a processor in instruction cycle units and measuring various times of a hardware level execution state and an access state for each communication path, and a virtual memory. Memory management means for controlling the inter-processor communication based on the netlist and the parallelism analysis means for measuring the software-level execution time of each processor and computing the system efficiency. The feature is that it is provided.

[0006]

The processor emulation means executes the operation of the processor in instruction cycle units and measures various times of the hardware level execution state and the access state for each communication path. The memory management means associates the virtual memory with the main memory and controls the inter-processor communication based on the netlist. The parallelism analyzing means measures the software-level execution time of each processor and calculates the efficiency of the system.

[0007]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a parallel processing system design support apparatus including a multiprocessor simulator according to an embodiment of the present invention. The parallel processing system design support apparatus includes an input unit 1, a simulator 2, and a parallel processing program compile. It is composed of a device 3 and a multiprocessor simulator 4.

The input means 1 has an input function and a display function, and also has a function of automatically converting a graphic expression type language into a text type language advantageous for computer processing. The simulator 2 executes a parallel processing program converted into a text type language by the input means 1 based on an instruction of the designer input using the input means 1 to perform grammar check and the like, and to execute each process. Data necessary for function division by the parallel processing program compiling device 3 is generated by measuring the execution time and the like, and is displayed on the input means 1. Further, the simulator 2 executes a program for each processor whose function is divided by the parallel processing program compiling device 3 based on the instruction of the designer input using the input means 1 so that the operating time and synchronization of each processor are executed. By measuring the waiting time and the like, data necessary for determining the optimum number of processors and the coupling method by the parallel processing program compiling device 3 is generated and displayed on the input means 1.

The parallel processing program compiling device 3 is
Based on a designer's instruction input using the input means 1, a parallel processing program written in a text-type high-level language is compiled to generate an instruction code for operating a plurality of processors, and the optimum. The number of different processors and the coupling scheme between the processors. The multiprocessor simulator 4 executes the instruction code of each processor generated by the parallel processing program compiling device 3 based on the instruction of the designer input using the input means 1, and connects each processor and the coupling between the processors. The efficiency of the method is measured and displayed on the input means 1.

This parallel processing system design support device is realized by, for example, a workstation or a personal computer. FIG. 2 is a block diagram of the parallel processing program compiling device 3. The parallel processing program compiling device 3 is composed of a function dividing means 7, a number of processors / coupling method determining means 8, and an instruction code generating means 9. The function dividing means 7 is the non-recursive processing means 1
0, peeling processing means 11, and 1-loop processing means 12.

The function dividing means 7 divides the parallel processing program converted into the text type by the input means 1 into a program for each processor. The number-of-processors / coupling-method determining unit 8 determines the number of processors and the coupling method between the processors based on the division result of the function dividing unit 7, and generates a netlist.

The instruction code generating means 9 is a function dividing means 7.
The function-divided program is compiled to generate an instruction code for driving the processor. FIG. 3 is a block diagram of the simulator 2. The simulator 2 is composed of a command analysis unit 14, a lexical analysis unit 15, a syntax analysis unit 16, an execution unit 17, and a data generation unit 18, and the execution unit. 17 includes a switching means 19.

The command analysis means 14 analyzes the instruction from the designer supplied via the input means 1 and controls the simulation. The lexical analysis unit 15 reads the parallel processing program converted into the text type by the input unit 1 or the program whose function is divided by the function dividing unit 7 of the parallel processing program compiling device 3, decodes the lexical token, and checks spelling errors. To do.

The syntactic analysis means 16 receives the words from the lexical analysis means 15 and analyzes the grammar to check for grammatical errors. The execution unit 17 receives the analysis result from the syntax analysis unit 16 and performs various arithmetic processes according to the syntax. The data generation means 18 measures the processing time of the program, predicts the efficiency of the program, data for function division by the function division means 7 of the parallel processing program compiling device 3, or the number of processors of the parallel processing program compiling device 3. -Generates data for determining the number of processors and the coupling method by the coupling method determining means 8 and displays the result on the input means 1.

The switching means 19 waits for synchronization while the execution means 17 is executing an operation of a certain process, and when the continuation condition is not satisfied, saves the information of the process being executed and switches to the operation of another process. FIG. 4 is a configuration diagram of the multiprocessor simulator 4. The multiprocessor simulator 4 includes a scheduling unit 21, a processor emulation unit 22, a memory management unit 23, and a parallelism analysis unit 24.

The scheduling means 21 is an input means 1
Instructions generated by the instruction code generation means 9 of the parallel processing program compiling device 3 after determining the number of processors, the type of coupling method, the simulation order of the processors, etc., based on the designer's instruction input via The simulation is controlled by reading the code and the number of processors / net list generated by the coupling method determination means 8.

The processor emulation means 22 includes
Called by the scheduling means 21, the operation of the processor is executed in the unit of instruction cycle. During this period, various times of the hardware level execution state and the access state of each communication path are measured. The memory management means 23
Called by the processor emulation means 22, the virtual memory 25 of, for example, 4 Gbytes is associated with the main memory 26 of, for example, 4 Mbytes, and the interprocessor communication is controlled based on the netlist.

The parallelism analyzing means 24 is called by the scheduling means 21, measures the software-level execution time of each processor, calculates the efficiency of the system, and displays the result on the input means 1. Next, the operation will be described. First, an outline of a design method using the above parallel processing system design support device will be described.

The designer designs the parallel algorithm for each procedure which is a logical processing unit. At this time, the procedure does not necessarily have a one-to-one correspondence with the physical processor. Communication with the outside of the procedure is represented by an argument. Moreover, at this stage, the argument is treated exactly like any other variable, and synchronization regarding the specification of the argument and the assignment to the argument is completely unnecessary. With regard to the description of parallel processing, processing to be executed simultaneously is collectively described as one parallel execution statement.
In other words, a parallel algorithm that guarantees automatic synchronization until all the processing in one parallel execution statement is completed and that the values of all variables are updated at the execution end stage (hereinafter referred to as “synchronization parallel algorithm”). ")). This description level is referred to as PDL (Procedur
eDescription Level).

The parallel processing program compiling device 3 is
The processing for each processor is designed based on the PDL description simulated by the simulator 2. First, in consideration of parallelism, the synchronization parallel algorithm is functionally divided into a number of processes (procedures that are called in parallel execution statements and do not directly or indirectly include parallel execution statements). At this time, the portions that are sequentially executed are copied to each process as they are, and the parallel execution statements are distributed so that the processing time between the processes is as uniform as possible. Then, prepare a set of logical variables in advance, and combine a synchronization statement to stop processing until a certain condition is satisfied between parallel execution statements before splitting and an assignment statement to these logical variables. The communication message is generated to synchronize the processes. This series of processes is called a peeling process because it represents a process in which a large number of processes are stuck together and are forcibly peeled off so that separate procedures are performed. Then, only the procedure to be executed first is converted into a description including a parallel execution statement (hereinafter referred to as “parallel process”). That is, when the flow graph at the PDL description stage is as shown in FIG. 5, the flow graph after the peeling process is as shown in FIG. In this state, if the processing time between each process and the operating rate satisfy the design specifications, each process is assigned to one processor.
When the design specifications are not satisfied, particularly when there is a large difference in processing time between processes, the process is divided so that only one loop statement is included in the process, and a synchronization statement is generated. In this case, one loop statement is the number of loop statements in which one loop statement is not a structure (nested structure) that completely includes another loop statement. Therefore, when two loop statements form a nested structure, they are treated as one loop statement. Then, the ratio between the processes is calculated so that the processing times are equalized, and Berns is adjusted so as to be as close as possible to the ratio.
Divide the process using the condition of tain. The description level for each processor is set to SDL (Structure).
It is called a description level). If the design specifications are not clearly satisfied at this stage, PD
It is necessary to start over from the L design.

Further, the parallel processing program compiling device 3 is an S simulated by the simulator 2.
The communication state between the processors is determined based on the DL description, and all the processors that are frequently communicating are connected. Moreover, the processors are connected so that there is no processor (isolated processor) that cannot communicate with any of the processors that require communication, and this is used as a network.
Then, the SDL description is converted into a processor-specific instruction code. Further, the determined network is converted into a netlist including a set of logical numbers of the processors to be combined.
Further, a logical number list of processors to be directly or indirectly communicated with by each processor is generated from the netlist for each processor and added to the instruction code. In addition, in order for the processors not directly coupled in the network to communicate with each other, it is necessary to perform the communication via the third processor (indirect communication). Therefore, each processor needs to store candidates for the relay processor necessary for transferring data to all the other processors. At this stage, it is necessary to reexamine the design specifications and, if they are not satisfied, redesign. It is possible to change the network to a standard network if it is mild, but it is necessary to change the PDL design if it is severe.

Next, the details of the design method using the parallel processing system design support apparatus will be described. The designer inputs into the input means 1 a parallel program of PDL description written in a graphic representation high-level language. As a result, the input unit 1 converts the graphic representation type language into a text type language and stores it in a storage unit (not shown).

Next, the designer inputs to the input means 1 an instruction to simulate a parallel program. As a result, the lexical analysis means 15 of the simulator 2 sequentially reads out the parallel program a of PDL description from the storage means, cuts out words from the sentence, and extracts from the symbol table b stored in advance in the storage means, as shown in FIG. After finding the attribute corresponding to the symbol, the symbol and the attribute are output as a symbol / attribute list c. The symbol table b is created according to the type of programming language.

Next, the syntactic analysis means 16, as shown in FIG.
The symbol / attribute list c is received for each sentence from the lexical analysis unit 15, the type of sentence corresponding to the symbol / attribute list c is specified from the grammar rule table d stored in the storage unit in advance, and the syntax analysis table e is obtained. create. Grammar rule table d
Is created according to the type of programming language. Next, the execution means 17, as shown in FIG. 9, receives the syntax analysis table e from the syntax analysis means 16, finds the processing according to the analysis result from the execution function table f stored in the storage means in advance,
Run. At this time, the data required for the process is taken out from the process management table g stored in advance in the storage means, and the result is written in the corresponding part of the process management table g.

On the other hand, the data generating means 18 receives the syntactic analysis table e from the syntactic analyzing means 16 and creates the corresponding assembly code in the equivalent code table h as shown in FIG.
The execution time of the equivalent code is calculated with reference to the instruction code table i and the addressing mode table j stored in advance in the storage means, and the execution time is added to the time table k of the process currently being executed.

When the simulation is completed, the result is displayed on the input means 1. If the results meet the specifications,
Go to the next stage. If the specifications are not satisfied, redesign from the PDL description stage. Next, the designer inputs an instruction to convert the parallel program from the PDL description to the SDL description in the input means 1. As a result, the parallel processing program compiling device 3 sequentially reads the parallel program from the storage means based on the designer's instruction, and the function dividing means 7
The function is divided by. This function division is to convert the synchronization parallel algorithm expressed in the PDL description into the parallel process expressed in the SDL description, and includes the non-recursive process of the recursive process, the separation process, and the one-loop process. The details are described below. The definitions of terms used in the following description are shown in Tables 1 and 2 below.

[0027]

[Table 1]

[0028]

[Table 2]

The non-recursive processing means 10 converts a recursive process, which is a recursive procedure including parallel execution statements in a parallel program, into an ordinary recursive procedure. In other words, in the recursive process, processes are generated by the number of times the recursive call is executed, these processes are executed at the same time, and the number of processes that occur until execution is not fixed, which makes functional division difficult. Therefore, it is necessary to convert the recursive process into an ordinary recursive procedure in order to execute the function division. By the non-recursive processing of this recursive process, FIG.
The process model as shown in FIG. 1 (A) is converted into the process model as shown in FIG. 11 (B). Specifically, the following processes (1) and (2) are executed.

(1) When a procedure including a parallel execution statement is further called by a procedure called from the parallel execution statement, copy the procedure by changing the procedure name to A'for all the corresponding procedures A. , Replace parallel execution statements with sequential execution statements. (2) Replace the procedure names called from A to A'for all the procedures called in the parallel execution statement.

The peeling process means 11 performs a peeling process including a dividing process, a synchronization mechanism / communication protocol generating process, a divided set procedural process, and an inline expanding process. The division processing is performed by min- min so that each processing amount is equalized to a set of statements having the same number as the parallel execution statement having the largest execution statement.
The processing is divided based on the max principle. Specifically, the following processes (1) to (5) are performed.

(1) By the variable type division / synthesis processing, a conversion unit is generated before and after the subordinate parallel processing. (2) Divide all parallel execution statements (Formula 1 below) that constitute dependent parallel processing into a set (Formula 2 below) in units of one sentence,
This maximum number of elements m _i is the number of divided procedures. (3) Based on the min-max principle for the execution time of each statement, the set (Equation 2 below) is a set of m _i pieces (Equation 3 below).
Put together.

(4) Copy m _i execution units including the subordinate parallel processing, and embed the elements of the following expression 3 therein. (5) For each process, if a variable definition distributed to another process is used in the basic block in which embedding has occurred, an assignment statement for transmission / reception is generated.

[0034]

[Equation 1]

[0035]

[Equation 2]

[0036]

[Equation 3]

The generation process of the synchronization mechanism / communication protocol is
A communication protocol is generated for each set after division. Specifically, the following processes (1) to (3) are performed. (1) Variables are classified and all received / broadcast variables a ^k
Then, a synchronization variable f ^k is generated for the communication variable v ^k .
At this time, the number of elements on the receiving side and the transmitting side of the synchronization variable is adjusted to the number of procedures receiving and transmitting the variable.

(2) In accordance with the following rules (1) to (3), a synchronization mechanism and a communication protocol are generated at the receiving point, the broadcasting point, and the relay point, respectively. At this time, the positive logic or negative logic is unified, and the initial value is inserted once for each variable. Note that the receiving point refers to the location where the receiving variable is used in the parallel execution statement, the broadcasting point refers to the location where the broadcasting variable is used in the parallel execution statement, and the relay point is the relay variable on both sides of the assignment statement. The place to do.

If the receiving (broadcasting) point is in the execution statement of the control structure, the receiving (broadcasting) protocol is generated at the receiving (broadcasting) point. If it does not belong to the control structure, a reception (broadcast) protocol is generated if there is at least one reception (broadcast) point, and a synchronization mechanism is generated otherwise. Generate a relay protocol at the relay point.

There should be no difference in the change in the value of the synchronization variable depending on the presence or absence of the control structure. (3) Synchronization variable f End is generated and all other executable statements are sandwiched by the following expression 4.

[0041]

[Equation 4]

The procedural processing of the divided set is performed by dividing the divided set.
Create a procedure whose execution part is and call these procedures.
Generate one parallel statement to issue and place it as the original execution part.
It will be replaced. Specifically, the following (1) to (4)
Process. (1) Copy the generated communication variable. Also, each subdivided
Synchronization variable f of split set Variable names do not overlap in end replication
Sea urchin

(2) According to the following rules (1) to (3), a procedure declarative part having a divided set as an execution part is generated. At this time, the correspondence between variables and variable types is taken. The receive variables and the logical variables that appear in the synchronization statement are input variables. Broadcast variables and defined logical variables are output variables.

Regarding the relay variables,
After changing the variable names at the receiving point and the broadcasting point, they are used as input / output variables. The automatically generated variables are internal variables. (3) One parallel execution statement that calls all the generated procedures using the copied communication variable as an argument is generated. At this time, input / output arguments are generated corresponding to the input / output variables of each procedure declaration part.

(4) A synchronization variable f from each procedure is added to the generated parallel execution statement. The sequential execution statement in which the end determination statement of the following Expression 5 is added to end _i is replaced with the original execution unit.

[0046]

[Equation 5]

The inline expansion processing replaces the procedure call statement with the expanded execution unit for the procedure calling the procedure unless the procedure before expansion is the kernel. Specifically, the following procedures (1) to (5) are executed. The kernel is the procedure that is first executed. (1) Replace the procedure call statement with the execution part of the corresponding procedure.

(2) The internal variable included in the execution unit is renamed when the variable name is duplicated, and is defined as it is when the variable name is not duplicated. (3) If the variable type does not exist, the variable type is defined and then the variable is associated with the type. (4) The input / output variables included in the execution unit are replaced with the input / output arguments, and the changed internal variables are replaced with the changed names.

The kernel generated by the peeling process has a structure in which a plurality of parallel execution statements are sequentially executed. In the peeling process, the equalization of the processing amount for the processes is considered for each parallel execution statement. However, it does not consider the equalization of the processing amount for all processes called from the kernel. Therefore, by optimizing the processing amount of each of the generated parallel processes as a whole, an optimum system is obtained. Therefore, it is necessary to determine the number of executing processors of each process based on the ratio of the processing amount of the process between the parallel execution statements. There, it becomes necessary to divide the processing of each process into n. And this is possible when the procedure contains a loop statement. In order to be able to apply the division method focusing on this loop statement, it is necessary to make all procedures into one loop. This one-loop processing is realized by the following procedures (1) to (6).

(1) The execution part of the procedure including two or more loop statements is divided at the end part of the loop statement. (2) If there is a data dependency between the sets of divided sentences, the variable is stored. (3) According to the following rules (1) to (3), a procedure declarative part having a set of divided statements as an execution part is generated.

A variable having a data dependency is used as an input variable when it is used in the execution unit. A variable that has a data dependency is defined in the execution part as an output variable. For variables that have data dependencies that are used and defined in the execution part, separate the variable names into input / output variables. Furthermore, the variable names of the used part and the defined part of the execution part are replaced with the input / output variable names.

Variables having no data dependency are local variables. (4) The use / definition of the execution unit is regarded as the reception / broadcast point, and the synchronization mechanism / communication protocol is generated. (5) Synchronous variable f for each procedure end is generated and the execution unit is sandwiched by the following expression 4.

(6) Generate a procedure call statement that is divided into parts that call the original process. Next, the designer inputs to the input means 1 an instruction to simulate the program after the function division processing. As a result, the lexical analysis unit 15 of the simulator 2 sequentially reads the parallel program a from the storage unit as shown in FIG.
The word is cut out from the sentence, the attribute corresponding to the symbol is searched from the symbol table b, and then the symbol and the attribute are output as the symbol / attribute list c.

Next, the syntactic analysis means 16, as shown in FIG.
The symbol / attribute list c is received for each sentence from the lexical analysis unit 15, the type of sentence corresponding to the symbol / attribute list c is specified from the grammar rule table d, and the syntax analysis table e is created. Next, as shown in FIG. 9, the execution means 17 receives the syntax analysis table e from the syntax analysis means 16, finds the processing according to the analysis result from the execution function table f, and executes it. At this time,
The data required for processing is taken out from the processing management table g, and the result is written in the corresponding location of the processing management table g. Further, the execution means 17 activates the switching means 19 if the sentence of the syntax analysis table e received from the syntax analysis means 16 is a wait statement.

As a result, the switching means 19 refers to the condition part of the syntax analysis table e as shown in FIG. 12, and the condition is T (Tru).
If it is e), the process is continued without doing anything. The condition is F (F
If “alse”, the current state is entered in the process management table m, the time wheel n is advanced by one step to obtain the process name to be executed next, and the process is switched to the program to be executed according to the process management table m.

That is, as shown in FIG. 13, the i-th process is executed (step S1), and it is determined whether or not it is waiting for synchronization (step S2). If it is waiting for synchronization, it is determined whether or not the condition for continuing processing is not satisfied. (Step S3), if not established, the i-th process is saved (step S4), and i is set to 1
To i (step S5), the i-th process is called (step S6), and the process returns to step S1. If the synchronization is not waited in step S2, the process returns to step S1. If the condition is not satisfied in step S3, the process returns to step S1.

On the other hand, the data generating means 18 receives the syntactic analysis table e from the syntactic analyzing means 16 and creates the corresponding assembly code in the equivalent code table h as shown in FIG.
The execution time and the synchronization waiting time of the equivalent code are calculated with reference to the instruction code table i and the addressing mode table j stored in advance in the storage means, and the execution time is shown in the time table k of the process currently being executed. And synchronization waiting time are added separately.

When the simulation is completed, the result is displayed on the input means 1. If the results meet the specifications,
Go to the next stage. If the specifications are not satisfied, redesign from the PDL description stage. Next, the designer determines the number of processors and the coupling method between the processors in the input means 1 and inputs an instruction to generate an instruction code for operating the processors. As a result, the number-of-processors / coupling method determining unit 8 of the parallel processing program compiling apparatus 3 refers to the data generated by the data generating unit 18 of the simulator 2 and determines the number of processors and the coupling method between the processors. Generate a relay processor list.

The determination of the coupling method is performed by the following procedures (1) to (3). (1) A set of all processors (p a ⁱ , p a ^j )
The binding force is calculated with respect to and the binding force matrix F = (F ^ij ) is obtained. Here, the cohesion is the amount of communication between processes,
It can be determined by the size of the variable and the number of transmissions and receptions during the process execution. In the present embodiment, the following equation 6 is used as the binding force function. This function can be regarded as an amount proportional to the amount of information that the process communicates during execution.

[0060]

[Equation 6]

(2) Histograms of all the elements of the obtained binding force matrix F are taken. (3) When the histogram is divided into several distributions, a set of processors belonging to the distribution is directly connected as a network in order from the distribution with the largest binding force to create a netlist. At this time, the distribution is adopted until there is no isolated processor that is not directly or indirectly coupled to any of the processors that need communication.
If the distribution is not divided, all processors belonging to this distribution are directly connected as a network to create a netlist.

By determining the coupling method in this way, by relaying a small communication amount between processes without directly coupling, it is possible to suppress an increase in the communication circuit and to increase the communication amount. By directly connecting objects, communication overhead associated with relaying can be reduced. When the network is determined by the above procedure, communication between the processors is possible for the time being, but this is merely a line connection. That is, there is a set of processors that cannot directly communicate with each other unless all the processors are connected to each other. The processors cannot communicate with each other without passing through a third party. However, information as to which processor it is possible to communicate with has not yet been determined. Therefore, it is necessary to determine this information. This can be determined given the netlist. This problem is known as the problem of determining the shortest path between two given points.
The solution methods such as the kstra) method are famous. In this example,
Since the communication route is determined using the Dijkstra method,
A detailed description of the algorithm is omitted. As the information for communicating with a processor other than itself, a list of processors to communicate directly with in order to communicate with that processor may be stored. Further, even if there are a plurality of shortest routes, there is no problem, and if all of them are stored, it becomes possible to prevent only a specific communication path from becoming congested.

The parallel processing program compiling device 3
The instruction code generation means 9 of 1 compiles the program whose functions have been divided by the function division means 7 to generate an instruction code for operating the processor. Next, the designer attaches the parallel processing program compiling device 3 to the input means 1.
An instruction to perform simulation is input using the instruction code and the netlist generated by. This causes the multiprocessor simulator 4 to perform a simulation. The multiprocessor simulator 4 is shown in FIG.
Like (A) shared memory type, (B) tree structure type, (C) array type, (D) torus type, (E)
It is possible to realize a typical network such as the hypercube type, and to compare the network performance.

The scheduling means 21 uses the number of processors, the type of network, and
After determining the processor simulation order and the like, the code generation means 9 of the parallel processing program compiling device 3 is executed.
The generated code and the net list determined by the number of processors / connection method determination means 8 are read to control the simulation. That is, as shown in FIG. 15, at the time of initialization, the communication network information and the initial value data are passed to the memory management means 23, and the execution order of the processors is set in the time wheel p. Then, at the time of simulation, the processor number of the executing processor of the time wheel p is passed to the processor emulation means 22, and the pointer of the time wheel p is advanced by one.

The processor emulation means 22 is
Called by the scheduling means 21, the operation of the target processor is executed in the unit of instruction cycle. During this time, the hardware-level execution state (during operation, instruction call, local memory read / write / call wait / write wait, shared memory call / write,
It measures the time of call waiting, write waiting, I / O call / write / call waiting / write wait) and the access status (call / write / call wait / write wait) of each communication path. That is, as shown in FIG. 16, the instruction code, that is, the program q written in the assembly language is executed. For example, the memory management means 2 is read by reading mov a, do and outputting the address for a.
The data data (a) from 3 is received. Since the instruction is mov, the data data (a) is assigned to do in the register file of the processor data file r, and then the pointer is advanced by one. At the same time, the time required for each cycle is entered in the time information section in the processor data file r with reference to the instruction cycle time table s.

The memory management means 23 is called from the processor emulation means 22, and establishes a correspondence between the virtual space or virtual memory 25 and the physical space or main memory 26. At the same time, it controls communication between the processors via the network via the I / O space. That is, as shown in FIG. 17, at the time of initial setting, the configuration information of the communication network is received by the scheduling means 21, and the attribute indicating the processor accessible to each port is set to set the communication network t. This port can be accessed by only one set of processors set in the attribute, and communication can be performed by this. When the simulation is started, the memory management means 23 returns the corresponding data to the processor emulation means 22 according to the processor number and address designated by the processor. Note that u is processor data and v is shared data.

The parallelism analyzing means 24 is called by the scheduling means 21 and measures the time relating to the software level execution state of each processor. That is, in the multiprocessor simulator 4, ten system variables are prepared for each processor, and by setting these variables, the time during which the variables are set can be independently measured. .. The designer can measure the execution time of an arbitrary process by using this variable. Pr out of 10 system variables
b0 to prb2 are reserved by the system, and measure the time during processing execution, communication, and standby, respectively.
While the process is being executed, it is the time when the processor is executing its assigned work, while during the communication, it is the time when the data necessary for the process is being sent or received or is being relayed to another processor, and is waiting. The inside is just waiting time without doing anything. Measurement is performed for each system variable, and the measured results are totaled together with the hardware level results and output as a data file.

When the simulation is completed, the result is displayed on the input means 1. If the results meet the specifications,
Finish the design. If the specifications are not satisfied, redesign from the PDL description stage. If the communication efficiency cannot be satisfied, the efficiency is compared with the existing network as shown in FIGS. 14A to 14E, and if the existing network satisfies the specifications, it is adopted.

[0069] parallel processor for executing parallel processing program developed by the above procedure, for example as shown in FIG. 18, a plurality of processors 29 ₀ ~29 _n-1 having a local memory 28 ₀ ~28 _n-1 It is connected by a communication network and communicates with a plurality of other processors 29 _{0 to} 29 _n-1 via a communication path. The communication network includes a data bus 30 and bi-directional memory blocks 31 _{0 to} 3 _{0 to} 3 according to a netlist showing the coupling state of the processors 29 _{0 to} 29 _n-1.
A general-purpose switch 32 that switches the correspondence with 1 _n-1 and a network controller 33 that controls the general-purpose switch 32.
Consists of. The communication is performed by a plurality of processors 29 that can be combined.
_This is performed by writing in a plurality of bidirectional memory blocks 31 _{0 to} 31 _n-1 accessible only to _{0 to} 29 _n-1 .
In addition, this communication network includes all the processors 29 _{0 to} 29
_{The n-1} has the accessible shared memory 34, and the processors 29 _{0 to} 29 _n-1 can communicate with each other through the shared memory 34. It is assumed that the exclusive control at the hardware level in the communication between the processors 29 _{0 to} 29 _n-1 is automatically performed, and in terms of software, each of the processors 29 _{0 to} 29 _n-1 is a non-divided read / write. It is assumed that the cycle has a tas (Test and Set) instruction. FIG. 19 is an overall configuration diagram of a memory space (virtual space). The memory space is roughly divided into three parts (local memory space, shared memory space, I / O space). The local memory space is an area that can be accessed only by the corresponding processors 29 _{0 to} 29 _n−1 .
It exists for each of the processors 29 _{0 to} 29 _n-1 . Local memory space is further (may not be present depending on the processor 29 ₀ ~29 _n-1) Processor 29 ₀ ~29 _n-1 unique exception vector area, become PE binding information unit, from the user area. The shared memory space is an area accessible by all the processors 29 _{0 to} 29 _n−1 ,
Exclusive control is performed by the network controller 33, and only one processor 29 _{0 to} 29 _n-1 can access at the same time. The I / O space consists of many memory blocks, and each block can be accessed only by a specific set of processors. The exclusive control is performed by the network controller 33 in accordance with a net list indicating the connection state of the processors 29 _{0 to} 29 _n-1 . This area can be accessed simultaneously for each block. PE
The (processor) connection information section exists in the local memory space, and as shown in FIG. 20, the processors 29 _{0 to} 29 _n-1.
, A network type, a network parameter, the number of a processor with which the processor can communicate directly via I / O, its I / O address, and the like are stored. The user area is the processor 29 ₀ as shown in FIG.
To 29 only the area and the processor 29 ₀ through 29 _n-1 to _n-1 stores a program to be executed is composed of the area for storing data to be accessed. Since the exception vector area differs depending on the processors 29 _{0 to} 29 _n-1 , description of its structure is omitted. The I / O space is made up of 1 block of 16 bytes as shown in FIG. 22, through which a set of processors can communicate. One block further includes an attribute area, a transmission / reception buffer, and a spare area. Areas accessible by the processors 29 _{0 to} 29 _n-1 are a transmission / reception buffer and a spare area, and an attribute area is accessible only by the network controller 33.

Specific operations of the main operation of the parallel processing program compiling apparatus will be described below. (Specific Example 1) The non-recursive process of the recursive process will be described by using the non-recursive process of IntGauss (), which is a procedure for obtaining an indefinite integral value including a Gaussian function shown in Expression 7 below.

[0071]

[Equation 7]

The indefinite integral value G _m is divided into two cases as shown in the following equation 8 depending on whether _m is an even number or an odd number.

[0073]

[Equation 8]

Here, the value of the above expression 8 is the following expression 9 to expression 11
Can be calculated by

[0075]

[Equation 9]

[0076]

[Equation 10]

[0077]

[Equation 11]

The procedure for obtaining the value of G _m is IntGaus.
s (), IntEGauss a procedure for determining the value of E _n
(), IntOGauss a procedure for determining the value of O _n
(), IntIOGau procedures for obtaining the integral value of O _n
If ss (), the program becomes as shown in FIGS. The shaded portion in FIG. 24 is a parallel execution statement.
In the procedure IntEGauss (), the procedure Int
OGauss () and procedure IntIOGauss
() Is a process because it is called in the parallel execution statement. Further, since the procedure IntOGauss () calls the procedure IntEGauss (), the procedure IntEGauss () is a recursive procedure. Therefore, the procedure IntEGauss () is a recursive process.

The non-recursive process for the recursive process is performed based on the following principles (1) and (2). (1) A procedure A ′ is newly generated in which the parallel execution statements of the recursive process A are sequentially executed statements. (2) For the procedure called from the recursive process A, all the procedure names that call the recursive process A are changed to A '.

That is, the procedure Int after the non-recursive processing
EGaus () is as shown in FIG. FIG. 28 shows the newly generated procedure IntEGGauss1 (), and FIG. 29 shows the modified procedure IntOGauss ().
Shown in. 29. In FIG. 29, the shaded portion shows the changed portion. (Specific Example 2) Regarding the processing from function division to network determination, a procedure c for executing a butterfly operation in the fast Fourier transform as in the program of FIG. 30.
A description will be given using alc. In this example, there is no recursive process, and all procedures are in one loop, so it is not necessary to perform the non-recursive process and the one-loop process of the recursive process, and therefore the description thereof is omitted.

(1) Division processing A flow graph as shown in FIG. 31 is obtained from the program shown in FIG. This flow graph section represents each executable statement,
A plurality of branches, that is, a part surrounded by a broken line represents parallel execution. As a result of the division processing, a flow graph as shown in FIG. 32 is obtained. (2) Synchronous mechanism / communication protocol generation process The variable classification result for the procedure calc by the variable classification process is as shown in FIG. Variables yre, yim,
xre and xim are independent variables in this procedure, but the procedure cfft calling the procedure calc
Since both are variables zre and zim in the inside, both are treated as the same variable. Therefore, the variable yr
e, yim, xre, and xim are relay variables. Then, based on the classification result, a synchronization variable is generated for all variables other than the isolated variable and used as communication variables. The communication variables obtained in this way are shown in FIG. The processing execution part of the program after the generation processing of the synchronization mechanism / communication protocol is shown in FIGS. 35 to 38, the shaded portion represents the synchronization mechanism / communication protocol generated by the separation processing means 11 of the function dividing means 7 of the parallel processing program compiling device 3.

(3) Procedural processing and inline expansion processing of non-divided set After the generation of the synchronization mechanism / communication protocol, a procedure having this set as a process execution unit is generated. Then, inline expansion processing is executed for this procedure calc. (4) Network determination In order to obtain the cohesive force distribution necessary for network determination, the simulator 2 performs simulation again. The binding force matrix obtained as a result of the simulation is shown in FIG.
9 and the binding force distribution created thereby is shown in FIG. In FIG. 39, P0 is management of the entire system, P1 to P7 are trigonometric table creation, P8 to P11 are butterfly operations, and P12 to P14 are bit reverse operations. From this binding force distribution, the binding force is 8 or more (*
The set of processors (indicated by the mark) is directly connected to form a network. The resulting network is shown in graphical form in FIG. The nodes of this graph represent processors, and the solid line branches represent communication paths.
Moreover, the broken line branch indicates that communication is performed although not directly coupled, that is, that a third processor is required for communication between these.

In the above embodiment, when determining the range in which the processors are directly coupled, the maximum coupling force with which all the processors that need communication are directly or indirectly coupled is used as a standard. The binding force may be configured so that the designer can set a smaller value by using the input means 1. Further, in the above embodiment, the one-loop processing is always executed, but the one-loop processing may be executed only when the designer gives an instruction using the input means 1.

[0084]

As described above, according to the present invention, the processor emulation means for executing the operation of the processor in the unit of instruction cycle and measuring various times of the execution state at the hardware level and the access state for each communication path. , A memory management means for associating a virtual memory with a main memory and controlling communication between processors based on a netlist, and a parallelism analysis for measuring a software level execution time of each processor and calculating a system efficiency Since the means is provided, it is possible to realize a simulation for an arbitrary number of processors and communication networks, and it is possible to select an efficient number of processors and communication networks suitable for a program before the system is manufactured. In addition, the efficiency of each processor can be predicted before the system is manufactured, and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a parallel processing system design support apparatus including a multiprocessor simulator according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a parallel processing program compiling device.

FIG. 3 is a configuration diagram of a simulator.

FIG. 4 is a configuration diagram of a multiprocessor simulator.

FIG. 5 is a flow graph of a process model by PDL description.

FIG. 6 is a flow graph of a process model after peeling processing.

FIG. 7 is an operation explanatory diagram of lexical analysis means.

FIG. 8 is an operation explanatory diagram of the syntax analysis unit.

FIG. 9 is a diagram for explaining the operation of the executing means.

FIG. 10 is a diagram illustrating the operation of the data generating means.

FIG. 11 is a flow graph of a process model before and after non-recursive processing.

FIG. 12 is a diagram for explaining the operation of the switching means.

FIG. 13 is a flowchart for explaining the operation of the switching means.

FIG. 14 is a configuration diagram of a network that can be realized by a multiprocessor simulator.

FIG. 15 is a diagram for explaining the operation of the scheduler means.

FIG. 16 is an operation explanatory diagram of a processor emulation means.

FIG. 17 is a diagram for explaining the operation of the scheduler means.

FIG. 18 is a configuration diagram of an actual model of a parallel processing processor.

FIG. 19 is a configuration diagram of a virtual space.

FIG. 20 is a configuration diagram of a PE connection information part.

FIG. 21 is a configuration diagram of a user area.

FIG. 22 is a configuration diagram of an I / O space.

FIG. 23 is an explanatory diagram of a program in PDL description.

FIG. 24 is an explanatory diagram of a program in PDL description.

FIG. 25 is an explanatory diagram of a program in PDL description.

FIG. 26 is an explanatory diagram of a program in PDL description.

FIG. 27 is an explanatory diagram of a program after the non-recursive process.

FIG. 28 is an explanatory diagram of a program after non-recursive processing.

FIG. 29 is an explanatory diagram of a program after the non-recursive process.

FIG. 30 is an explanatory diagram of a program in PDL description.

FIG. 31 is a flow graph of a process model based on PDL description.

FIG. 32 is a flow graph of a process model after division processing.

FIG. 33 is an explanatory diagram of a variable classification result.

FIG. 34 is an explanatory diagram of communication variables.

FIG. 35 is an explanatory diagram of a program in which a synchronization mechanism / communication protocol is embedded.

FIG. 36 is an explanatory diagram of a program in which a synchronization mechanism / communication protocol is embedded.

FIG. 37 is an explanatory diagram of a program in which a synchronization mechanism / communication protocol is embedded.

FIG. 38 is an explanatory diagram of a program in which a synchronization mechanism / communication protocol is embedded.

FIG. 39 is an explanatory diagram of a binding force matrix.

FIG. 40 is an explanatory diagram of a bond strength distribution.

FIG. 41 is an explanatory diagram of a network.

[Explanation of symbols]

 22 processor emulation means 23 memory management means 24 parallelism analysis means 25 virtual memory 26 main memory

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location G06F 15/16 430 9190-5L 15/20 D 7218-5L

Claims (1)

[Claims] 1. Correspondence between a virtual memory and a main memory, and a processor emulation means for executing an operation of a processor in an instruction cycle unit and measuring various times of a hardware level execution state and an access state for each communication path. In addition, a memory management means for controlling inter-processor communication based on the netlist and a parallelism analysis means for measuring the software level execution time of each processor and computing the system efficiency are provided. Processor simulator.