JP2927583B2 - Parallel processing programming simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing programming simulator for simulating a parallel processing program in a high-level language capable of describing parallel execution.

[0002]

2. Description of the Related Art Conventional simulators verify the correctness of a program and cannot predict the efficiency of the program.

[0003]

Since the conventional simulator could not predict the efficiency of the program, an efficient program was developed for compiling a parallel processing program in a high-level language capable of describing parallel execution. It was difficult to do. The present invention has been made in view of such circumstances, and provides a parallel processing programming simulator capable of developing an efficient program when compiling a parallel processing program in a high-level language capable of describing parallel execution. With the goal.

[0004]

SUMMARY OF THE INVENTION The present invention provides a lexical analysis means for detecting a spelling error by reading a parallel processing program in a high-level language including a parallel execution statement that summarizes processes to be executed simultaneously and decoding the lexical data. Syntactic analysis means for receiving a word from the lexical analysis means and analyzing the grammar to detect a grammatical error; execution means for performing various arithmetic processing according to the syntax received from the syntax analysis means; Data generating means for measuring the processing time by the means and estimating the efficiency of the parallel processing program.

[0005]

The lexical analysis means detects a spelling error by reading a parallel processing program in a high-level language including a parallel execution statement that summarizes processes to be executed simultaneously and decoding the lexical data. The syntax analyzer detects a grammatical error by receiving a word from the lexical analyzer and analyzing the grammar. The execution means performs various arithmetic processes according to the syntax received from the syntax analysis means. The data generation unit estimates the efficiency of the parallel processing program by measuring the processing time by the execution unit.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram of a parallel processing system design support apparatus having a parallel processing programming simulator according to an embodiment of the present invention. The parallel processing system design support apparatus includes an input unit 1, a simulator 2, a parallel processing program It comprises a compiling device 3 and a multiprocessor simulator 4.

The input means 1 has an input function and a display function, and also has a function of automatically converting a graphic expression type language into a text type language advantageous for computer processing. The simulator 2 executes a parallel processing program converted into a text type language by the input unit 1 based on a designer's instruction input using the input unit 1 to perform a grammar check and the like, and to execute each process. By measuring the execution time and the like, data necessary for function division by the parallel processing program compiling device 3 is generated and displayed on the input means 1. Further, the simulator 2 executes a program for each processor, the functions of which are divided by the parallel processing program compiling device 3, based on a designer's instruction input by using the input means 1, and operates and synchronizes each processor. By measuring the waiting time and the like, data necessary for determining the optimal number of processors and the coupling method by the parallel processing program compiling device 3 is generated and displayed on the input means 1.

The parallel processing program compiling device 3
Based on a designer's instruction input using the input means 1, a parallel processing program described in a text-type high-level language is compiled to generate an instruction code for operating a plurality of processors, and Determine the number of processors and the coupling method between processors. The multiprocessor simulator 4 executes an instruction code for each processor generated by the parallel processing program compiling device 3 based on a designer's instruction input using the input means 1, and connects each processor and the connection between processors. The efficiency of the system is measured and displayed on the input means 1.

This parallel processing system design support apparatus is realized by, for example, a workstation or a personal computer. FIG. 2 is a configuration diagram of the parallel processing program compiling device 3. The parallel processing program compiling device 3 includes a function dividing means 7, a number-of-processors / coupling-method determining means 8, and an instruction code generating means 9. , The function dividing means 7 includes the non-recursive processing means 1
0, separation processing means 11, and one loop processing means 12.

The function dividing means 7 divides the parallel processing program converted into a text type by the input means 1 into a program for each processor. The number-of-processors / connection-method determining means 8 determines the number of processors and the connection method between the processors based on the division result of the function dividing means 7, and generates a netlist.

The instruction code generating means 9 includes a function dividing means 7
To generate an instruction code for driving the processor by compiling the program divided into functions. FIG. 3 is a configuration diagram of the simulator 2. The simulator 2 includes a command analysis unit 14, a lexical analysis unit 15, a syntax analysis unit 16, an execution unit 17, and a data generation unit 18. 17 is provided with switching means 19.

The command analyzing means 14 analyzes instructions supplied from the designer through the input means 1 and controls the simulation. The lexical analysis means 15 reads the parallel processing program converted into the text type by the input means 1 or the program divided by the function dividing means 7 of the parallel processing program compiling device 3 and decodes the lexical characters to check spelling errors. I do.

The syntactic analysis means 16 receives the word from the lexical analysis means 15, analyzes the grammar, and checks for grammatical errors. The execution unit 17 receives the analysis result from the syntax analysis unit 16 and performs various arithmetic processes according to the syntax. The data generating means 18 measures the processing time of the program and the like, predicts the efficiency of the program, and predicts the efficiency of the program. The data for function division by the function dividing means 7 of the parallel processing program compiling apparatus 3 or the number of processors of the parallel processing program compiling apparatus 3 Generate data for determining the number of processors and the connection method by the connection method determining means 8 and display the result on the input means 1.

The switching means 19 waits for synchronization while the execution means 17 is executing an operation of a certain process, and when the continuation condition is not satisfied, saves the information of the process being executed and switches to an operation of another process. FIG. 4 is a configuration diagram of the multiprocessor simulator 4. The multiprocessor simulator 4 includes a scheduling unit 21, a processor emulation unit 22, a memory management unit 23, and a parallelism analysis unit 24.

The scheduling means 21 includes the input means 1
After determining the number of processors, the type of coupling method, the simulation order of the processors, and the like based on the designer's instruction input through the command line, the instruction generated by the instruction code generation means 9 of the parallel processing program compiling device 3 The simulation is controlled by reading the code and the netlist generated by the number-of-processors / coupling-method determining means 8.

The processor emulation means 22 comprises:
Called by the scheduling means 21, the operation of the processor is executed in instruction cycle units. During this time, various times of the execution state at the hardware level and the access state for each communication path are measured. The memory management means 23
It is called by the processor emulation means 22 to establish correspondence between the virtual memory 25 of, for example, 4 Gbytes and the main memory 26 of, for example, 4 Mbytes, and to control the inter-processor communication based on the netlist.

The parallelism analyzing means 24 is called by the scheduling means 21, measures the execution time of each processor at the software level, calculates the efficiency of the system, and displays the result on the input means 1. Next, the operation will be described. First, an outline of a design method using the parallel processing system design support device will be described.

A designer designs a parallel algorithm for each procedure which is a logical processing unit. At this time, the procedure does not always correspond one-to-one with the physical processor. Communication with the outside of the procedure is represented by an argument. Moreover, at this stage, the arguments are treated exactly like the other variables, and there is no need to synchronize the specification of the arguments or the assignment to the arguments. Concerning the description of the parallel processing, the processing to be executed simultaneously is collectively described as one parallel execution statement.
In other words, a parallel algorithm (hereinafter referred to as a “synchronous parallel algorithm”) that is automatically synchronized until all the processing in one parallel executable statement is completed and that the values of all variables are updated at the end of execution. "). This description level is hereinafter referred to as PDL (Procedur
eDescription Level).

The parallel processing program compiling device 3 comprises:
Based on the PDL description simulated by the simulator 2, processing for each processor is designed. First, in consideration of parallelism, the function of the synchronization parallel algorithm is divided into a possible number of processes (procedures called in parallel execution statements and not directly or indirectly including parallel execution statements). At this time, the sequentially executed portion is copied to each process as it is, and the parallel execution statements are distributed so that the processing time between the processes becomes as uniform as possible. Then, prepare a set of Boolean variables in advance, and combine a synchronization statement to stop processing until a condition between parallel execution statements is satisfied before splitting and an assignment statement to these Boolean variables. A message is generated to synchronize the processes. A series of these processes is referred to as a peeling process because a process in which a large number of processes are stuck together is forcibly peeled off so that separate procedures are performed. Then, only the procedure to be executed first is converted into a description including a parallel execution statement (hereinafter referred to as a “parallel process”). That is, when the flow graph at the stage of the PDL description is as shown in FIG. 5, the flow graph after the peeling process is as shown in FIG. In this state, if the processing time and operation rate between the processes satisfy the design specifications, each process is assigned to one processor.
If the design specifications are not satisfied, especially if there is a large difference in the processing time between the processes, the process is divided so as to include only one loop statement, and a synchronous statement is generated. In this case, one loop statement is the number of loop statements in which a certain loop statement does not completely include another loop statement (nested structure). Therefore, if two loop statements form a nested structure, they are treated as one loop statement. Then, a ratio between the processes is calculated so that the processing time is equalized, and Berns is determined so as to be as close as possible to the ratio.
The process is divided using the tein condition. The description level for each processor is set to SDL (Structure).
This is referred to as “Description Level”. If the design specifications are not clearly satisfied at this stage, PD
It is necessary to start over from the L design.

Further, the parallel processing program compiling device 3 executes S
The communication state between the processors is determined based on the DL description, and all processors that frequently communicate are connected. In addition, the processors are connected so that there is no processor (isolated processor) that cannot communicate with any of the processors requiring communication, and this is used as a network.
Then, the SDL description is converted into an instruction code unique to the processor. Further, the determined network is converted into a netlist including a set of logical numbers of the processors to be connected.
Further, from the net list, a logical number list of the processors with which each processor should communicate directly or indirectly is generated for each processor, and added to the instruction code. Note that in order for processors that are not directly coupled in the network to communicate with each other, it is necessary to perform communication via the third processor (indirect communication). For this purpose, each processor needs to store a candidate for a relay processor necessary for transferring data to all other processors. At this stage, the design specifications are examined again, and if they are not satisfied, it is necessary to redo the design. The network can be changed to a standard network if the network is mild, but the PDL design needs to be changed if the network is severe.

Next, details of a design method using the parallel processing system design support apparatus will be described. The designer inputs a parallel program of PDL description described in a graphic expression type high-level language to the input unit 1. Thereby, the input unit 1 converts the graphic expression type language into the text type language and stores it in the storage unit (not shown).

Next, the designer inputs to the input means 1 an instruction to simulate the parallel program. As a result, the lexical analysis means 15 of the simulator 2 sequentially reads out the parallel program a of the PDL description from the storage means as shown in FIG. 7, cuts out words from the sentence, and extracts the words from the symbol table b stored in the storage means in advance. After searching for the attribute corresponding to the symbol, the symbol and the attribute are output as a symbol / attribute list c. The symbol table b is created according to the type of the programming language.

Next, the syntactic analysis means 16, as shown in FIG.
The symbol / attribute list c is received in units of one sentence from the lexical analysis means 15, the type of the sentence corresponding to the symbol / attribute list c is specified from the grammar rule table d stored in advance in the storage means, and the syntax analysis table e is obtained. create. Grammar rule table d
Are created according to the type of programming language. Next, as shown in FIG. 9, the execution unit 17 receives the syntax analysis table e from the syntax analysis unit 16 and searches for a process according to the analysis result from the execution function table f stored in the storage unit in advance.
Execute. At this time, data necessary for the processing is extracted from the processing management table g stored in the storage means in advance, and the result is written in a corresponding location of the processing management table g.

On the other hand, as shown in FIG. 10, the data generation means 18 receives the syntax analysis table e from the syntax analysis means 16 and creates a corresponding assembly code in an equivalent code table h.
The execution time of the equivalent code is calculated with reference to the instruction code table i and the addressing mode table j stored in the storage means in advance, and the execution time is added to the time table k of the currently executing process.

When the simulation is completed, the result is displayed on the input means 1. If the result satisfies the specification,
Proceed to the next stage. If the specifications are not satisfied, the design is started again from the stage of PDL description. Next, the designer inputs an instruction to convert the parallel program from the PDL description to the SDL description into the input unit 1. Thereby, the parallel processing program compiling device 3 sequentially reads out the parallel programs from the storage means based on the instruction of the designer, and
Divides functions. This function division converts a synchronization parallel algorithm represented by a PDL description into a parallel process represented by an SDL description, and includes a non-recursive process of a recursive process, a stripping process, and a one-loop process. The details will be described below. The definitions of terms used in the following description are shown in Tables 1 and 2 below.

[0026]

[Table 1]

[0027]

[Table 2]

The non-recursive processing means 10 converts a recursive process which is a recursive procedure including a parallel execution statement in a parallel program into a normal recursive procedure. That is, in the recursive process, processes for the number of times recursive calls are executed are generated, and these processes are executed simultaneously. Since the number of processes that occur until execution is not determined, it becomes difficult to divide functions. Therefore, when performing the function division, it is necessary to convert the recursive process into an ordinary recursive procedure. By the non-recursive processing of this recursive process, FIG.
A process model as shown in FIG. 1A is converted into a process model as shown in FIG. Specifically, the following processes (1) and (2) are executed.

(1) When a procedure including a parallel execution statement is further called by a procedure called from the parallel execution statement, the procedure name is changed to A 'for all the corresponding procedures A, and the procedure is duplicated. , Replaces the parallel executable statements with the sequential executable statements. (2) For all procedures called in the parallel execution statement, replace the calling procedure names from A to A '.

The peeling processing means 11 performs a peeling process including a dividing process, a process of generating a synchronization mechanism / communication protocol, a procedure for processing a set to be divided, and an inline expansion process. The division processing is performed such that each processing amount is equalized to a set of statements of the same number as the number of parallel execution statements having the largest execution statement.
The process is divided based on the max principle. Specifically, the following processes (1) to (5) are performed.

(1) A conversion unit is generated before and after dependent parallel processing by variable type division / synthesis processing. (2) All parallel execution statements (formula 1 below) constituting the dependent parallel processing are divided into sets (formula 2 below) in units of one statement,
The maximum number of elements m _i and the split procedure number. (3) On the basis of the min-max principle for the execution time of each sentence, a set (the following equation 2) is divided into _mi sets (the following equation 3)
Put together.

[0032] (4) an execution unit contained Dependent Parallel Processing and m _i pieces copy, embed the following elements: number 3 therein. (5) For each process, if a variable definition distributed to another process is used in the embedded basic block, an assignment statement for transmission and reception is generated.

[0033]

(Equation 1)

[0034]

(Equation 2)

[0035]

(Equation 3)

The processing for generating the synchronization mechanism and communication protocol is as follows.
A communication protocol is generated for each of the divided sets. Specifically, the following processes (1) to (3) are performed. (1) Variables are classified and all received / broadcast variables a ^k
, A synchronization variable f ^k is generated and set as a communication variable v ^k .
At this time, the number of elements on the receiving side and the transmitting side of the synchronization variable is adjusted to the number of procedures for receiving and transmitting the variable.

(2) According to the following rules, a synchronization mechanism and a communication protocol are generated at the receiving point, the broadcasting point, and the relay point, respectively. At this time, positive logic or negative logic is used, and the initial value is inserted once for each variable. Note that the receiving point refers to the place where the received variable is used in the parallel executable statement, the broadcast point refers to the place where the broadcast variable is used in the parallel executable statement, and the relay point refers to the place where the relay variable exists on both sides of the assignment statement. A place to do.

If the reception (broadcast) point is in the execution statement of the control structure, a reception (broadcast) protocol is generated at the reception (broadcast) point. If it does not belong to the control structure, it generates a reception (broadcast) protocol if there is at least one reception (broadcast) point, and generates a synchronization mechanism otherwise. Generate a relay protocol at the relay point.

Change in value of synchronization variable depending on presence or absence of control structure
There must be no difference. (3) Synchronous variable f generate end and execute all other
The sentence is sandwiched by Equation 4 below.

[0040]

(Equation 4)

The procedural processing of the divided set is performed by dividing the divided set
Generate procedures that have
Generate one parallel executable statement and place it in the original executable.
It is something to replace. Specifically, the following (1) to (4)
Is performed. (1) Duplicate the generated communication variables. Also, each share
Synchronous variable f of split set Duplicate end, variable names do not overlap
Sea urchin.

(2) In accordance with the following rules (1) to (4), a procedure declaration section in which the divided set is an execution section is generated. At this time, the correspondence between the variable and the variable type is taken. Those that are received variables and logical variables that appear in the synchronization statement are input variables. Those that are broadcast variables and defined logical variables are output variables.

For the relay variables,
After the variable names at the receiving point and the broadcasting point are changed, they are set as input / output variables. Automatically generated variables are internal variables. (3) Using the duplicated communication variables as arguments, generate one parallel executable statement that calls all generated procedures. At this time, input / output arguments are generated corresponding to the input / output variables of each procedure declaration section.

(4) A synchronization variable f from each procedure is added to the generated parallel execution statement. The sequential execution statement in which the end judgment statement of the following expression 5 is added to end _i is replaced with the original execution unit.

[0045]

(Equation 5)

In the inline expansion process, if the procedure before expansion is not a kernel, the procedure calling statement is replaced with the execution unit after expansion for the procedure calling the procedure. Specifically, the following procedures (1) to (5) are executed. The kernel is a procedure that is executed first. (1) Replace the procedure call statement with the execution part of the corresponding procedure.

(2) The internal variables included in the execution unit are renamed when the variable names are duplicated, and are defined as they are when the variable names are not duplicated. (3) If the type of the variable does not exist, define the variable type and then associate the variable with the type. (4) The input / output variables included in the execution unit are replaced with input / output arguments, and the changed internal variables are replaced with the changed names.

The kernel generated by the stripping process has a structure in which a plurality of parallel executable statements are sequentially executed. In the stripping process, equalization of the processing amount for each parallel execution statement is considered. However, no consideration is given to equalizing the processing amount for all processes called from the kernel. Therefore, by equalizing the processing amount of each process as a whole of the generated parallel processes, an optimal system is obtained. Therefore, it is necessary to determine the number of execution processors of each process based on the ratio of the processing amount of the process between the parallel execution statements. In this case, it is necessary to divide the processing of each process into n. This is possible when the procedure contains a loop statement. In order to be able to apply the division method focusing on this loop statement, it is necessary to make all the procedures into one loop. This one-loop processing is realized by the following procedures (1) to (6).

(1) The execution part of a procedure including two or more loop statements is divided at the end of the loop statement. (2) If there is a data dependency between the set of divided sentences, the variable is stored. (3) According to the following rules (1) to (4), a procedure declaration section is generated in which a set of divided statements is an execution section.

Variables having a data dependency are used in the execution unit as input variables. Variables for which data dependence exists are defined in the execution unit as output variables. If a variable having a data dependency is used or defined in the execution unit, the variable name is separated and used as an input / output variable. Further, the variable names at the used and defined locations of the execution unit are replaced with input / output variable names.

Variables having no data dependency are local variables. (4) Synchronization mechanism / communication protocol is generated by regarding the use / definition places of the execution unit as reception / broadcast points, respectively. (5) Synchronous variable f for each procedure end is generated, and the execution unit is inserted by the following equation (4).

(6) Generate a procedure call sentence divided into places where the original process is called. Next, the designer inputs to the input means 1 an instruction to simulate the program after the function division processing. Thereby, the lexical analysis means 15 of the simulator 2 sequentially reads the parallel program a from the storage means as shown in FIG.
After extracting a word from the text and searching for an attribute corresponding to the symbol from the symbol table b, the symbol and the attribute are output as a symbol / attribute list c.

Next, as shown in FIG.
The symbol / attribute list c is received in units of one sentence from the lexical analysis unit 15, the type of the sentence corresponding to the symbol / attribute list c is specified from the grammar rule table d, and a syntax analysis table e is created. Next, as shown in FIG. 9, the execution means 17 receives the syntax analysis table e from the syntax analysis means 16, finds out a process according to the analysis result from the execution function table f, and executes it. At this time,
The data necessary for the processing is extracted from the processing management table g, and the result is written in the corresponding part of the processing management table g. The execution unit 17 activates the switching unit 19 if the sentence of the syntax analysis table e received from the syntax analysis unit 16 is a wait sentence.

As a result, the switching unit 19 refers to the condition part of the syntax analysis table e as shown in FIG.
If e), the processing is continued without doing anything. If the condition is F (F
If (alse), the current state is written in the process management table m, and then the time wheel n is advanced by one step to obtain a process name to be executed next, and is switched to a program to be executed according to the process management table m.

That is, as shown in FIG. 13, the i-th process is executed (step S1), and it is determined whether or not the synchronization is awaited (step S2). Is determined (step S3), and if not satisfied, the i-th process is saved (step S4), and 1 is set to i.
Is added to i (step S5), the i-th process is called (step S6), and the process returns to step S1. If the synchronization is not waiting in step S2, the process returns to step S1. If the condition is not satisfied in step S3, the process returns to step S1.

On the other hand, as shown in FIG. 10, the data generation means 18 receives the syntax analysis table e from the syntax analysis means 16 and creates a corresponding assembly code in the equivalent code table h.
The execution time and the synchronization waiting time of the equivalent code are calculated with reference to the instruction code table i and the addressing mode table j stored in the storage means in advance, and the execution time is stored in the time table k of the currently executing process. And the synchronization wait time.

When the simulation is completed, the result is displayed on the input means 1. If the result satisfies the specification,
Proceed to the next stage. If the specifications are not satisfied, the design is started again from the stage of PDL description. Next, the designer determines the number of processors and the coupling method between the processors into the input means 1 and inputs an instruction to generate an instruction code for operating the processors. Thereby, the number-of-processors / coupling-method determining means 8 of the parallel processing program compiling device 3 refers to the data generated by the data generating means 18 of the simulator 2 to determine the number of processors and the coupling method between the processors, Generate a relay processor list.

The determination of the connection method is performed according to the following procedures (1) to (3). (1) All processor sets (p a ⁱ , p a ^j )
Is calculated, and a bonding force matrix F = (F ^ij ) is obtained. Here, the binding force is the communication amount between processes,
It can be determined by the size of the variable and the number of transmissions and receptions during the execution of the process. This function can be considered to be an amount proportional to the amount of information communicated during the execution of the process.

[0059]

(Equation 6)

(2) A histogram is obtained for all the elements of the obtained coupling force matrix F. (3) When the histogram is divided into several distributions, a set of processors belonging to the distribution is directly connected as a network in order from a distribution having a large coupling force to create a netlist. At this time, the distribution is adopted until there is no isolated processor that is not directly or indirectly coupled to any of the processors requiring communication.
If the distribution is not divided, all the processors belonging to this distribution are directly connected as a network to create a netlist.

By determining the coupling method in this manner, by relaying a small communication amount between processes without directly coupling, it is possible to suppress an increase in the number of communication circuits and to increase the communication amount. By directly linking them, communication overhead associated with relaying can be reduced. When the network is determined by the above procedure, communication between the processors is possible for the time being, but this is merely a connection of the lines. That is, there is a set of processors that cannot communicate directly except when all processors are connected to each other. The processors cannot communicate with each other without going through a third party. However, information as to which processor can communicate with has not been determined yet. Therefore, this information needs to be determined. This can be determined given the netlist. This problem is known as the problem of determining the shortest path between two given points, and is called Dijkstra (Dij
Solving methods such as the kstra method are famous. In this embodiment,
Since the communication route is determined using the Dijkstra method,
Detailed description of the algorithm is omitted. As information for communicating with other processors, a list of processors to be directly communicated with in order to communicate with that processor may be stored. In addition, there may be a plurality of shortest paths, and if all of the shortest paths are stored, it is possible to prevent a specific communication path from being congested.

The parallel processing program compiling device 3
Instruction code generation means 9 compiles the program divided by the function division means 7 and generates an instruction code for operating the processor. Next, the designer inputs the parallel processing program compiling device 3 to the input means 1.
Is input using the instruction code and the netlist generated by the above. Thereby, the multiprocessor simulator 4 performs a simulation. The multiprocessor simulator 4 is shown in FIG.
(A), shared memory type (A), tree structure type (B), array type (C), torus type (D), and (E)
It is possible to realize a representative network such as a hypercube type (hypercube type), and to compare network performances.

The scheduling means 21 determines the number of processors, the type of network,
After determining the simulation order of the processor, the code generation means 9 of the parallel processing program compiling device 3
Reads the generated code and the netlist determined by the number-of-processors / coupling-method determining means 8, and controls the simulation. That is, as shown in FIG. 15, at the time of initialization, the communication network information and the initial value data are passed to the memory management means 23, and the execution order of the processor is set on the time wheel p. At the time of simulation, the processor number of the execution processor of the time wheel p is passed to the processor emulation means 22, and the pointer of the time wheel p is advanced by one.

The processor emulation means 22 comprises:
Called by the scheduling means 21, the operation of the target processor is executed in instruction cycle units. During this time, the hardware-level execution status (calculation, instruction call, local memory read / write / call wait / write wait, shared memory call / write,
The times of call waiting, writing wait, I / O call / write / call wait / write wait) and the access state (call / write / call wait / write wait) for each communication path are measured. That is, as shown in FIG. 16, an instruction code, that is, a program q written in an assembly language is executed. For example, mov a, do is read, an address for a is output, and the memory management unit 2 is read.
3 receives data data (a). Then, since the instruction is mov, after assigning data data (a) to do in the register file of the processor data file r, the pointer is advanced by one. At the same time, the time required for each cycle is entered in the time information section in the processor data file r with reference to the instruction cycle time table s.

The memory management means 23 is called from the processor emulation means 22 and makes correspondence between the virtual space, that is, the virtual memory 25, and the physical space, that is, the main memory 26. At the same time, communication between processors by a network is controlled via the I / O space. That is, as shown in FIG. 17, at the time of initialization, the communication network form information is received by the scheduling means 21 and an attribute indicating a processor that can access each port is set to set the communication network t. This port can be accessed only by a set of processors set in the attribute, thereby enabling communication. When the simulation is started, the memory management unit 23 returns corresponding data to the processor emulation unit 22 according to the processor number and address specified by the processor. Note that u is processor data and v is shared data.

The parallelism analyzing means 24 is called by the scheduling means 21 and measures the time relating to the software-level execution state of each processor. That is, in the multiprocessor simulator 4, ten system variables are prepared for each processor, and by setting these variables, the time during which the variables are set can be measured independently. . The designer can measure the execution time of an arbitrary process by using this variable. Of the 10 system variables, pr
b0 to prb2 are reserved in the system and measure the time during processing, during communication, and during standby, respectively.
During processing, it is the time during which the processor is performing its assigned task, and during communication, it is the time during which data required for processing is transmitted or received or relayed to another processor. Inside is the time just waiting without doing anything. Measurement is performed for each system variable, and the measured results are totaled together with the results at the hardware level and output as a data file.

When the simulation is completed, the result is displayed on the input means 1. If the result satisfies the specification,
Finish the design. If the specifications are not satisfied, the design is started again from the stage of PDL description. If the communication efficiency is not satisfactory, the efficiency is compared with the existing network as shown in FIGS. 14A to 14E, and if the existing network satisfies the specifications, it is adopted.

As shown in FIG. 18, for example, as shown in FIG. 18, a plurality of processors 29 _{0 to} 29 _n-1 having local memories 28 _{0 to} 28 _n-1 execute the parallel processing program developed by the above procedure. It is connected by a communication network and communicates with a plurality of other processors 29 _{0 to} 29 _n-1 via a communication path. The communication network communicates with the data bus 30 and the bidirectional memory blocks 31 _{0 to} 3 ₀ by using a netlist indicating a connection state between the plurality of processors 29 _{0 to} 29 _n-1.
1 _n-1 and a network controller 33 for controlling the general-purpose switch 32
Consists of Communication is through a plurality of processors 29 that can be combined.
_This is performed by writing a plurality of bidirectional memory blocks 31 _{0 to} 31 _{n−1 that} can be accessed only by _{0 to} 29 _n−1 .
This communication network also includes all the processors 29 _{0 to} 29
_n-1 has an accessible shared memory 34, and the processors 29 _{0 to} 29 _n-1 can communicate with each other via the shared memory 34. The exclusive control at the hardware level in the communication between the processors 29 _{0 to} 29 _n-1 is assumed to be automatically performed. Further, in terms of software, each of the processors 29 _{0 to} 29 _n-1 performs undivided read / write. It is assumed that a cycle tas (Test Set) instruction is provided. FIG. 19 is an overall configuration diagram of a memory space (virtual space). The memory space is roughly divided into three parts (local memory space, shared memory space, and I / O space). The local memory space is an area that can be accessed only by the corresponding processors 29 _{0 to} 29 _n−1 ,
It exists for each of the processors 29 _{0 to} 29 _n-1 . Local memory space is further (may not be present depending on the processor 29 ₀ ~29 _n-1) Processor 29 ₀ ~29 _n-1 unique exception vector area, become PE binding information unit, from the user area. The shared memory space is an area that can be accessed by all processors 29 _{0 to} 29 _n−1 ,
Exclusively controlled by the network controller 33, only one processor 29 _{0 to} 29 _n-1 can access at the same time. The I / O space consists of a number of memory blocks, each block being accessible only by a particular set of processors. The exclusive control is performed by the network controller 33 in accordance with the net list indicating the connection state of the processors 29 _{0 to} 29 _n-1 . This area can be accessed simultaneously for each block. PE
(Processor) The connection information section exists in the local memory space, and as shown in FIG. 20, the processors 29 _{0 to} 29 _n-1.
, The network type, network parameters, the number of the processor with which the processor can directly communicate via I / O, the I / O address thereof, and the like. The user area includes a processor 29 ₀ as shown in FIG.
To 29 _n−1, and an area for storing data accessed only by the processors 29 _{0 to} 29 _n−1 . Since the exception vector area differs depending on each of the processors 29 _{0 to} 29 _n−1 , the description of the structure is omitted. The I / O space is made up of 16 bytes per block as shown in FIG. 22, through which a set of processors can communicate. One block further includes an attribute area, a transmission / reception buffer, and a spare area. The areas accessible by the processors 29 _{0 to} 29 _n−1 are the transmission / reception buffer and the spare area, and the attribute area is accessible only by the network controller 33.

Hereinafter, a specific operation of the main operation of the parallel processing program compiling apparatus will be described. (Specific Embodiment 1) The non-recursive processing of the recursive process will be described using the non-recursive processing of the procedure IntGauss () for obtaining an indefinite integral value including a Gaussian function shown in the following Expression 7.

[0070]

(Equation 7)

The indefinite integral value G _m is divided into two cases as shown in the following Expression 8 according to the even and odd numbers of m.

[0072]

(Equation 8)

Here, the value of the above equation 8 is obtained by the following equations 9 to 11
Can be calculated by

[0074]

(Equation 9)

[0075]

(Equation 10)

[0076]

[Equation 11]

The procedure for finding the value of G _m is IntGauss
s (), IntEGauss a procedure for determining the value of E _n
(), IntOGauss a procedure for determining the value of O _n
(), IntIOGau procedures for obtaining the integral value of O _n
If ss () is used, the program is as shown in FIGS. The shaded portion in FIG. 24 is a parallel execution statement.
In the procedure IntEGauss (), the procedure Int
OGauss () and Procedure IntIOGauss
() Is a process because it is called in a parallel execution statement. Furthermore, since procedure IntOGas () calls procedure IntEGauss (), procedure IntEGauss () is a recursive procedure. Therefore, the procedure IntEGauss () is a recursive process.

The non-recursive processing for the recursive process is performed based on the following principles (1) and (2). (1) A procedure A ′ is newly generated in which parallel execution statements of the recursive process A are sequentially executed. (2) For the procedure called from the recursive process A, change all the procedure names that call the recursive process A to A '.

That is, procedure Int after non-recursive processing
EGauss () is as shown in FIG. FIG. 28 shows a newly generated procedure IntEGauss1 (), and FIG. 29 shows a modified procedure IntOGasus ().
Shown in In FIG. 29, the shaded portion indicates a changed portion. (Embodiment 2) A procedure c for executing a butterfly operation in fast Fourier transform as shown in the program of FIG.
Explanation will be given using alc. In this example, there is no recursive process, and all the procedures are formed into one loop, so that it is not necessary to perform the non-recursive process and the one-loop process of the recursive process, and a description thereof will be omitted.

(1) Dividing Process A flow graph as shown in FIG. 31 is obtained from the program of FIG. The sections of this flow graph represent each executable statement,
A plurality of branches, that is, a portion surrounded by a broken line indicates parallel execution. As a result of performing the division processing, a flow graph as shown in FIG. 32 is obtained. (2) Synchronization Mechanism / Communication Protocol Generation Processing The variable classification result for the procedure calc by the variable classification processing is as shown in FIG. The variables ire, yim,
xre and xim are independent variables in this procedure, but the procedure cfft calling the procedure calc
Since both are variables zre and zim, they are treated as the same variable. Therefore, the variable yr
e, yim, xre, and xim are relay variables. Subsequently, synchronization variables are generated for all variables other than the isolated variables based on the classification result, and are used as communication variables. FIG. 34 shows the communication variables thus obtained. FIGS. 35 to 38 show processing execution portions of the program after the synchronization mechanism / communication protocol generation processing. In FIGS. 35 to 38, the shaded portion indicates the synchronization mechanism / communication protocol generated by the separation processing means 11 of the function dividing means 7 of the parallel processing program compiling device 3.

(3) Non-partitioned set procedural processing and inline expansion processing After the generation of the synchronization mechanism and the communication protocol, a procedure is generated in which this set is used as a processing execution unit. Then, an inline expansion process is executed for this procedure calc. (4) Determination of Network In order to obtain a binding force distribution required for determining a network, simulation is performed again by the simulator 2. Fig. 3 shows the binding force matrix obtained as a result of the simulation.
9 and FIG. 40 shows the resulting bonding force distribution. In FIG. 39, P0 is management of the entire system, P1 to P7 are trigonometric function tables, P8 to P11 are butterfly operations, and P12 to P14 are bit reverse operations. From this bonding force distribution, a bonding force of 8 or more (* in FIG. 39)
The set of processors (net) of (marked part) are directly connected to each other to form a network. The resulting network is shown in graphical form in FIG. The nodes of this graph represent processors, and the solid-line branches represent communication paths.
The broken-line branch indicates that communication is being performed although not directly connected, that is, communication between them requires a third processor.

In the above embodiment, when determining the range in which the processors are directly coupled to each other, the maximum coupling power in which all the processors that need communication are directly or indirectly coupled is used as a reference. The coupling force may be configured so that the designer can set a smaller value by using the input means 1. In the above embodiment, the one-loop processing is always executed. However, the one-loop processing may be executed only when the designer gives an instruction using the input unit 1.

[0083]

As described above, according to the present invention, a spelling error is detected by reading a parallel processing program in a high-level language including a parallel execution statement that summarizes processes to be executed at the same time and decoding the lexical data. Lexical analysis means, syntax analysis means for receiving a word from the lexical analysis means and analyzing the grammar to detect a grammatical error, and execution means for performing various arithmetic processing according to the syntax received from the syntax analysis means. And a data generation unit that measures the processing time of the execution unit and predicts the efficiency of the parallel processing program. Therefore, it is possible to verify the correctness of the parallel processing program and predict the efficiency at the same time. This has an excellent effect that the efficiency of the program can be evenly developed and an efficient program can be developed as the whole system.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a parallel processing system design support apparatus including a parallel processing programming simulator according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a parallel processing program compiling device.

FIG. 3 is a configuration diagram of a simulator.

FIG. 4 is a configuration diagram of a multiprocessor simulator.

FIG. 5 is a flow graph of a process model based on a PDL description.

FIG. 6 is a flow graph of a process model after a peeling process.

FIG. 7 is an explanatory diagram of the operation of the lexical analyzer.

FIG. 8 is an explanatory diagram of the operation of the syntax analysis means.

FIG. 9 is an explanatory diagram of the operation of the execution means.

FIG. 10 is an explanatory diagram of the operation of the data generation means.

FIG. 11 is a flow graph of a process model before and after non-recursive processing.

FIG. 12 is an explanatory diagram of the operation of the switching means.

FIG. 13 is a flowchart for explaining the operation of the switching means.

FIG. 14 is a configuration diagram of a network that can be realized by a multiprocessor simulator.

FIG. 15 is an explanatory diagram of the operation of the scheduling means.

FIG. 16 is an explanatory diagram of the operation of the processor emulation means.

FIG. 17 is an explanatory diagram of the operation of the scheduling means.

FIG. 18 is a configuration diagram of a real model of a parallel processing processor.

FIG. 19 is a configuration diagram of a virtual space.

FIG. 20 is a configuration diagram of a PE combination information unit.

FIG. 21 is a configuration diagram of a user area.

FIG. 22 is a configuration diagram of an I / O space.

FIG. 23 is an explanatory diagram of a program in PDL description.

FIG. 24 is an explanatory diagram of a program in PDL description.

FIG. 25 is an explanatory diagram of a program in PDL description.

FIG. 26 is an explanatory diagram of a program in PDL description.

FIG. 27 is an explanatory diagram of a program after non-recursive processing.

FIG. 28 is an explanatory diagram of a program after non-recursive processing.

FIG. 29 is an explanatory diagram of a program after non-recursive processing.

FIG. 30 is an explanatory diagram of a program in PDL description.

FIG. 31 is a flow graph of a process model based on a PDL description.

FIG. 32 is a flow graph of a process model after division processing.

FIG. 33 is an explanatory diagram of a variable classification result.

FIG. 34 is an explanatory diagram of communication variables.

FIG. 35 is an explanatory diagram of a program in which a synchronization mechanism and a communication protocol are embedded.

FIG. 36 is an explanatory diagram of a program in which a synchronization mechanism and a communication protocol are embedded.

FIG. 37 is an explanatory diagram of a program in which a synchronization mechanism and a communication protocol are embedded.

FIG. 38 is an explanatory diagram of a program in which a synchronization mechanism and a communication protocol are embedded.

FIG. 39 is an explanatory diagram of a coupling force matrix.

FIG. 40 is an explanatory diagram of a bonding force distribution.

FIG. 41 is an explanatory diagram of a network.

[Explanation of symbols]

 15 lexical analysis means 16 syntax analysis means 17 execution means 18 data generation means

Claims (1)

(57) [Claims] 1. A lexical analysis means for detecting a spelling error by reading a parallel processing program in a high-level language including a parallel execution statement that summarizes processes to be executed at the same time and decoding the lexical data. And a parsing means for detecting a grammatical error by analyzing the grammar, executing means for performing various arithmetic operations according to the syntax received from the parsing means, and measuring a processing time by the executing means. A parallel processing programming simulator, comprising: a data generation means for predicting the efficiency of the parallel processing program.