JPH05304603A - Picture signal processor - Google Patents

Abstract

PURPOSE:To increase the processing speed of a picture signal processing circuit which corrects a shading distortion, and to prevent the increase of cost by simplifying circuit constitution. CONSTITUTION:At the time of an initial setting, data Bn indicating a black reference level, and data Xn indicating a difference between the black reference level and a white reference level are stored in a RAM 27. At the time of the correcting processing of the shading distortion, the data Bn are subtracted from data Dn obtained from a picture signal outputted by a line sensor which reads an object by an adder/subtracter 15. Then, the subtracted data Sn are multiplied by data Yn read from an ROM 22 by a multiplier 20, and the multiplied data Mn are applied to a RAM 25 as address data. The data Yn stored in the ROM 22 are made to correspond to the data Xn as 1/Xn, and then the data Mn are obtained as Dn-Bn/Xn. Thus, the correcting processing of the shading distortion can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus for subjecting an image signal obtained from an image pickup device to signal processing such as shading correction and gamma correction.

[0002]

2. Description of the Related Art In an image reading apparatus such as a facsimile or an image reader, an object is read by a line sensor which scans in one direction to obtain a continuous image signal line by line. In this case, due to the characteristics of the optical system that forms a subject image on the light receiving surface of the line sensor, the amount of light at both ends of the line sensor decreases, and so-called shading distortion occurs in which the white level of the image signal decreases toward the end. For example, as shown in FIG. 6, the white level of the output of the line sensor approaches the black level side as it approaches both ends, and the output voltage V ₂ at the end of the line sensor is lower than the output voltage V ₁ at the center of the line sensor. Since this becomes low, it becomes necessary to correct this distortion in the process of processing the image signal.

FIG. 7 shows the output (image signal) of the line sensor.
3 is a block diagram showing the configuration of a correction circuit that corrects the shading distortion of FIG. The A / D converter 1 converts an analog-valued image signal into digital data and outputs it as image data. The reference control circuit 2 that supplies the reference voltages V _RH and V _RL to the A / D converter 1 is between the voltages V _PH and V _PL indicating the maximum level and the minimum level of the image signal supplied from the peak hold circuit 3. , The illumination voltages V _RH and V _RL are changed based on the correction data corresponding to the shading distortion of the image signal so that the white level of the image signal shows a constant value in one line. Here, the correction data is supplied from the RAM 4 that stores the output data of the A / D converter 1 for one line.
The image data for one line when the line sensor reads a subject serving as a white level reference is stored as correction data. Therefore, the reference control circuit 2
_Reduces the difference between the reference voltages V _RH and V _RL with respect to the image signal of each line from the central portion toward the end portion so that A from the white level to the black level at the central portion and the end portion. / D
The number of conversion steps of the converter 1 is made equal. As a result, the shading distortion included in the analog value is corrected during the conversion operation of the A / D converter 1.

[0004]

However, the A / D
When the reference voltages V _RH and V _RL of the converter 1 are changed in accordance with the correction data, if the reference voltages V _RH and V _RL have an error due to the change of the power supply voltage or the temperature characteristics of the elements forming the circuit, The conversion accuracy of the A / D converter 1 is impaired, and shading distortion cannot be sufficiently corrected. Therefore, a correction circuit for compensating the conversion accuracy of the A / D converter 1 is required, but it is extremely difficult to accurately respond to various changing conditions depending on the environment in which the device is used.

It has also been considered to correct shading distortion by subjecting image data after A / D conversion to predetermined arithmetic processing. If the shading distortion is corrected by processing the digital data, it will be less affected by fluctuations in the power supply voltage and stable operation can be expected, but addition and multiplication of the correction data and the image data can be performed in many steps. Since it needs to be executed, it takes a long time for calculation processing and is not suitable for high-speed operation.

Therefore, an object of the present invention is to correct shading distortion by digital signal processing and to enable high-speed signal processing.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that the image signal for each line obtained from an image sensor is bit-wise In a processing device for correcting a signal level according to, a first data indicating a first reference level is stored, and a second data indicating a difference between a second reference level and a first reference level is stored. Memory, a first arithmetic circuit for subtracting the first data from the input image data, a second memory for storing multiplier data associated with the second data, and the second data. And a second arithmetic circuit that multiplies the image data from which the first data has been subtracted by the multiplication data read corresponding to the above.

[0008]

According to the present invention, the data of the first reference level and the data of the difference between the first reference level and the second reference level are stored, and these data are sequentially read and given to the arithmetic circuit. Necessary arithmetic processing can be completed by executing addition and multiplication once. Therefore, the time required for the arithmetic processing can be shortened and high-speed operation can be supported.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an image signal processing apparatus of the present invention for performing correction processing on an image signal. The A register 11 and the B register 12 are the selector 1
Image data for 1 bit given from 3 and 14 is taken in and output at predetermined timings. The output of the A register 11 is given to one input of the adder / subtractor 15, and the output of the B register 12 is given to the other input of the adder / subtractor 15 through the selector 16. On the other hand, the selector 13 receives data from the data bus 17 and the address bus 18 and supplies either one to the A register 11, and the selector 14 further performs A / D conversion for digitally converting the data from the address bus 18 and the image signal. The output data (image data) of the container 10 is received and either is given to the B register 12 or the address bus 18. Then, the output of the adder / subtractor 15 is once taken into the C register 19, and a selector for selecting whether to output to the data bus 17 and the address bus 18 from this C register 19 or to give it to one input of the multiplier 20. 21 is input. Multiplier 20
Is an RO that receives address data from the address bus 18.
The output data of M22 is received by the other input, and the output is given to the D register 23. The output of the multiplier 20 is given to the selector 16 from the D register 23 and also given to the first RAM 25 through the selector 24. Further, the address bus 18 is connected to an address generating circuit 26 having a counter structure for generating address data and a second RAM 27 for storing the data in units of one line, and stores the data sent to the address bus 19. The address data is provided to the ROM 22 and the selectors 13 and 24 at a desired timing.

In the above-mentioned signal processing device, an initial setting operation for writing the correction data in the RAM 27 is performed before the shading distortion is actually corrected. Figure 2
FIG. 6 is a timing diagram illustrating the initial setting operation.
Here, the operation clock of the A / D converter 10 is set to a cycle twice as long as the system clock. First, the line sensor is used to read the subject document that is the reference for the black level, and the average of one line of the image signal or an appropriate number of lines is A
The image data Bn (n = n) is input to the / D converter 10.
1, 2, 3, ...) as black correction data for the selector 1
4 to the address bus 18 and write to the RAM 27. As a result, black correction data is set in the RAM 27. After that, the subject original serving as the reference of the white level is read, and the image data Wn obtained in the same manner is selected by the selector 1
4 to B register 12. At the same time RAM2
Data Bn is read from 7 and given to the A register 11 from the address bus 18 through the selector 13. And
The data Bn and the data Wn are given from the respective registers 11 and 12 to the adder / subtractor 15, the data Xn obtained by subtracting the data Bn from the data Wn is taken into the C register 19, and this data Xn is taken as the white correction data by the selector 21.
From the address bus 19 to write to the RAM 27. As a result, white correction data is set in the RAM 27. Therefore, the black correction data and the white correction data for correcting the shading distortion are stored in the RAM 27 so as to correspond to one line of the image data.

After the above initializing operation is completed, the shading distortion is corrected by subjecting the image data to a predetermined arithmetic processing with the correction data stored in the ROM 27. FIG. 3 is a timing chart for explaining a calculation processing operation for correcting shading distortion. The image signal obtained from the line sensor that reads the subject is digital data Dn (n = n) by the A / D converter 10.
1, 2, 3, ...), and the selector 14 selects B.
It is given to the register 12. At the same time, RAM27
The data Bn is read from the register B and given to the A register 11, and the data Bn and the data D are read from the registers 11 and 12.
n is input to the adder / subtractor 15. The adder / subtractor 15 subtracts the data Bn from the data Dn and gives the data Sn representing the difference to the C register 19. Further, in the RAM 27, after the data Bn is read, the data Xn is read at the subsequent timing, and the ROM 2 is read as the address data.
Given to 2. The ROM 22 stores the data Yn obtained by multiplying the reciprocal of the data Xn by a constant coefficient in association with the data Xn, and is configured to output the predetermined data Yn with respect to the data Xn. That is, since the data Xn is obtained by subtracting the data Bn from the data Wn, Yn = α / (Wn−Bn) (α is a constant coefficient). Then, the data Sn captured in the C register 19 and the data Yn read from the ROM 22 are input to the multiplier 20, and the data Mn obtained by multiplying the data Sn by the data Yn is converted into the D register 23.
Give to. Therefore, the data Mn taken into the D register 23 becomes Mn = (Dn-Bn) .alpha ./ (Wn-Bn) with respect to the data Dn, which satisfies the shading distortion correction condition based on the correction data.

Further, this data Mn is stored in the selector 24.
Is supplied as address data to the RAM 25 in which data is set as a gamma correction conversion table, and non-linear data Gn with respect to the data Mn is sent to the data bus 17. In the normal gamma correction, the conversion characteristic is set so as to compensate for the non-linearity on the side of reproducing the image signal, and the data corresponding to all points in the range where the input data changes is stored in the RAM 25. It has been written.

Regarding the writing of data to the RAM 25, normally, all the data is created externally and is written in the RAM 25 from the data bus 17 in association with the address data supplied from the address generating circuit 26. However, here, only the data having appropriate intervals on the curve showing the required conversion characteristics is externally created and written in the RAM 25, and the data between these data is processed by the internal circuit. Can be created and interpolated. For example, for two points of data A1 and A2, Y = (A2-A1) .X + A1 is calculated to obtain data between two points of A1 and A2 by linear interpolation.

FIG. 4 is a diagram showing the flow of each data when creating the data to be set in the RAM 25, and FIG. 5 is a timing diagram for explaining the operation. Note that the configuration of the circuit block is the same as that in FIG. 1 and its description is omitted. In the RAM 27, data located on a desired characteristic curve is set in advance at several specific addresses, and at the beginning of the initial setting period, two pieces of data are read from the RAM 27 to the data bus 17 so that the A register 11 and B register 1
Taken in 2. For example, 9 on the curve showing the conversion characteristic
Unique data D0 to D at addresses corresponding to points
8 is stored, and adjacent two data are sequentially loaded into the A register 11 and the B register 12.

First, the A register 11 and the B register 1
Data D1 and data D2 from 2 respectively
5, and the data S1 obtained by subtracting the data D1 from the data D2 is given to the C register 19. continue,
The data S1 is input to the multiplier 20 from the C register 19 and the data C1 is input from the ROM 22 to output the data S1.
The data M1 (1) obtained by multiplying the data C1 with the data C1 is given to the D register 23. Data C given from ROM 22
1 represents one section between the address of the data D1 and the address of the data D2, which is divided into a plurality of equal sections. For example, in the case of dividing into eight sections, it represents ⅛. Then, the data M1 (1) is input from the D register 23 to the adder / subtractor 15, and the data data A1 (1) obtained by adding the data D1 to this data M1 (1) is added to the C register 1
9 and sends it from the C register 19 to the data bus 17 and writes it in the RAM 25.

Similarly, the data D1 and the data D2 are repeatedly input to the adder / subtractor 15 from the A register 11 and the B register 12, and the output thereof is sequentially multiplied by the data C2, C3 ... , And by further adding the data D1, the data A1 (2), A1 (3) ...
・ Get and write to RAM25. For example, when the address from the data D1 to the data D2 is divided into 8 sections,
The data C1 to C7 are given from the ROM 20 for each section, and the operation represented by A1 (m) = (D2-D1) .Cm + D1 (m is an integer) is executed for each of the data D1 and data D1. Data A1 (1) to A1 (7) located on a straight line passing through the data D2 are obtained. Therefore, the data between the data D1 and the data D2 is linearly interpolated. After the interpolation between the data D1 and the data D2 is completed as described above, the data Dn (n = 2, 3
...) and the data Dn + 1 are sequentially read and fetched in the A register 11 and the B register 12, and predetermined arithmetic processing is repeated to obtain the data An (m), and the data between the respective data are linearly interpolated to obtain the data D0. Data from D8
The continuous data is set in the RAM 25.

As described above, the interpolation data between the two data is calculated based on the data Dn set in the specific address of the RAM 25 and is written in the RAM 25, thereby writing the data in the RAM 25. Is simplified. Further, most of the arithmetic circuit portion that calculates the data to be written in the RAM 25 is used in common with the arithmetic circuit that performs the shading distortion correction processing, so that the increase in the arithmetic circuit portion can be minimized.

[0018]

According to the present invention, the data indicating the difference between the black level and the white level is stored in the memory together with the data indicating the black level, and the shading distortion correction process is performed based on these data. As a result, necessary arithmetic processing can be completed in two steps of subtraction and multiplication, and high speed operation becomes possible.

In addition, by performing a part of the common arithmetic circuit for the arithmetic operation executed when obtaining the data for shading distortion correction and the arithmetic operation executed when actually performing the shading distortion correction processing, the arithmetic circuit The increase in the circuit configuration of the part is suppressed. Further, these arithmetic circuits can be operated as a writing circuit of a RAM provided so as to perform a non-linear conversion process on the output side of the device, and the arithmetic circuits can be efficiently used.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image signal processing device of the present invention.

FIG. 2 is a timing diagram illustrating an operation when setting correction data.

FIG. 3 is a timing diagram illustrating a calculation process for correcting shading distortion.

FIG. 4 is a block diagram showing a data flow when initializing a RAM for nonlinear conversion processing.

FIG. 5 is a timing diagram illustrating an operation when initializing a RAM for nonlinear conversion processing.

FIG. 6 is a waveform diagram showing shading distortion of an image signal obtained from an image sensor.

FIG. 7 is a block diagram of a conventional image signal processing apparatus that corrects shading distortion.

[Explanation of symbols]

 1, 10 A / D converter 2 Reference control circuit 3 Peak hold circuit 4, 25, 27 RAM 11, 12, 19, 23 Register 13, 14, 16, 21, 24 Selector 15 Adder / subtractor 17 Data bus 18 Address bus 20 Multiplier 22 ROM 26 Address generation circuit

Claims (4)

[Claims] 1. A processing device for correcting a signal level bit by bit for an image signal for each line obtained from an image sensor, stores first data indicating a first reference level, and stores the first data. A first memory that stores second data indicating a difference between the second reference level and a reference level, a first arithmetic circuit that subtracts the first data from input image data, and the second memory. A second memory for storing multiplier data associated with the data; and a second arithmetic circuit for multiplying the image data from which the first data is subtracted by the multiplication data read corresponding to the second data. An image signal processing device comprising: 2. The first data obtained by receiving the image signal of the first reference level is stored in the first memory, and then the image signal of the second reference level is received, and the first data is received. 2. The image signal processing apparatus according to claim 1, further comprising an initial setting unit that stores the second data obtained by subtracting the data of 1. in the first memory. 3. The first arithmetic circuit subtracts the first data from the image signal data of the second reference level during the initial setting period and supplies the subtracted first data to the second memory. Item 2. The image signal processing device according to item 2. 4. The image signal processing apparatus according to claim 1, further comprising decoding means for receiving output data of the second arithmetic circuit and outputting non-linear data to the data.