JPH04362894A - Color signal processor - Google Patents

Abstract

PURPOSE:To convert a color signal without deterioration by adding the first sample having a reference phase and a phase difference, the second sample difference data having a phase opposite to that of the first sample, and the 1H delayed difference data. CONSTITUTION:From a terminal 101 a carrier color signal is input, a PLL circuit 26 extracts a color burst signal from the carrier color signal input from the terminal 101, and a latch 1 is driven by a clock SC4. C data 104 is driven by latch 2, non-inversion output latch 3, output inversion/non-inversion select latches 4 and 5 at predetermined clocks to divide C data to 4-phase data systems. Further, C data 104 are selectively added to one another by adders 6 and 7. Of divided data, difference data units between data units having a phase difference of 180 deg. are supplied to clock conversion circuits 28 and 29. Adders 10 and 11 respectively add signals 113 and 115 delayed by 1H with line memories 8 and 9 and outputs 7 having no delay together. According to this constitution, without signal deterioration, mutual conversion can be done between the carrier color signal and the color difference signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing device for processing a carrier color signal.

0002

2. Description of the Related Art When digital processing such as noise reduction is performed on a composite image signal composed of a luminance signal and a carrier color signal using, for example, a field memory, the carrier color signal is a color difference signal, etc. It is advantageous to perform the above processing after demodulating the baseband signal into a baseband signal because it can be performed without considering the phase of the carrier color signal.

In this case, the carrier color signal is demodulated into a color difference signal by directly analog-to-digital (A/D) converting the carrier color signal using a sampling clock phase-synchronized with the color burst signal of the carrier color signal. , a baseband color difference signal in the form of a digital signal is obtained.

The above-mentioned demodulation processing operation will be explained in detail below using a PAL color television signal as an example.

[0005] The carrier color signal C separated from the PAL color television signal is A/Ded using a sampling clock whose phase is synchronized to four times the frequency of the color burst signal.
Convert the obtained sample data according to the reference phase,
The carrier color signal is demodulated into a color difference signal by dividing the sample data into phases and taking the difference between sample data whose phases differ by 180 degrees.

Now, the sample data obtained by the sampling clock of the BY carrier wave phase (0°) is PBY,
If the sample data obtained by a sampling clock with a phase of 90° is ERY, the sample data obtained by a sampling clock with a phase of 180° is NBY, and the sample data obtained by a sampling clock with a phase of 270° is LRY, then at odd number line (When the phase of the color burst signal is 225°) PBY=B-Y+DC ERY=R-Y+DC NBY=-(B-Y)+DC LRY=-(R-Y)+DC When the phase of the color burst signal is 225° 135°) PBY=B-Y+DC ERY=-(R-Y)+DC NBY=-(B-Y)+DC LRY=R-Y+DC Therefore, B-Y=(PBY-NBY)/2 R- Y=(ERY-LRY)/2 (at odd number line)
-(ERY-LRY)/2 (for even lines), and demodulated data is obtained.

[0007]It should be noted that the same R-
To obtain Y data, either invert the phases of the ERY and LRY sampling clocks for each line, or invert the ERY and LRY sampling clocks for each line.
This can be obtained by reversing the polarities of RY and LRY.

By the way, if the phase of the color burst signal and the phase of the sampling clock match exactly as described above, the carrier color signal can be demodulated into a complete color difference signal by the above processing, but in reality, A reference signal transmission system, PLL (PhaseLo
It is difficult to accurately match the phase of the sampling clock with the phase of the color burst signal, that is, the demodulation axis, due to individual deviations of circuits such as the CKED LOOP circuit system, fluctuations in power supply voltage, and the like.

Furthermore, in the case of NTSC color television signals, even if the sampling clock phase and the demodulation axis do not match, as long as the orthogonal relationship is maintained, there is no problem except in processing that handles absolute hue. The following problems occur in PAL color television signals.

Now, when a carrier color signal having a phase angle θ, an amplitude r, and a DC component DC is A/D converted using a sampling clock shifted by a phase φ from the BY axis and the RY axis, the obtained sampling data is It will look like this: (Data for odd lines is marked with ", and data for even lines is marked with '.) For odd lines (when the color burst phase is 225°) P
BY'=r*cos(θ-φ)+DCERY'=r*s
in(θ-φ)+DCNBY'=-r*cos(θ-φ
)+DCLRY'=-r*sin(θ-φ)+DC even line (when color burst phase is 135°) PBY
”=r*cos(θ+φ)+DCERY”=-r*si
n(θ+φ)+DCNBY”=-r*cos(θ+φ)
+DCLRY”=r*sin(θ+φ)+DC According to the above results, the demodulated data obtained will be different for each line, and it will be possible to connect two screens like a wipe or fade, or change the correlation between images. In processing such as noise reduction using , it becomes difficult to preserve hue.

[0011] Therefore, as a method for solving the above-mentioned problems, a method of summing demodulated data of different line polarities as described below can be considered.

BY (odd line + even line) = (PBY'-NBY') + (PBY''-NBY') =
4r(cos(θ-φ)+cos(θ+φ))=4rc
osφcosθ RY (odd line + even line) = (ERY”-LRY”) + (LBY”-EBY”) =
4r(sin(θ-φ)+sin(θ+φ))=4rc
osφsinθ From the above results, each demodulated color signal component has a form in which the BY and RY signal components are multiplied by a constant scalar amount 4cosφ, and the absolute hue is determined.

In order to modulate the color difference signal into the original C signal, opposite polarity data is formed from the demodulated data, and the positive and negative data of the B-Y and R-Y components are sequentially D/A converted according to the chroma sequence. However, in the PAL color television system, the polarity of the R-Y carrier wave is inverted for each line, so the order of D/A conversion is B-Y demodulated data, R-Y polarity inverted data, B- Y polarity inversion data,
The RY demodulated data is alternately performed line by line.

[0014]

[Problems to be Solved by the Invention] By the way, by converting the carrier color signal into a digital baseband signal through the above-mentioned modulation and demodulation processing, screen composition processing such as wipe and fade can be performed by using field memory, etc. However, if the signal to be processed using field memory, etc. is a signal that includes time axis fluctuations, horizontal By performing processing according to a reference clock obtained by multiplying the synchronization signal, the geometric positions of sample data used in the processing can be easily aligned.

However, the reference clock used in the above-mentioned modulation/demodulation processing is, for example, the reference signal fSC used when converting a low frequency converted color signal into a carrier color signal in the reproduction processing of a VTR, or the reference clock used in the conversion processing. A clock that is phase-synchronized with the color burst signal of the carrier color signal obtained by the method is used, and this clock has no phase synchronization relationship with the clock obtained by multiplying the horizontal synchronization signal, but is obtained by the modulation/demodulation processing described above. When the above-mentioned screen synthesis processing, noise reduction processing, special playback processing, etc. are performed on the baseband signal, beats are generated and processed because the reference clocks used in each processing are not phase-synchronized. There was a risk that the signal would deteriorate.

The present invention has a simple configuration, converts a carrier color signal into a color difference signal without generating beats, and converts the converted color difference signal into the original carrier color signal without deteriorating it. The purpose of this invention is to provide a color signal processing device that can perform the following functions.

[0017]

[Means for Solving the Problems] A color signal processing device of the present invention is a device for processing color signals, and is capable of sampling a carrier color signal using a sampling clock phase-synchronized with a reference phase of the carrier color signal. Input the sampling data formed by, and among the input sample data,
difference data forming means for forming difference data between first sample data having a first phase difference from the reference phase and second sample data having an opposite phase to the first sample data; and the difference data forming means. data rate converting means for converting and outputting the data rate of differential data formed by the data rate converting means; delay means for delaying the differential data output from the data rate converting means by one horizontal synchronization period; The apparatus includes an adding means for adding the output difference data and the difference data delayed by the delay means and outputting the result.

[0018]

[Operation] According to the above structure, it is possible to convert a carrier color signal into a color difference signal without generating a beat or the like, and to convert the converted color difference signal into the original carrier color signal without deteriorating it. I will be able to do it.

[0019]

EXAMPLES The present invention will be explained below using examples of the present invention.

FIG. 1 is a diagram showing a schematic configuration of a color signal processing device to which the present invention is applied as an embodiment of the present invention, and FIG.
3 is a timing chart for explaining the operation of the configuration shown in FIG. 1.

In FIG. 1, 1, 2, 14, 24 are latch circuits, 3, 15 are inverted output latch circuits, 4, 5, 16
, 17 is an output inversion/non-inversion selection latch circuit, 6, 7, 1
0 and 11 are lower digit input adders, 8 and 9 are line memories, 12 is a multiplexer, 13 is a demultiplexer,
18, 19, 20 are logical combinational circuits as shown in FIG. 3, 21, 22, 27 are adders, 23 is a selection output circuit, 2
5 is a timing controller, 26 is a PLL circuit, 2
8 and 29 are clock conversion circuits.

100 is an input terminal for C data (1 sample 6 bits) obtained by A/D converting the C signal by an A/D converter (not shown); 101 is an input terminal for the C signal; 102 is not shown This is an input terminal for a timing signal representing a section of a color burst signal obtained by a synchronous separation circuit or the like.

In FIG. 1, a color burst signal is extracted from a carrier color signal inputted from an input terminal 101 in a PLL circuit 26 according to a timing signal inputted from an input terminal 102. A clock SC4 whose phase is synchronized to four times the average phase of the color burst signal is generated and the latch circuit 1 is operated, thereby causing the latch circuit 1 to generate C data 104. (See FIG. 2. In FIG. 2, data 104'' represents data on odd lines, data 104' represents data on even lines, and the same applies below.)

Next, the C data 104 has a predetermined phase difference from the color burst signal, and has clocks SCA, SCB, SCC, and SC having a period of fSC (fSC is the subcarrier frequency).
D operates the latch circuit 2, the inverted output latch circuit 3, and the output inverted/non-inverted selection latch circuits 4 and 5, thereby dividing the data into four phase-based data series. Inverted output latch circuit 3
By adding the data output from the output inverting/non-inverting selection latch circuits 4 and 5 by the adder 6, the data output from the output inverting/non-inverting selection latch circuits 4 and 5 are added by the adder 7. Difference data between data that differ by 180 degrees is formed, and the clock conversion circuits 28 and 29
supplied to

If the C data output from the A/D converter is a two's complement system, the above processing will be as follows.

That is, the pseudo BY data DBY is

0
027]

[Example 1] The latch circuit 2 operated by the clock SCA and the inverted output latch circuit 3 operated by the clock SCC extract data DSCA and data DSCC of inverted polarity, which are 180 degrees different in phase from each other, and output the data DSC.
C is inverted by the inverting output latch circuit 3 and supplied to the adder 6, and the carry input (CI in the figure) of the adder 6 is set to "H".
The above processing is performed by inputting a level signal.

Furthermore, in the PAL color television system, since the R-Y carrier phase is inverted for each line, when forming the pseudo R-Y data DRY, the clock SC
B, data DSCB of inverted polarity extracted by the output inverting/non-inverting latch circuits 4 and 5 operated by SCD;
, DSCD is inverted and outputted line by line according to the color burst phase using the timing signals PL and NL, and is further formed in the same manner as the above-mentioned DBY.

Note that the output inverting/non-inverting latch circuit 4,
For example, 5 is configured as shown in FIG. 4a, and in FIG. 4a, 41 is an exclusive or gate, 42
is a latch circuit, or inverts the phase of input data in accordance with timing signals PL and NL that invert the polarity so that the polarities are different from each other every line period.

The demodulated data formed as described above is expressed as follows.

[0031]

Note that the clock conversion circuits 28 and 29 in FIG. 1 are configured as shown in FIG. 5.

In FIG. 5, 30 is a data input terminal;
1 and 32 are flip-flop circuits, 33 is a data output terminal, 34 is a data transfer clock input terminal, 35 is a delay circuit, and 36 is a clock input terminal for controlling the delay circuit 35.

Now, the period of the data transfer clock input from the input terminal 34 is Tb, the period of the clock input from the input terminal 36 is Tc, the flip-flop circuit 31,
32 propagation delay time tpd, flip-flop circuit 3
1 and 32, the delay time τ3 of clock B with respect to clock A in the figure is
is τ3>Tb −Tc −tsu−tpdτ3≦Tb
-tsu-tpd.

Here, Tc ≦Tb /2, and tpd+tsu is generally very small, and tpd+t
Since it is considered that su≦Tc /2, tpd+tsu≦
τ3≦Tb.

Data input from the input terminal 30 is input in synchronization with a clock obtained by dividing the clock input from the input terminal 36, and the frequency of the clock input from the input terminal 36 is input from the input terminal 34. If the frequency is twice or more than the frequency of the data transfer clock input from the input terminal 34, the data input from the input terminal 30 can be transferred in synchronization with the data transfer clock input from the input terminal 34.

Therefore, the input terminal 36 in FIG. 6 receives the clock 80 generated by the timing controller 25 in FIG.
H CKED SC4 is supplied, and the input terminal 30 receives a clock 80H CK input from the input terminal 36.
The difference data in synchronization with ED SC4 is sent to adder 6.
, 7, and the clock 80H which is in a multiplier relationship with the horizontal synchronizing signal is input from the timing controller 25 to the input terminal 34.
From 9 onwards, the clock 80H has a multiplication relationship with the horizontal synchronization signal.
Difference data that has been subjected to clock conversion processing is output in synchronization with .

Note that the data rate of the differential data obtained by the differential processing is 2fSC≒(567+1/2)f
h (fh is the horizontal synchronization frequency), so even if clock conversion processing is performed by the clock conversion circuits 28 and 29 configured as described above at this stage, the beat will have a period of 2H and a width of 0.
Since it is 5fSC, it is almost invisible visually.

[0038]The clock conversion circuits 28 and 29
The differential data subjected to clock conversion processing is supplied to line memories 8 and 9 and adders 10 and 11.

Note that the demodulated data obtained by the above processing will be different for each line if the phases of the sampling clock and the demodulation axis do not match, as described above, so the one-line memory shown in FIG. By adding the demodulated data delayed by one line period by 8 and 9 and the undelayed data by adders 10 and 11, demodulation processing including color burst is completed.

Furthermore, since the C signal has a lower data rate than the Y signal, which is normally processed simultaneously, in this embodiment, the C signal is selected in a time-division manner by the multiplexer 12 operated by the timing signal B/R and MEMCK. It is being output.

During modulation, the demodulated data formed as described above is sent to the demultiplexer 13 and the latch circuit 1.
4. The following modulation data is formed by the inverting output latch circuit 15 and the output inverting/non-inverting selection latch circuits 16 and 17.

[0042]

The C signal is restored by sequentially outputting the formed modulation data by the selection output circuit 23 and the latch circuit 24 according to the chroma sequence and performing D/A conversion.

Note that when forming modulated data, the polarity of R-Y data is set to clocks PHB and PH, similarly to when forming demodulated data.
The inverting/non-inverting latch circuits 16 and 17 operated by the timing signal L
They are alternately reversed by S and XLS.

By the way, as mentioned above, the level of demodulated data obtained during demodulation is 2VC, but the level of modulated data required during modulation is VC, and the dynamic range of the A/D and D/A converters used is If they are at the same level,
It is necessary to reduce the level of modulation data to 1/2.

However, when the level of modulated data is halved as described above, the least significant bit (LSB)
digit loss occurs, which adversely affects the S/N of modulated data.

Therefore, in this embodiment, as described above, the demodulated data is divided into (number of bits during A/D conversion: 6 bits)+1 bit.
= 7 bits, and the following processing is performed during modulation so that the peak to peak value of data is not impaired.

That is, the above-mentioned processing is carried out, for example, by the logic combinational circuits 18, 19, 2 configured as shown in FIG.
This is done at 0.

FIG. 4b shows the configuration of the logic combinational circuit 18, which is composed of AND gates 43, 45, and a NAND gate 44, and FIG. 4c shows the configuration of the logic combinational circuit 18.
9 and 20, and the AND gates 43 and 46
, and a NAND gate 44.

7 bits output from the inverted output latch circuit 15 by the logic combination circuit 18 shown in FIG.
The adder 27 to which the upper 6 bits of data are supplied controls whether to permit or prohibit addition of the carry input (CI in the figure) to the supplied 6 bits of data. Logic combinational circuit 1 shown in
9 and 20, the output inversion/non-inversion selection latch circuit 16
, of the 7-bit data output from 17, the top 6
In the adders 21 and 22 to which bits are supplied, a carry input (
By controlling whether to enable or disable addition of CI) in the figure, data can be inverted and modulated while maintaining resolution without increasing the number of bits of A/D and D/A converters. You will be able to form data.

The modulated data for the demodulated data is, for example, as follows.

[0051] Demodulated data +10
+11 -10 -11 Modulation data (non-inverted) +5 +5
-5 -6 Modulation data (inverted) -5 -6 +5
+5 peak to peak
Value +10 +11 -1
0 -11 Also, the C signal is D/A converted from the modulated data formed as described above, and then restored to an analog signal via a low-pass filter (not shown). There is no loss of sexuality.

Furthermore, the logic combinational circuits 18 and 19
, 20 are for overflow prevention when similar processing is performed when the demodulated data input during modulation is the minimum value (the largest negative number in absolute value).

As explained above, in the color signal processing device shown in this embodiment, when demodulating a carrier color signal, C data and data of the opposite phase thereof are used as demodulated data of the carrier color signal. By using the difference, D of C data
It is now possible to digitally modulate and demodulate the carrier color signal without using a C offset, and when a DC offset occurs near the threshold during A/D conversion, it is possible to eliminate fluctuations in the DC offset data, power supply voltage fluctuations, This prevents hue fluctuations in the carrier color signal due to modulation/demodulation processing caused by mismatch between DC offset values and data due to element individual deviations, etc., and also prevents deterioration in resolution of modulation/demodulation processing.

Furthermore, by adding the demodulated data between lines, it is possible to prevent demodulated data from being different for each line when the phases of the sampling clock and the demodulated axis do not match, and to prevent demodulation of the absolute axis from occurring. It becomes possible, and furthermore,
Since the color burst phase for each line in the PAL color television system is inverted by inverting the data polarity, the geometric arrangement of sample points can be completed in a 4-field sequence, making screen composition processing easier. become.

Furthermore, in this embodiment, by performing the clock conversion process during the demodulation process, when processing is performed using the clock generated based on fh and the clock generated based on fSC, the generation of beats is prevented. It becomes possible to prevent this.

Furthermore, since the clock conversion process is performed before the line addition process using the line memory, the number of storage words of the line memory used for the demodulation process is determined by fS.
It becomes possible to arbitrarily select a clock that corresponds to the clock generated based on fh, regardless of the clock generated based on C.

[0057]

[Effects of the Invention] As explained above, according to the present invention, a carrier color signal is converted into a color difference signal without generating a beat etc. with a simple configuration, and the converted color difference signal is not deteriorated. It becomes possible to provide a color signal processing device that can convert the color signal to the original carrier color signal without any process.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a color signal processing device to which the present invention is applied, as an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the configuration shown in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the configuration shown in FIG. 1;

FIG. 4 is a diagram showing a detailed configuration of a part of the configuration shown in FIG. 1;

FIG. 5 is a diagram showing a detailed configuration of the clock conversion circuit shown in FIG. 1;

[Explanation of symbols]

1 Latch circuit 2 Latch circuit 3 Inverted output latch circuit 4 Output inversion/non-inversion selection latch circuit 5 Output inversion/non-inversion selection latch circuit 6 Lower digit input adder 7 Lower digit input adder 8 Line memory 9 Line Memory 10 Lower digit input addition adder 11 Lower digit input addition adder 12 Multiplexer 13 Demultiplexer 14 Latch circuit 15 Inversion output latch circuit 16 Output inversion/non-inversion selection latch circuit 17 Output inversion/non-inversion selection latch circuit 18 Logic Combinational circuit 19 Logical combinational circuit 20 Logical combinational circuit 21 Adder 22 Adder 23 Selection output circuit 24 Latch circuit 25 Timing controller 26 PLL circuit 27 Adder 28 Clock conversion circuit

Claims (1)

[Claims] 1. A device for processing a color signal, which inputs sampling data formed by sampling a carrier color signal with a sampling clock phase-synchronized with a reference phase of the carrier color signal. Among the sample data, a first phase having a first phase difference from the reference phase
difference data forming means for forming difference data between the sample data and second sample data having an opposite phase to the first sample data; and converting the data rate of the difference data formed by the difference data forming means. , a data rate conversion means for outputting, a delay means for delaying the difference data output from the data rate conversion means by one horizontal synchronization period, and a difference data output from the data rate conversion means and the delay means for delaying the difference data output from the data rate conversion means. 1. A color signal processing device comprising an addition means for adding and outputting difference data.