JPH04184976A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to form a gate electrode without giving damage due to an etching of a polysilicon film and to improve the breakdown strength of a gate oxide film by a method wherein the gate electrode is constituted into a three-layer structure consisting of a polysilicon film, an oxide film and the polysilicon film, which are formed one after another from the lower part of the structure. CONSTITUTION:A gate oxide film 2, a polysilicon film 3, an oxide film 4 and a polysilicon film 5 are formed one after another on a silicon substrate consisting of a p-type low-concentration region 1. Then, the films 5 and 4 are subjected to anisotropic etching in order masking the substrate by a photolithography technique and after that, phosphorus is ion-implanted and n-type low-concentration regions 6 are formed. Subsequently, after a polysilicon film 10 is vapor-phase grown, an anisotropic etching is performed on the films 10 and 3 and sidewalls are formed. Arsenic is ion-implanted and n-type high-concentration regions 7 are formed. Thereby, when an anisotropic etching is performed on the gate oxide film 2 and the polysilicon film 5, the etching can be stopped by the oxide film 4 in the middle of a gate electrode. Accordingly, it is made possible to form the gate electrode without giving damage due to the etching and the breakdown strength of the gate oxide film can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device and a method for manufacturing the same.
S) Regarding transistors.

[Conventional technology]

A method of manufacturing the gate, source, and drain of a conventional MOS transistor will be described with reference to FIG.

A 200-layer gate oxide film 2 is formed by thermal oxidation on a silicon substrate starting from a low concentration P region 1 . 6,000 layers of polysilicon are grown over the entire surface, and the polysilicon is masked by photolithography and anisotropically etched to form gate polysilicon 9. Next, phosphorus was applied at an energy of 40 keV and a dose of I X I O”/aA.
Then, ions are implanted to form a low concentration n-type layer 6. (Figure 3 (
a)) Polysilicon is grown in vapor phase over the entire surface by 2,000 people, and anisotropic etching is performed to form a polysilicon sidewall 8. Arsenic with energy of 70 keV,
Ion implantation was performed at a dose of I x 10''/- at a high concentration n.
A mold layer 7 is formed. (FIG. 3(b)) Through the above steps, an n-channel MO8 transistor can be formed.

An advantage of the MOS transistor as shown in FIG. 3(b) is that the low concentration n-type region 6 corresponding to the LDD is located completely under the gate electrode (polysilicon 9 and polysilicon sidewall 10). Therefore, the gate oxide film 2
One example of this is that the resistance of the lightly doped n-type layer 6 immediately below is reduced. In other words, when a forward voltage is applied to the gate, the potential near the surface of the LDD portion below the gate is lowered and a channel is formed, thereby reducing the resistance of the LDD portion.

[Problem to be solved by the invention]

In the above-described conventional method for manufacturing a MOS transistor, anisotropic etching by RIE or the like is performed to form gate polysilicon 9, but this damages the gate oxide film. Therefore, when the polysilicon sidewall 10 is formed, there is a problem in that the withstand voltage of the gate oxide film under the sidewall is greatly reduced.

[Means to solve the problem]

A step of forming a gate oxide film, a step of forming a first polycrystalline silicon, a step of forming a first oxide film, and a step of forming a second polycrystalline silicon on the main surface of a semiconductor substrate. a step of etching the second polycrystalline silicon; a step of etching the first oxide film; a step of forming a first impurity diffusion region; and a step of forming a third polycrystalline silicon. , a step of etching back the third polycrystalline silicon to form a sidewall on a side surface of the second polycrystalline silicon, and a step of forming a second impurity diffusion region.

〔Example〕

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

On a silicon substrate consisting of a low concentration P vacant region 1, a gate oxide film 2 of 200 layers, a polysilicon layer 3 of 200 layers, and a polysilicon layer of 200 layers are formed.
Anisotropic etching is performed on the polysilicon 5 and the oxide film 4 in order by masking them by zero-order photolithography, which sequentially forms a human oxide film 4 and a 3,000-layer polysilicon film 5. Then, phosphorus is ion-implanted at an energy of 100 keV and a dose of 7×10 ”/aa to form a low concentration n-type region 6 .

After 2,000 layers of polysilicon 10 are grown in a vapor phase, polysilicon 10 and polysilicon 3 are anisotropically etched to form sidewalls. Then, arsenic was heated at an energy of 70 keV and a dose of I x 10”/
Highly doped n-type region 7 is formed by ion implantation using aa.

Through the above steps, an n-channel MO8) transistor can be formed.

Polysilicon 10 serves to electrically conduct polysilicon 5 and polysilicon 3.

FIG. 2 is a longitudinal section of another embodiment of the invention.

In this example, the polysilicon 5 in the previous example was replaced with metal silicide 11. The manufacturing method is shown below.

On a silicon substrate consisting of a low concentration P vacant region l, a gate oxide film 2 of 200 layers, a polysilicon layer 3 of 200 layers, and 2
00 people's oxide film 4 and 3000 people's metal silicide 11
are formed in sequence. Next, the metal silicide 11 and the oxide film 4 are sequentially anisotropically etched using a mask using photolithography 12. And phosphorus is energy 10
A low concentration n-type region 6 is formed by ion implantation at 0 keV and a dose of 7 x 10'''/d.After vapor phase growth of 2000 polysilicon 7, anisotropic etching is performed on polysilicon 7 and polysilicon 3. Then, arsenic is heated to 70 keV energy.
Ion implantation is performed at a dose of lXl0''/afl at high concentration n
A mold region 8 is formed. Through the above steps, an n-channel MOS transistor can be formed. In Example 2, since metal silicide is used for a part of the gate electrode, the gate electrode can be made to have low resistance.

〔Effect of the invention〕

As explained above, the present invention provides a method for manufacturing a gate electrode having a polysilicon sidewall. The gate electrode has a three-layer structure consisting of polysilicon, oxide film, and polysilicon from the bottom. When anisotropic etching is performed on the gate polysilicon using a mask using photolithography, the oxide film in the middle prevents the etching from occurring there. It can be stopped. Therefore, the gate electrode can be formed without damaging the gate oxide film under the lower polysilicon due to etching of the polysilicon, and the withstand voltage of the gate oxide film can be greatly improved. When examining the amount of charge injected that causes destruction of the gate oxide film, it was found to be 1.5 C/aJ in the conventional MOS transistor, but it was significantly improved to 15 C/cat in the present invention.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. FIG. 2 is a longitudinal sectional view of another embodiment of the invention. FIG. 3 is a longitudinal sectional view for explaining the prior art. 1... Low concentration P empty region, 2... Gate oxide film, 3... Polysilicon, 4...
Oxide film, 5...Polysilicon, 6...
Low concentration n-type region, 7... High concentration n-type region, 8.
...Side wall, 9...Gate polysilicon, 10...Polysilicon, 11...
...Metal silicide. Agent patent attorney Uchihara Oto? ? Figure (IL) Figure 7 (b) Figure 2

Claims (3)

[Claims] (1) A step of forming a gate oxide film, a step of forming a first polycrystalline silicon, a step of forming a first oxide film, and a step of forming a second polycrystalline silicon on the main surface of a semiconductor substrate. a step of etching the second polycrystalline silicon; a step of etching the first oxide film; a step of forming a first impurity diffusion region; and a step of forming a third polycrystalline silicon. a step of etching back the third polycrystalline silicon to form a sidewall on a side surface of the second polycrystalline silicon; and a step of forming a second impurity diffusion region. A method for manufacturing a semiconductor device. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the second polycrystalline silicon is metal silicide. (3) A first conductor is provided on one main surface of a semiconductor substrate of one conductivity type via a first insulating film, and a second conductor and a second conductor are provided directly above the first conductor. an insulating film, a third conductor is provided directly above the second insulating film, and the second conductor is adjacent to a side surface of the second insulating film and a side surface of the third conductor. A semiconductor device characterized in that the semiconductor device is surrounded by