JP2897555B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a short-channel CMOS transistor, in which the formation of the source / drain is simplified and the manufacturing cost is reduced.

[0002]

2. Description of the Related Art In forming a source / drain of a CMOS, one photomask is used for an n-channel transistor, and one photomask is used for a p-channel transistor. Further, as the device has a shorter channel, it is necessary to use a low doping concentration for the source / drain structure, attach a sidewall to the gate electrode, and then form the source / drain electrode at a high concentration. Therefore, two more photomasks are used. In other words, four photomasks are generally used to form the source and drain of the CMOS.

Here, a conventional CMOS manufacturing method will be described with reference to the sectional views of FIGS. 5 and 6 and the process flow of FIG.

An n-well 102 and a p-type silicon
A well 103 is formed, and a field oxide film 104 is further formed by, for example, a selective oxidation method as shown in the element sectional view of FIG. Next, a gate oxide film 105 having a film thickness of 10
A non-doped polysilicon 106 is deposited to a thickness of about 300 nm, and a polysilicon gate electrode 106 is formed by photolithography as shown in the element sectional view of FIG. After the gate electrode is formed, a photoresist 119 is formed by using a photolithography technique, and using this as a mask for ion implantation, phosphorus is added to the p-well at 40 keV at 2 × 10 ¹³ / cm 2.
About ^two ions are implanted to form an n-source / drain n ^- region 113 of the nMOSFET as shown in the element cross-sectional view of FIG. Next, a photoresist 120 is formed using a photolithography technique, and using this as an ion implantation mask, boron is applied to the n-well at 15 keV at 2 × 10 ^13.
/ Cm ² as to In'o injection, p of source-drain of the pMOSFET, as shown in element cross-sectional view of FIG. 5 (D) ^- to form a region 109. Next, as shown in the device sectional view of FIG. 5E, a silicon oxide film 121 is deposited to a thickness of about 150 nm, and as shown in the device sectional view of FIG. A side wall 122 is formed by using a photolithography technique.
A photoresist 123 is formed, and the photoresist 123 is used as an ion implantation mask.
Ion implantation at about 5 × 10 ¹⁵ / cm ^{2 at 0} keV and nM
The source / drain n ⁺ region 116 of the OSFET is formed. Next, another photolithography technique is used to form a photoresist 124 as shown in the element sectional view of FIG.
Is formed, and BF ₂ is applied to the n-well and the polysilicon on the n-well at 50 keV at 5 × 1 using this as an ion implantation mask.
About ¹⁵ / cm ² ions are implanted to form p ⁺ regions 112 of the source and drain of the pMOSFET. Next, for example, N ₂ annealing is performed at 850 ° C. for about 30 minutes to activate the source / drain of the transistor and the region of the polysilicon electrode. Deposit about 40 nm in thickness. Next, when a heat treatment is performed at a temperature of about 700 degrees Celsius, titanium silicide 118 is formed in a self-aligned manner only in the gate polysilicon and the diffusion layer. Only the remaining titanium and its reaction products are selectively removed from the insulating film.

[0005]

The above-mentioned conventional CMs
As is clear from the process flow after the gate electrode is formed in FIG.
Four photomasks are used. Regarding the photolithography technology, the process used is not a batch process but a single wafer process, and the alignment exposure apparatus used is expensive and relatively expensive. In addition, the photolithography process has a relatively large effect on yield degradation. It is advantageous if the number of photolithographic steps can be reduced because of these production cost problems.

Also, the conventional n-channel MOSF
The polysilicon electrode of ET is doped by arsenic ion implantation to suppress the short channel effect. 0.4 μm
The following CMOS technology has a short channel effect problem when using phosphorus instead of arsenic. On the other hand, if activation is performed at a low temperature or for a short time to suppress the short channel effect using arsenic, it is difficult to obtain a sufficient doping concentration for the entire polysilicon layer. There is a problem that causes the deterioration of the characteristics.

Further, when the silicide process is used, a thicker sidewall is required as compared with the optimum sidewall thickness for the n-channel transistor characteristics so that the silicide of the source / drain does not short-circuit with the silicide of the gate electrode. It is. That is, the thickness of the sidewall to obtain a high yield of the silicide process is:
There is a problem that it is too thick at least for the device characteristics of the n-channel MOSFET. In addition, since the silicide reaction consumes a lot of silicon, most of the silicon in the shallow source / drain diffusion layer for suppressing the short channel effect is reacted, and as a result, the junction leakage current increases, and the source / drain parasitic Resistance is rising. That is, there is a difficulty that the requirements for the short channel effect and the salicide process are different with respect to the source / drain junction depth.

In addition, since the source / drain junction depths of the n-channel MOSFET and the p-channel MOSFET are different, the optimum sidewall thickness of the n-channel MOSFET is different from that of the p-channel MOSFET in terms of device characteristics. Therefore, n-channel MOSFET and p-channel MOSFET
There is a problem that independent optimization cannot be performed for each.

[0009]

A feature of the present invention is that an n-channel MOS of a CMOS integrated circuit is formed on one main surface of a semiconductor substrate.
A method of forming a FET and a p-channel MOSFET, a step of forming gate electrodes of both MOSFETs, a step of depositing a double layer comprising a silicon nitride film as a lower layer and a silicon oxide film as an upper layer on the entire surface; MO
Selectively removing the double-layered silicon oxide film from the SFET formation region and forming a side wall of the silicon nitride film on a side of a gate electrode of the n-channel MOSFET; Forming a first n ⁺ region of the drain;
Removing the side wall of the silicon nitride film of the OSFET to form a source / drain n ⁻ region of the n-channel MOSFET; and forming a side wall of a first insulating film on a side of a gate electrode of the n-channel MOSFET. Removing the double-layered silicon oxide film remaining in the formation region of the p-channel MOSFET;
Forming a source / drain second n ⁺ region of the FET; removing the double-layer silicon nitride film remaining in the region of the p-channel MOSFET; ^- semiconductor including the steps of forming a region, and the step of the side walls of the second insulating film is formed on the side of the gate electrode of the p-channel MOSFET, to form a p ⁺ region of the source and drain of the p-channel MOSFET An apparatus manufacturing method.

Another feature of the present invention is a method of forming an n-channel MOSFET and a p-channel MOSFET of a CMOS integrated circuit on one principal surface on a semiconductor substrate.
A step of forming a gate electrode of an FET; a step of depositing a double layer comprising a silicon nitride film as a lower layer and a silicon oxide film as an upper layer on the entire surface; and selectively forming the double layer from the formation region of the p-channel MOSFET. To form p ^- regions of source / drain of the p-channel MOSFET, to form a side wall of a first insulating film on a side of a gate electrode of the p-channel MOSFET,
Forming a source / drain p ⁺ region of the ET, removing the double-layer silicon nitride film remaining in the formation region of the n-channel MOSFET, and removing a source / drain n ⁻ region of the n-channel MOSFET. Forming
A second portion is provided on the side of the gate electrode of the n-channel MOSFET.
Forming an insulating film side wall, and forming the n-channel MOSFET
Forming a source / drain n ⁺ region.

[0011]

Next, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 showing sectional views in the order of steps and FIG. 7 showing a step flow after forming a gate electrode.

An n-well 102 and a p-well 103 are formed on a p-type substrate 101, and a filled oxide film 104 is formed by, for example, a selective oxidation method as shown in the element sectional view of FIG. Next, a gate oxide film 105 is formed to a thickness of about 10 nm, and a non-doped polysilicon 106 is deposited to a thickness of 300 nm.
Then, a gate electrode 106 is formed by photolithography as shown in the element cross-sectional view of FIG. Next, a silicon nitride film 107 is deposited to a thickness of about 150 nm, a silicon oxide film 108 is deposited to a thickness of about 50 nm, and a photoresist 125 is formed using a photolithography technique as shown in the element sectional view of FIG. Then, using this as an etching mask, the silicon oxide film 108 in the nMOSFET region is removed by isotropic etching. Next, the sidewalls 12 are anisotropically etched.
6 is formed, FIG. 1 nMOSFET source drain in the n ⁺ arsenic region 12 of arsenic as shown in element cross section by ion implantation about 1 × 10 ¹⁵ / cm ² at 70keV in (D)
7 is formed. Next, hot phosphoric acid is applied to the side wall 12.
6 is removed, and phosphorus is ion-implanted at 40 keV to about 2 × 10 ¹³ / cm ² to form the n ⁻ region 113 of the source / drain of the nMOSFET. As shown in the element cross-sectional view of FIG. 128 is deposited to a thickness of about 300 nm.
Next, a side wall 129 is formed by anisotropic etching, and phosphorus is reduced to 7 as shown in the element sectional view of FIG.
Ion implantation at about 5 × 10 ¹⁵ / cm ^{2 at 0} keV and nM
The source / drain n ⁺ phosphorus region 130 of the OSFET is formed. Next, the silicon nitride film 10 remaining in the n-well
7 is removed and boron is added at 15 keV to 2 × 10 ¹³ / cm ^2.
As ion implantation to the source and drain of the pMOSFET p ^- forms a region 109 is deposited a silicon oxide film 131 as the film thickness 150nm, as shown in FIG. 2 (B). Next, a side wall 132 is formed by anisotropic etching, and BF ₂ is applied at 50 keV for 5 seconds as shown in FIG.
Ion implantation is performed at about × 10 ¹⁵ / cm ² to form p ⁺ regions 112 of source and drain of the pMOSFET. That B
Although the F ₂ ion implantation enters the region of the nMOSFET, the activated concentration of phosphorus is much larger than that of BF ₂ and the junction depth of phosphorus can be made deeper than that of BF _2.
The source / drain doped with ET phosphorus and the polysilicon electrode are preserved. Next, when the silicide technology is used, a heat treatment is performed at a temperature of, for example, 850 degrees Celsius to activate the ion-implanted impurities of the source / drain and the polysilicon electrode. For example, as shown in the element cross-sectional view of FIG. Titanium 117 is deposited to a thickness of about 40 nm.
Next, after a silicidation reaction is performed at a temperature of about 700 degrees Celsius, a titanium reaction product only in the insulating film is selectively removed, and as shown in the element cross-sectional view of FIG. The silicide 118 is formed only in the diffusion and polysilicon electrode regions.

The present embodiment, as can be seen from the above example,
Since the thick sidewall is used without deteriorating the device characteristics, as shown in FIG. 11, there is an effect of improving the yield related to bridging of the source / drain and the gate electrode.

In addition, since the present invention uses a deeper source-drain junction than the prior art, the junction leakage current and large parasitic resistance associated with a shallow junction are avoided in the case of a silicide process. Therefore, there is an effect that the reliability is improved as shown in FIG. Since the deterioration of the short channel effect can be suppressed despite the deep junction, FIG.
As shown in the dependence of the threshold voltage on the gate electrode length, device characteristics can be improved.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 and 4 showing cross sections in the order of steps and FIG. 8 showing a step flow after forming a gate electrode.

An n-well 102 and a p-well 103 are formed on a p-type substrate 101, and a field oxide film 104 is formed by, for example, a selective oxidation method as shown in the element sectional view of FIG. Next, the gate oxide film 105 is formed to a thickness of 10 nm.
And a non-doped polysilicon 106 having a film thickness of 30
About 0 nm, doping the film by phosphorus diffusion,
As shown in the element sectional view of FIG. 3B, the gate electrode 10 of phosphorus-doped polysilicon is formed by photolithography.
6 is formed. Next, the silicon nitride film 107 is
The silicon oxide film 108 is deposited to a thickness of 50 n
m, and a photoresist 125 is formed using a photolithography technique as shown in the element cross-sectional view of FIG.
8 is removed by isotropic etching. Next, using the remaining silicon oxide film 108 as a mask, the silicon nitride film 107 of the pMOSFET is removed with hot phosphoric acid to remove boron.
Implant 2 × 10 ¹³ / cm ² at 5 keV to obtain pM
The source and drain of OSFET p ^- forms a region 109, a silicon oxide film is deposited 110 as thickness 200nm as shown in element cross-sectional view of FIG. 3 (A). Next, a side wall 111 of a silicon oxide film 110 is formed by anisotropic etching, and BF ₂ is applied at 50 keV to 5 × 1.
About 0 ¹⁵ / cm ^{2, and} as shown in the element sectional view of FIG.
⁺ Region 112 is formed. Next, the silicon nitride film 107 remaining in the p-well 103 is removed by hot phosphoric acid, and phosphorus is ion-implanted at 2 × 10 ¹³ / cm ² at 40 keV to form n ⁻ regions 113 of source and drain of the nMOSFET. Then, as shown in the element sectional view of FIG. 4B, an oxide film 114 is deposited to a thickness of about 150 nm. Next, a side wall 115 of a silicon oxide film is formed by anisotropic etching, and arsenic is applied at 70 keV to 3 × 10 ¹⁵ / c.
as m ² and Io injection, the source and drain of the nMOSFET as shown in element cross-sectional view of FIG. 4 (C) n ⁺ region 11
6 is formed. Another photomask is used to prevent arsenic from entering the pMOSFET region, but an ohmic contact tunnel diode can be formed without using the photomask. Either method reduces the number of lithography steps as a whole as compared with the conventional technique. This second embodiment is similar to the first embodiment in FIG.
1, 12 and 13 are obtained.

[0017]

As described above, the present invention can use three less photomasks than the conventional manufacturing method. As shown in FIGS. 7 to 9, the CVD deposition step and the etching step are increased, but the number of the lithography steps having a relatively high manufacturing cost is reduced, and the effect that the manufacturing cost is reduced as a whole is obtained. In addition, since the present invention uses less photolithography steps, the yield is improved, and as a result, the manufacturing cost is further reduced.

Further, according to the present invention, even in the case of n-p gate CMOS, n
Phosphorus doping can be used for the gate electrode of the channel MOSFET. For this reason, the doping concentration of the electrode can be increased as compared with the conventional technology, so that there is an effect that the device characteristics are improved as shown in FIG. or,
Since the present invention uses one sidewall thickness for the n-channel MOSFET and the other for the p-channel MOSFET, the p-channel and n-channel source
The drain structure can be optimized separately. Therefore, CMO
This has the effect of improving the device characteristics of S.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a CMOS according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a step subsequent to FIG. 1 in order;

FIG. 3 is a sectional view showing a method of manufacturing a CMOS according to a second embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a step subsequent to FIG. 3 in order;

FIG. 5 is a sectional view showing a conventional CMOS manufacturing method in the order of steps.

FIG. 6 is a cross-sectional view showing a step subsequent to FIG. 5 in order;

FIG. 7 is a view showing a manufacturing process flow of the first embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process flow according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process flow of a conventional technique.

FIG. 10 is a diagram showing a comparison between transistor drain currents according to the present invention and the prior art.

FIG. 11 is a diagram showing a comparison between the yields of the present invention and the prior art.

FIG. 12 is a diagram showing a comparison between junction leak currents according to the present invention and the prior art.

FIG. 13 is a diagram showing the dependence of the threshold voltage on the gate electrode length in the present invention and the prior art.

[Explanation of symbols]

Reference Signs List 101 p-type substrate 102 n-well 103 p-well 104 field oxide film 105 gate oxide film 106 gate electrode of polysilicon 107 silicon nitride film for ion implantation mask 108 silicon oxide film for hot phosphoric acid etching mask 109 source of pMOSFET P ^- region of drain 110 silicon oxide film for pMOSFET sidewall 111 pMOSFET sidewall 112 pMOSFET source / drain p ⁺ region 113 nMOSFET source / drain n ^- region 114 silicon for nMOSFET sidewall n of the source and drain of the n ⁺ region 117 titanium 118 titanium silicide 119 source and drain sidewalls 116 nMOSFET oxide film 115 nMOSFET ^- Photoresist mask 120 source and drain of the phosphorus ions implanted frequency p ^- region boron ion implantation photoresist mask 121 photoresist mask arsenic ion implantation of the silicon oxide film 122 sidewall 123 of the source-drain n ⁺ region for the sidewall 124 Photoresist mask for BF ₂ ion implantation in p ⁺ region of source / drain 125 Photoresist for CMOS source / drain formation 126 Side wall 127 n ⁺ arsenic region for source / drain of nMOSFET 128 Silicon oxide film 129 Side wall 130 Source for nMOSFET N ⁺ phosphorus region of drain 131 silicon oxide film 132 sidewall

Claims (2)

(57) [Claims] In a method of forming a first conductivity type channel MOSFET and a second conductivity type channel MOSFET of a CMOS integrated circuit on one principal surface on a semiconductor substrate, a step of forming gate electrodes of both channel MOSFETs; Depositing a double layer comprising a silicon nitride film as a lower layer and a silicon oxide film as an upper layer on a surface, and selectively removing the silicon oxide film of the double layer from a region where the first conductivity type channel MOSFET is formed; The first conductivity type channel MO
Forming a side wall of the silicon nitride film on a side of a gate electrode of the SFET;
Forming a first relatively high impurity concentration first conductivity type region of the source / drain of the ET; removing a side wall of the silicon nitride film of the first conductivity type channel MOSFET; Forming a first conductivity type region having a relatively low impurity concentration in the source and drain of the first conductivity type channel MOSFET;
Forming a side wall of a first insulating film on a side of a gate electrode of the ET, and removing the double-layered silicon oxide film remaining in a region where the second conductivity type channel MOSFET is formed;
Forming a second relatively high impurity concentration first conductivity type region of the source and drain of the first conductivity type channel MOSFET; and forming the second conductivity type channel MOSFET.
Removing the double-layered silicon nitride film remaining in the T region; and forming a second conductivity type region having a relatively low impurity concentration in the source and drain of the second conductivity type channel MOSFET; The second conductivity type channel MOS
Forming a side wall of a second insulating film on a side portion of the gate electrode of the FET, and forming a second conductivity type region having a relatively high impurity concentration of a source / drain of the second conductivity type channel MOSFET. A method for manufacturing a semiconductor device, comprising: 2. A method of forming a first conductivity type channel MOSFET and a second conductivity type channel MOSFET of a CMOS integrated circuit on one principal surface on a semiconductor substrate, wherein a step of forming gate electrodes of both channel MOSFETs is performed. Depositing a double layer comprising a silicon nitride film as a lower layer and a silicon oxide film as an upper layer on the surface; and selectively removing the double layer from a region where the second conductivity type channel MOSFET is formed; Forming a second conductivity type region having a relatively low impurity concentration at the source / drain of the type channel MOSFET, forming a side wall of a first insulating film on a side of a gate electrode of the second conductivity type channel MOSFET, Removing the double layer silicon oxide film remaining in the first conductivity type channel region; and removing the second conductivity type channel MOS.
Forming a second conductivity type region having a relatively high impurity concentration in the source / drain of the FET; removing the double-layer silicon nitride film remaining in the first conductivity type channel MOSFET region; First conductivity type channel MO
Forming a first conductivity type region having a relatively low impurity concentration in the source / drain of the SFET; forming a side wall of a second insulating film on a side portion of a gate electrode of the first conductivity type channel MOSFET; Forming a first conductivity type region having a relatively high impurity concentration in the source / drain of the one conductivity type channel MOSFET.