JPH04179183A - Wiring board - Google Patents

Wiring board

Info

Publication number
JPH04179183A
JPH04179183A JP2302353A JP30235390A JPH04179183A JP H04179183 A JPH04179183 A JP H04179183A JP 2302353 A JP2302353 A JP 2302353A JP 30235390 A JP30235390 A JP 30235390A JP H04179183 A JPH04179183 A JP H04179183A
Authority
JP
Japan
Prior art keywords
wiring
board
input
conductor pattern
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2302353A
Other languages
Japanese (ja)
Inventor
Hiroyuki Nitta
博幸 新田
Hideki Osaka
英樹 大坂
Kenichi Saito
賢一 斎藤
Yoshiaki Kitatsume
吉明 北爪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2302353A priority Critical patent/JPH04179183A/en
Publication of JPH04179183A publication Critical patent/JPH04179183A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means

Landscapes

  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To enable a noise voltage emitted from a wiring pattern to be estimated at the layout design phase of a printed board by providing a printed-circuit board with a wiring pattern and a signal input/output circuit that serve to quantitatively measure noise voltage induced by reflections, cross talks, EMI, or the like. CONSTITUTION:In an experimental wiring board 1, the waveforms of the reflected waves of input signals are observed by wirings 20-23 different in width, whereby the characteristic impedance and the propagation constant of the wirings 20-23 can be obtained. In a cross talk experiment, a connection pin 62 of one of parallel wires of a conductor pattern is connected to a connection pin 61 which serves as an input terminal of the applied signal or an output terminal connection pin 70 of an IC, whereby pulse signals are inputted to the conductor pattern. An input/output terminal 63 of the other of the parallel wires of the conductor pattern and the other end of the conductor pattern are connected to connection parts 60-70, whereby the various terminated states can be selected. As mentioned above, in a cross talk measuring experiment, measurements can be executed changing the conductor patterns in terminal load conditions. Basing on these measurement data and a theory, a relation between a physical structure size, electrical characteristics and a cross talk voltage can be analyzed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、配線基板上での電磁気的特性や現象を実験、
測定するための実験装置に係り、特に、反射、クロスト
ーク、E M、 Iを測定するための実験配線基板及び
実験装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on experiments and experiments on electromagnetic characteristics and phenomena on wiring boards.
The present invention relates to an experimental device for measuring, and in particular, to an experimental wiring board and an experimental device for measuring reflection, crosstalk, EM, and I.

〔従来の技術〕[Conventional technology]

一般に、高速パルス伝送基板では、クロック周波数の高
速化に伴いタロスト−り、反射、EMIなどの雑音の発
生が問題となっている。これらの配線基板上に発生する
雑音に対しては、各回路をレイアウトした後、実際にプ
リン1へ基板を作成し、その回路布線上でどのような雑
音が発生しているか定量的な測定を行い、対策を講じて
いた。特開平1−28885号公報に記載されているよ
うに、回路基板上の導体パターンの電気的特徴は配線基
板を作成して、その導体パターンの諸特性を測定して評
価を行っていた。つまり、各回路基板に対し、実際に基
板を作成しないと、発生する雑音の定量的な値は分から
なかった。このため開発工程が長期化していた。
Generally, in high-speed pulse transmission boards, as the clock frequency increases, the generation of noise such as tarost distortion, reflection, and EMI has become a problem. Regarding the noise generated on these wiring boards, after laying out each circuit, we actually create a board for Print 1 and quantitatively measure what kind of noise is generated on the circuit wiring. and took measures. As described in Japanese Unexamined Patent Publication No. 1-28885, the electrical characteristics of a conductor pattern on a circuit board have been evaluated by preparing a wiring board and measuring various characteristics of the conductor pattern. In other words, the quantitative value of noise generated for each circuit board could not be determined unless the board was actually created. As a result, the development process was prolonged.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来のように各回路基板のレイアウトパターン
毎に基板作成および雑音測定を行わなければ発生する雑
音が分からないのであれば、レイアウトパターンを変更
する度に、基板作成および雑音測定を行わなければ雑音
対策を講じることができない。そのため開発工程の長期
化を招いていた。
However, if it is impossible to know the noise generated unless you create a board and measure noise for each layout pattern of each circuit board, as in the past, you have to create a board and measure noise every time you change the layout pattern. Noise countermeasures cannot be taken. This led to a prolonged development process.

本発明の目的はこの問題点を解決するものであり、プリ
ン1〜基板のレイアウト設計の段階で、その布線パター
ンより発生する雑音電圧を予測可能とするための、実装
実験基板、及び、装置を提供することにある。
The purpose of the present invention is to solve this problem, and to provide a mounting experiment board and an apparatus for making it possible to predict the noise voltage generated from the wiring pattern at the stage of layout design of the printed circuit board 1 to the board. Our goal is to provide the following.

〔課題を解決するための手段〕[Means to solve the problem]

この目的を達成するため、本発明の配線基板は、基板上
にクロス1−一り、反射、EMIなどの雑音測定実験用
に、線幅、平行線長、平行線間間隔、シリアル布線にお
ける分岐長、ラジアル布線長をパラメータとした実装実
験が行えるように布線パターンを設けた構成となってい
る。
To achieve this objective, the wiring board of the present invention is designed to measure line width, parallel line length, distance between parallel lines, serial wiring, etc. The configuration is such that a wiring pattern is provided to allow implementation experiments using branch length and radial wiring length as parameters.

これらから得た実験データの電磁気学的解析により、配
線パターンの物理的配置と電気的特性から雑音発生を予
測可能とする。これにより、基板設計段階から雑音対策
を講じることができ、基板の開発工程を短縮化すること
ができる。
Electromagnetic analysis of the experimental data obtained from these experiments makes it possible to predict noise generation from the physical layout and electrical characteristics of wiring patterns. As a result, noise countermeasures can be taken from the board design stage, and the board development process can be shortened.

〔作用〕[Effect]

この構成により、クロストーク、反射波形が、様々な測
定条件で測定され線路の基本的な定数である特性インピ
ーダンス、伝搬速度も求めることができる。
With this configuration, crosstalk and reflected waveforms can be measured under various measurement conditions, and characteristic impedance and propagation speed, which are fundamental constants of the line, can also be determined.

平行布線の、パルスを印加するドライブラインとクロス
トーク電圧の誘導されるセンスラインの各点で波形を観
測することにより、タロスト−り・3 ・ 電圧とドライブ人力パルスと物理的構成サイズとの対応
が求められる。
By observing the waveforms at each point of the drive line that applies pulses and the sense line where crosstalk voltage is induced in parallel wiring, we can calculate the relationship between voltage, drive human power pulse, and physical configuration size. A response is required.

また、入力波形と反射波形の関係から反射係数、特性イ
ンピーダンスが求められる。
Further, the reflection coefficient and characteristic impedance are determined from the relationship between the input waveform and the reflected waveform.

これらの実験データと理論との対応により、配線パター
ンの物理的構成サイズと電気的特性から誘導雑音を定量
的に予測することが可能となる。
The correspondence between these experimental data and theory makes it possible to quantitatively predict induced noise from the physical configuration size and electrical characteristics of wiring patterns.

このため、基板設計段階で雑音を誤動作するレベル以下
となるように設計することができる。
Therefore, it is possible to design the board so that the noise is below the level that would cause malfunctions at the board design stage.

〔実施例〕〔Example〕

以下、本発明の実施例について詳細に説明する。 Examples of the present invention will be described in detail below.

まず、本発明の第一の実施例の実装実験基板のレイアウ
ト図を第1図に示す。第1図の1−は四層配線基板であ
り、11〜]4はそれぞれ平行布線間隔0.1,0.1
5,0.2,0.3mmとした平行布線であり、1−5
〜17は布線間隔が同じで平行線長をそれぞれ1. O
、J−5、20、25c mとした平行布線の導体パタ
ーンである。30〜32は入力端から複数の出力端へ放
射状に配線したラジアル布線であり、それぞれ布線長が
異なる。
First, FIG. 1 shows a layout diagram of a mounting experiment board according to a first embodiment of the present invention. 1- in FIG. 1 is a four-layer wiring board, and 11-]4 are parallel wiring intervals of 0.1 and 0.1, respectively.
5, 0.2, 0.3mm parallel wiring, 1-5
-17 have the same wiring spacing and the parallel wire length is 1. O
, J-5, 20, and 25 cm parallel wiring conductor patterns. 30 to 32 are radial wires that are wired radially from the input end to a plurality of output ends, and each wire has a different length.

・4 ・ 41〜43は一本の布線に対し複数の負荷が繁がってい
るシリアル布線の導体パターンであり、それぞれ分岐長
が異なり、入出力部51に接続可能である。50,5]
、は導体パターンと測定装置との入出力部である。第2
図は入出力部50の詳細を示したものである。第2図の
60はパルスジェネレータなどの信号発生機からの印加
信号の接続コネクタで、61はコネクタ60から引き出
した接続ピンである。62.63は平行布線導体パター
ンの信号接続ピンである。64ないし70は1−4ピン
DIPソケツトの接合端子から引出した信号接続部であ
る。これら接続ピン6]−ないし70の接合により平行
布線導体パターンに、直接。
・4・ 41 to 43 are conductor patterns of serial wiring in which a plurality of loads are connected to one wiring, each having a different branch length, and can be connected to the input/output section 51. 50,5]
, is an input/output section between the conductive pattern and the measuring device. Second
The figure shows details of the input/output section 50. Reference numeral 60 in FIG. 2 is a connector for connecting an applied signal from a signal generator such as a pulse generator, and 61 is a connection pin drawn out from the connector 60. 62 and 63 are signal connection pins of parallel wiring conductor patterns. 64 to 70 are signal connection parts drawn out from the connection terminals of the 1-4 pin DIP socket. These connecting pins 6] to 70 are connected directly to the parallel wiring conductor pattern.

印加信号6oを接続することも可能であり、14ピンD
IP(7)ICデバイス(INVERTER。
It is also possible to connect the applied signal 6o, 14 pin D
IP (7) IC device (INVERTER.

N A、 N D )の入出力端を接続することも可能
である。また、接続ピン71はグランドに接続しており
、平行布線導体パターン63を接続ピン71に接続する
ことでグランドに終端することもできる。
It is also possible to connect the input and output terminals of N A and N D . Further, the connecting pin 71 is connected to the ground, and by connecting the parallel wiring conductor pattern 63 to the connecting pin 71, it can be terminated to the ground.

次に、この実験配線基板での実験方法について説明する
。第1図の布線幅の異なる布線2o〜23で入力信号の
反射波形を観測することにより、各′FA幅での特性イ
ンピーダンス、伝搬定数を求めることができる。クロス
1−一りの実験では、第2図の平行線の一方の導体パタ
ーンの接続ピン62を印加信号の入力部である接続ピン
6]、又は、ICの出力端接続ピン70と接続すること
によりパルス信号を導体パターンに印加する。また、他
方の平行布線の導体パターンの入出力部63とその導体
パターンの他端は接続部60〜76と接続することによ
り各種の終端状態を選ぶことができる。例えば、接続ピ
ン63と71をg路の特性インピーダンスと同じ値の抵
抗で接続することにより整合終端することができ、IC
の入力端接続ピン69と接続することで入力端接続状態
を実現することができる。このように、クロストーク測
定実験で、ドライブライン、センスラインの各導体パタ
ーンの終端の負荷条件を変化させて測定を行うことがで
きる。これらの測定データと理論により、物理的構成サ
イズ、電気的特性とタロストーク電圧の関係を解析する
ことができる。また、30〜32のラジアル配線パター
ンや41〜43のシリアル配線パターンにより、配線パ
ターンの違いによる多重反射の特性を実験により検証す
ることができる。これらの実験及び解析により、基板の
設計段階でこ才りら物理的+’lJ成サイズ、電気的特
性から反射、クロストーク電圧を予測することが可能で
ある。
Next, an experimental method using this experimental wiring board will be explained. By observing the reflected waveform of the input signal on the wiring lines 2o to 23 having different wiring widths in FIG. 1, the characteristic impedance and propagation constant at each FA width can be determined. In the cross 1-1 experiment, connect the connecting pin 62 of the conductor pattern on one side of the parallel lines in FIG. A pulse signal is applied to the conductor pattern. Moreover, various termination states can be selected by connecting the input/output section 63 of the other parallel wiring conductor pattern and the other end of the conductor pattern to the connection sections 60 to 76. For example, matching termination can be achieved by connecting connection pins 63 and 71 with a resistor with the same value as the characteristic impedance of the g path, and
By connecting to the input end connection pin 69 of , an input end connection state can be realized. In this manner, crosstalk measurement experiments can be performed by changing the load conditions at the ends of each conductor pattern of the drive line and sense line. Using these measurement data and theory, it is possible to analyze the relationship between physical component size, electrical properties, and Talostok voltage. Further, by using the radial wiring patterns 30 to 32 and the serial wiring patterns 41 to 43, it is possible to verify by experiment the characteristics of multiple reflection due to differences in the wiring patterns. Through these experiments and analyses, it is possible to predict reflection and crosstalk voltage from the physical size and electrical characteristics at the board design stage.

次に、第3図を用いて本発明の第二の実施例について説
明する。第二の実施例は第一の実施例と同様な基板に面
実装部品を搭載するようにしたものである。第3図は、
第一の実施例の入出力部5oの詳細を示した図である。
Next, a second embodiment of the present invention will be described using FIG. In the second embodiment, surface-mounted components are mounted on a board similar to the first embodiment. Figure 3 shows
It is a diagram showing details of an input/output unit 5o of the first embodiment.

第3図の60aはパルスジェネレータなどの信号発生機
からの印加信号の接続コネクタで、61−aはコネクタ
60aから引き出した接続ピンである。62a、63a
は平行布線導体パターンの信号接続ピンである。
60a in FIG. 3 is a connector for connecting an applied signal from a signal generator such as a pulse generator, and 61-a is a connecting pin drawn out from the connector 60a. 62a, 63a
are signal connection pins with parallel wiring conductor patterns.

64a〜70aは14ピンsopの接合端子から引出し
た信号接続部である。第一の実施例と同様にこれら接続
ピン61. a〜70aの接合により平・ 7 ・ 行布線導体パターンに、直接、印加信号60aを接続す
ることも可能であり、14ピンsOPのICデバイス(
TNVERTER,NA、ND) の入出力端を接続す
ることも可能である。また、接続ピン71 aはグラン
ドに接続しており、平行布線導体パターン63,1を接
続ピン71 aに接続することでグランドに終端するこ
ともできる。これにより面実装部品を搭載した場合につ
いても、第一の実施例と同様に実験を行うことができ同
様の効果が得られる。
64a to 70a are signal connection portions drawn out from the connection terminals of the 14-pin SOP. As in the first embodiment, these connecting pins 61. It is also possible to connect the applied signal 60a directly to the flat, 7, and row wiring conductor patterns by joining a to 70a, and it is possible to connect the applied signal 60a directly to the flat, 7, and row wiring conductor patterns, and it is possible to connect the applied signal 60a directly to the 14-pin SOP IC device (
It is also possible to connect the input and output terminals of TNVERTER, NA, ND). Further, the connecting pin 71a is connected to the ground, and can be terminated to the ground by connecting the parallel wiring conductor pattern 63,1 to the connecting pin 71a. As a result, even when surface-mounted components are mounted, experiments can be conducted in the same manner as in the first embodiment, and similar effects can be obtained.

次に、第4図を用いて本発明の第三の実施例について説
明する。第三の実施例は第一、二の実施例で説明した実
装実験基板を含んだ実装実験装置である。第4図はこの
実装実験装置の構成図で、80はパーソナルコンピュー
タ(以下PC)、81は入力信号を生成するパルスジェ
ネレータ(以下PG)で(E P −I Bケーブル等
でpcと接続しており、信号出力は実験基板に接続され
ている。82は実験用基板で、この実験用基板82はコ
ネクタ83でPCの拡張スロットに接続可能な・8  
・ ものとなっている。PG81をPC80で制御すること
により入力波形の立上り時間、ピーク電圧等を変化させ
ることができ、第一の実施例の基板と同様な実験回路に
より測定した出力波形をA/D変換機84でアナログデ
ータからデジタルデータに変換し、PC80にそのデー
タを取り込み、データ処理を行うことができる。このよ
うに、測定とデータ処理をPCで自動的に行うことによ
り測定作業効率が上がり第一、二の実施例と同様な効果
が得られる。
Next, a third embodiment of the present invention will be described using FIG. 4. The third embodiment is a mounting experiment apparatus including the mounting experiment board described in the first and second embodiments. Figure 4 is a configuration diagram of this implementation experiment equipment, where 80 is a personal computer (hereinafter referred to as PC), 81 is a pulse generator (hereinafter referred to as PG) that generates an input signal (connected to the PC with an E P-I B cable, etc.). The signal output is connected to an experimental board. 82 is an experimental board, and this experimental board 82 can be connected to an expansion slot of a PC with a connector 83.
・ It has become a thing. By controlling the PG81 with the PC80, the rise time, peak voltage, etc. of the input waveform can be changed, and the output waveform measured using the same experimental circuit as the board of the first embodiment is converted into an analog signal using the A/D converter 84. It is possible to convert the data into digital data, import the data into the PC 80, and perform data processing. In this way, by automatically performing measurement and data processing on a PC, the efficiency of measurement work is increased and the same effects as in the first and second embodiments can be obtained.

〔発明の効果〕〔Effect of the invention〕

本発明では、配線基板上のクロストーク、反射、伝搬速
度が基板の構成やレイアウトにどのように依存している
かを知ることができるため、配線基板を設計する段階で
発生する雑音が予測でき、この段階で雑音対策を講じる
ことができる。このため、試作基板を作成してからしか
雑音対策を講じない場合に比べて、配線基板の開発工数
を短期化することができる。
In the present invention, it is possible to know how crosstalk, reflection, and propagation speed on a wiring board depend on the configuration and layout of the board, so it is possible to predict noise that will occur at the stage of designing a wiring board. At this stage, noise countermeasures can be taken. Therefore, compared to the case where noise countermeasures are taken only after creating a prototype board, the number of man-hours required for developing a wiring board can be shortened.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第一の実施例の実装実験基板のブロッ
ク図、第2図は第1図の入出力部の説明図、第3図は第
二の実施例である第1図の人出力部相当の説明図、第4
図は第1図の実装実験基板を含んだ実装実験装置の説明
図である。 1・・・実装実験基板、 11〜〕7・・・平行布線パターン、 30〜32・・ラジアル配線パターン、41〜43・・
・シリアル配線パターン、80・・・パーソナルコンピ
ュータ、 81・・・パルスジェネレータ。 84・・・A/D変換機。 ・11・
FIG. 1 is a block diagram of a mounting experiment board according to the first embodiment of the present invention, FIG. 2 is an explanatory diagram of the input/output section of FIG. 1, and FIG. Explanatory diagram corresponding to the human output section, No. 4
The figure is an explanatory diagram of a mounting experiment apparatus including the mounting experiment board of FIG. 1. 1... Mounting experiment board, 11-7] Parallel wiring pattern, 30-32... Radial wiring pattern, 41-43...
- Serial wiring pattern, 80...Personal computer, 81...Pulse generator. 84...A/D converter.・11・

Claims (6)

【特許請求の範囲】[Claims] 1.プリント基板上の布線において、反射、クロストー
ク、EMIなどの誘導雑音電圧を定量的に測定すること
が可能な配線パターン及び信号入出力部を設けたことを
特徴とする配線基板。
1. A wiring board comprising a wiring pattern and a signal input/output section that can quantitatively measure induced noise voltages such as reflection, crosstalk, and EMI in wiring on a printed circuit board.
2.請求項1の配線基板と、それを測定する測定装置を
備えた実装実験測定装置。
2. A mounting experiment measuring device comprising the wiring board according to claim 1 and a measuring device for measuring the wiring board.
3.請求項1において、配線間隔を0.1mm〜0.3
mmの範囲で変化させた平行布線と、線幅を0.1mm
〜0.3mmの範囲で変化させた単独布線群と、その他
にシリアル布線と、ラジアル布線の各布線パターンを持
つ配線基板。
3. In claim 1, the wiring interval is 0.1 mm to 0.3 mm.
Parallel wiring changed in the range of mm and line width of 0.1 mm
A wiring board with wiring patterns of a single wiring group varied within a range of ~0.3 mm, serial wiring, and radial wiring.
4.請求項1において、実験用ICの入力端子、出力端
子を切り替える手段を持つ配線基板。
4. The wiring board according to claim 1, having means for switching an input terminal and an output terminal of an experimental IC.
5.請求項2において、間隔を0.1mm〜0.3mm
の範囲で変化させた平行布線と、線幅を0.1mm〜0
.3mmの範囲で変化させた単独布線群と、シリアル布
線と、ラジアル布線の各布線パターンを持つ配線基板を
持つ実装実験測定装置。
5. In claim 2, the interval is 0.1 mm to 0.3 mm.
Parallel wiring with a range of 0.1mm to 0.
.. A mounting experiment measurement device that has a wiring board with individual wiring patterns, serial wiring, and radial wiring that are varied within a range of 3 mm.
6.請求項2において、実験用ICの入力端子、出力端
子を切り替える手段を持つ実装実験測定装置。
6. 3. The mounting experiment measuring device according to claim 2, further comprising means for switching an input terminal and an output terminal of the experimental IC.
JP2302353A 1990-11-09 1990-11-09 Wiring board Pending JPH04179183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2302353A JPH04179183A (en) 1990-11-09 1990-11-09 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2302353A JPH04179183A (en) 1990-11-09 1990-11-09 Wiring board

Publications (1)

Publication Number Publication Date
JPH04179183A true JPH04179183A (en) 1992-06-25

Family

ID=17907894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2302353A Pending JPH04179183A (en) 1990-11-09 1990-11-09 Wiring board

Country Status (1)

Country Link
JP (1) JPH04179183A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346835B1 (en) 1999-09-02 2002-02-12 Fujitsu Limited Power-on reset signal preparing circuit
WO2007063949A1 (en) * 2005-11-30 2007-06-07 Fukuoka Industry, Science & Technology Foundation Mounting board capable of evaluating wiring pattern characteristics

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346835B1 (en) 1999-09-02 2002-02-12 Fujitsu Limited Power-on reset signal preparing circuit
WO2007063949A1 (en) * 2005-11-30 2007-06-07 Fukuoka Industry, Science & Technology Foundation Mounting board capable of evaluating wiring pattern characteristics
US7911219B2 (en) 2005-11-30 2011-03-22 Fukuoka Industry, Science & Technology Foundation Wiring pattern characteristic evaluation mounting board
JP4740957B2 (en) * 2005-11-30 2011-08-03 財団法人福岡県産業・科学技術振興財団 Wiring pattern characteristics evaluation mounting board
KR101286488B1 (en) * 2005-11-30 2013-07-16 자이단호진 후쿠오카켄 산교·가가쿠기쥬츠신코자이단 Mounting board capable of evaluating wiring pattern characteristics

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