JPH0265360U - - Google Patents
Info
- Publication number
- JPH0265360U JPH0265360U JP14339188U JP14339188U JPH0265360U JP H0265360 U JPH0265360 U JP H0265360U JP 14339188 U JP14339188 U JP 14339188U JP 14339188 U JP14339188 U JP 14339188U JP H0265360 U JPH0265360 U JP H0265360U
- Authority
- JP
- Japan
- Prior art keywords
- insulating
- source
- drain electrodes
- thin film
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010408 film Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims 2
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Description
第１図〜第３図は本考案の第一実施例を示して
おり、第１図はこの実施例に係る薄膜トランジス
タの構成斜視図、第２図は第１図の―面断面
図、第３図Ａ〜Ｊは第一実施例に係る薄膜トラン
ジスタの製造工程を示す説明図を夫々示し、また
、第４図〜第５図は本考案の第二実施例を示して
おり、第４図はこの実施例に係る薄膜トランジス
タの構成斜視図、第５図は第４図の―面断面
図を示し、また、第６図及び第８図は従来におけ
る薄膜トランジスタの構成斜視図、第７図は第６
図の―面断面図、第９図は第８図の―面
断面図、第１０図は第９図のＡで示す部位の拡大
図を示している。
［符号の説明］、１……基板、２……ゲート電
極、３……ゲート絶縁膜、４……凹溝、５……第
一アモルフアス半導体層、７……ソース電極、８
……ドレイン電極。
1 to 3 show a first embodiment of the present invention, in which FIG. 1 is a perspective view of the structure of a thin film transistor according to this embodiment, FIG. Figures A to J show explanatory diagrams showing the manufacturing process of the thin film transistor according to the first embodiment, and Figures 4 to 5 show the second embodiment of the present invention. FIG. 5 is a perspective view of the configuration of a thin film transistor according to an embodiment, and FIG. 5 is a cross-sectional view taken along the plane of FIG.
FIG. 9 is a cross-sectional view of FIG. 8, and FIG. 10 is an enlarged view of the portion indicated by A in FIG. 9. [Explanation of symbols] 1...substrate, 2...gate electrode, 3...gate insulating film, 4...groove, 5...first amorphous semiconductor layer, 7...source electrode, 8
...Drain electrode.
Claims (1)
体層と、この半導体層に接続されたソース・ドレ
イン電極と、絶縁層を介し上記半導体層に対向し
て配置されたゲート電極とを備える薄膜トランジ
スタにおいて、 上記ソース・ドレイン電極の互いに対向しない
側の端部を絶縁層の厚み方向でゲート電極のソー
ス・ドレイン方向両端部から離れる方向へ折曲げ
て配置したことを特徴とする薄膜トランジスタ。 (2) 上記絶縁層が絶縁性基板から順に積層され
たエツチング剤可溶性の第一絶縁膜とエツチング
剤難溶性の第二絶縁膜とで構成され、エツチング
処理により部分的に除去された第一絶縁膜と第二
絶縁膜とで形成される凹溝にソース・ドレイン電
極を着膜させてソース・ドレイン電極の互いに対
向しない側の端部が折曲げ配置されていることを
特徴とする実用新案登録請求の範囲第１項記載の
薄膜トランジスタ。[Claims for Utility Model Registration] (1) An insulating substrate, a semiconductor layer provided on this substrate, source/drain electrodes connected to this semiconductor layer, and opposing to the semiconductor layer through an insulating layer. In the thin film transistor, the end portions of the source/drain electrodes that do not face each other are bent in the thickness direction of the insulating layer in a direction away from both end portions of the gate electrode in the source/drain direction. A thin film transistor featuring: (2) The insulating layer is composed of a first insulating film soluble in an etching agent and a second insulating film hardly soluble in an etchant, which are laminated in order from the insulating substrate, and the first insulating film is partially removed by an etching process. Registration of a utility model characterized in that source/drain electrodes are deposited in a groove formed by a film and a second insulating film, and the ends of the source/drain electrodes that do not face each other are bent. A thin film transistor according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14339188U JPH0737324Y2 (en) | 1988-11-04 | 1988-11-04 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14339188U JPH0737324Y2 (en) | 1988-11-04 | 1988-11-04 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0265360U true JPH0265360U (en) | 1990-05-16 |
| JPH0737324Y2 JPH0737324Y2 (en) | 1995-08-23 |
Family
ID=31410173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14339188U Expired - Fee Related JPH0737324Y2 (en) | 1988-11-04 | 1988-11-04 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0737324Y2 (en) |
-
1988
- 1988-11-04 JP JP14339188U patent/JPH0737324Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0737324Y2 (en) | 1995-08-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |