JPH0265157A - Master slice type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase bus driving capacity without extension of a driver by wiring a drive transistor to a transistor within an unused I/O cell in an I/O cell region as to form it. CONSTITUTION:As a necessary logic system can be constituted within one chip in case of high integration in a master slice type LSI, unused ones arise in I/O cell regions for interface with the outside. Now, in a master slice type IC device with a master chip 1, where a basic cell 2 region, a wiring channel 3, and an I/O cell 4 region are formed in unwired conditions, logical blocks 5, 7, and 9, where an optional variable wiring pattern is provided in each region on the master chip 1, an internal bus 11, and a bus driver 13 having a drive transistor, a drive master is formed by wiring it to elements 22 and 23 within unused cells 24 inside the I/O cell 4 region. According to this constitution, by utilizing a vacant I/O cell effectively a bus driver of large driving capacity can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a master slice type LSI, and particularly relates to an improvement of a bus driver in a master slice type LSI that is made into a large chip and has an enlarged internal bus network. The aim of this research is to provide a Yasuta slice-type LSI equipped with a bus driver that can improve bus drive capability without adding new drive transistors, and the basic cell area, wiring channel, and input/output cell area are A logic block is created by forming an arbitrary variable wiring pattern in each fi area on a master chip formed in advance in an end-connected state, and on the master chip.
In a master slice semiconductor integrated circuit device in which a bus driver having an internal bus and a drive transistor is formed, the drive transistor forms wiring patterning on transistors included in unused input/output cells in the area of the input/output cells. It is composed of

[Industrial application field]

The present invention relates to a master slice type LSI, and in particular to an improvement of a bus driver in a master slice type LSI that is made into a large chip and has an enlarged internal bus network.

The master slice type LSr is suitable for manufacturing various gate arrays. Master slice type LSI A master chip is created by creating a common pattern for the diffusion layer of the Sl, and only the wiring layer is individually designed according to the specifications requested by the user. L for production
It is SI.

According to this master slice type LSI, the delivery time of the LSI can be shortened by forming the diffusion layer into a common pattern.

With this master slice type LSI, MPU (Micr
o When creating a Processor Unit),
ALtJ(8rithn+ctic Logic
unit ), RAM (Ilando Acc
In addition to a plurality of logic blocks such as ESS Henory), an internal bus circuit connecting each logic block is formed on the master chip.

The internal bus circuit includes a bus transceiver that transmits and receives data between each logical block, and a bus network that transfers data to the path transceiver. A path transceiver consists of a bus receiver that receives data from a bus network and a bus driver that sends data to the bus network. Further, the bus driver includes a control section that controls the transmission of output data of the logic block and a drive transistor that drives the bus network.The present invention relates to this drive transistor.

Due to advances in semiconductor technology and demands for improved functionality of LSIs, LSIs are generally becoming larger in scale, and the number of logic blocks mounted on each chip tends to increase. Such larger chips require longer internal bus circuits that connect each logic block (
(for example, in terms of quantity), and accordingly, it is necessary to increase the driving capability of the drive transistor.

[Conventional technology]

First, a brief overview of the master slice type LSI will be provided. FIG. 3 shows an outline of a CMOS gate array master slice type LSI.

A master slice type LSI includes a basic cell area consisting of a plurality of basic cells 2 on one semiconductor substrate, a wiring channel 3 for connecting each basic cell 2, and a plurality of input/output cells (hereinafter referred to as I10 cells 4). , ) is formed in advance to form a master chip 1, and a wiring pattern is formed on the basic cell 2, wiring channel 3, and I10 cell 4 according to an order from the user side to complete the process. This is a so-called custom IC.

The area of basic cell 2 consists of two or more pairs of basic cells 2 in the Y direction using 0MO3)-transistors to form one row of basic cells, and the basic cell rows are spaced between them in the X direction. The wires are laid out in a repeating pattern with wiring channels 3 interposed in the end-connected state.

A plurality of I10 cells 4 are arranged around the peripheral edge of the master chip 1, and input/output pads 21 and input/output transistors (0MO3) 22, 23 are formed in a terminal-connected state in advance.

Next, using the above master slice type LSI, MPtJ
When creating fn5 of basic cell 2, as shown in Figure 4,
! JU is used to form logic blocks 5, 7.9 and path transceivers 6.8.10. The formation method is performed by second layer wiring using a custom mask. On the other hand, a bus network 11 is formed using the wiring channels 3. The formation method is the same as above.

Logical blocks 5, 7, and 9 are ALU, RAM, etc. for realizing the functions of the MPU. Bus transceiver 6.8.
10 connects each logic block 5, 7.9 to bus network 1
1 for transferring data and instance I-actions. They are formed for each logical block 5, 7, and 9, respectively.

Here, the configuration of the path transceiver 6 is shown in FIG. This FIG. 5 shows the configuration per bit in detail, and 6-1 to 6. A plurality of bits are provided depending on the number of bits. A bus receiver 12 for receiving data per bit from the bus network 11 of the transceiver 6 to the logic block 5 side, and a bus driver 13 for sending data from the logic block 5 to the bus network 11 side. Become. Pass receiver 12 and bus driver 13
The operation mode switching is performed by logic switching between "H" and "L" of the control signal C.

Next, the configuration of the bus driver 13 is shown in FIG.

This Fig. 6 shows 1 via for 1 minute.
If it is 8 bits, 8 bits are provided in parallel. The bus driver 13 includes a control section 25 that controls the output of input data A using a control signal C, and a drive section 26 that receives the output of the control section 25 and drives the bus network 11. The control unit 25 has a N O'I' gate 15, a NOT gate 16, a NAND gate 14, and a NOR gate 1.
Consists of 7. The drive unit 26 has a power supply voltage V. 0 and ground GND
It consists of CMOS transistors (hereinafter referred to as drive transistors 18 and 19) formed between them. As shown in the truth table of FIG. 7, when the control signal C is "L'", this bus driver 13 transfers the data inputted to the A4i terminal to the bus via the drive transistors 18 and 19 and the X terminal. Output to network 11. On the other hand, when the control signal C="H", the X terminal becomes high impedance Z and is disconnected from the bus network 11.
No data is sent, that is, this control signal C
="H" means that the path receiver 12 is in reception mode.

[Problem to be solved by the invention]

The highlight of the bus driver 13 formed in the above master slice type LSI is the logic blocks 5, 7, 9, . . . , which are connected to the bus network 11 as the master slice type LSI becomes larger in size. The number of bus networks 11 increases (several ny+
It can even extend to ), the drive transistors 18, 19 for driving the bus network 11 require a considerably large drive capacity. In order to improve the driving ability of the drive transistors 18 and 19, it is necessary to use transistors with a large area, which goes against the improvement in the integration density of LSIs.

This problem becomes even more remarkable as LSI chips become larger.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a master slice type LSI equipped with a bus driver that can improve the bus driving ability without adding a new drive transistor.

[Means to solve the problem]

In master slice type LSIs, when the degree of integration improves, the necessary logic system can be realized without using multiple chips.
It can be configured within one chip, and therefore does not require many interfaces with the outside. As a result, an unused I10 cell is created in the I10 cell area for interfacing with the outside. On the other hand, this I
The 10 cell originally transmits a signal to the outside through the I10 pad, and is equipped with an input/output transistor with a large drive capacity. Therefore, the present invention has been constructed as follows, focusing on the above points.

That is, the present invention provides a master chip (1) in which a basic cell (2) region, a wiring channel (3), and an input/output cell (4) region are formed in advance in a wired state, and the master chip (1). A master slice type semiconductor in which a logic block (5, 7, 9), an internal bus (11), and a bus driver (13) having a drive transistor are formed by forming arbitrary variable wiring patterns in each region above. #
In the integrated circuit device, the drive transistor is arranged in an unused input/output cell (2) in the area of the input/output cell (4).
4) The transistors (22, 23) included in the configuration are formed by forming wiring patterning.

[Effect]

According to the present invention having the above configuration, the I10 cell (4)
The transistors (22, 23) included in the unused input/output cells (24) in the area are used as the drive transistors (1819) of the bus driver (13), and the transistors (22, 23) are connected to the bus network (11). ) to drive.

The transistors (22, 23> are originally formed with high driving ability, and are sufficiently connected to the bus network (11).
can be driven. Therefore, according to the present invention, even if a new drive transistor (18.degree. 19) is not added, the large chip size of the master slice type LSI is not unnecessarily promoted.

〔Example〕

Next, embodiments according to the present invention will be described based on the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, portions that overlap with those shown in the conventional example (FIGS. 3 to 8) are given the same reference numerals, and explanations thereof will be omitted.

In this embodiment, the difference from the conventional example is that the driving section 26 of the bus driver 13 is not formed using the area of the basic cell 2, but the unused I10 cell 4 (hereinafter referred to as , this is called an empty I10 cell 24.

), the output transistor (PMO3>22) and the output transistor (NMO3) 23 are utilized, and the control section 25 is formed using the area of the basic cell 2.

That is, as shown in FIG. 8, the output cell 20 of the basic cell 2 usually includes an output transistor 22 and an output transistor 23 of a CMO3)-transistor, and an output pad 21.
and a wiring 27 connected to the output pad 21 from the connection point between the drain and source of the output transistor 22 and the output transistor 23. However, if this output cell 20 is not used, it remains formed on the master slice type LSI as a surplus transistor and is not removed.

Therefore, as shown in FIG. 2, the path transceiver 6 is formed using the basic cells 2 up to the control section 25 of the bus driver 13, and the drive section 26 is formed using the output transistor 22 of the empty I10 cell 24. , output transistor 23
Take advantage of. In this case, the wiring 27 in the empty I10 cell 24
is not wired, but wired so as to lead to the X#i child side. Wiring is performed by second-layer wiring. Note that FIG. 2 shows one bit in the path transceiver 6, and for a plurality of (N) bits, N circuits of FIG. 2 are provided in parallel. Moreover, although the path transceiver 6 has been described above, the same applies to the path transceivers 8 and 10, and the description thereof will be omitted.

Furthermore, since the operations of the control section 25 and the drive section 26 are similar to those shown in FIG. 6, their explanations will be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to effectively utilize the surplus 110 cells generated in a large-chip master slice type LSI, that is, the empty I10 cells, and to configure a bus driver with a large driving capacity. .

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a bus driver according to the invention, Fig. 3 is a basic configuration diagram of a master slice type LSI, and Fig. 4 is a basic cell area and wiring channel. 5 is a block diagram of a path transceiver, FIG. 6 is a circuit diagram of a bus driver, FIG. 7 is an explanatory diagram of the operation of FIG. 6, and FIG. 8 is a circuit diagram of an output cell. 1... Master chip 2... Basic cell 3... Wiring channel 4... I10 cell 5... Logic block 6... Bus transceiver 7... Logic block 8... Pass transceiver 9... ... Logic block 10 ... Path transceiver 11 ... Bus network 12 ... Bus receiver 13 ... Bus driver 21 ... Output pad 22 ... Output transistor 23 ... Output transistor 24 ... Empty I10 Cell 25... Control unit 26... Drive unit Bus driver's route to be completed in the month of sale B 20th master's slice type LSI basics #A mouth 3rd basic ℃ le completion and arrangement Concave leather 42 in the case of the front panel 42 Circuit diagram of the hard-wired inoma bus driver No. 6 Circuit diagram of the bus transceiver failure 20 Ekacell output failure No. B Nagi

Claims (1)

[Claims] 1. A master chip (1) in which a basic cell (2) region, a wiring channel (3), and an input/output cell (4) region are formed in an end-connected state, and the master chip ( 1) Logic blocks (5, 7, 9) and internal buses (1) are formed by forming arbitrary variable wiring patterns in each area above.
1) and a master slice type semiconductor integrated circuit device comprising a bus driver (13) having a drive transistor, wherein the drive transistor is installed in an unused input/output cell (24) in the area of the input/output cell (4). A master slice type semiconductor integrated circuit device, characterized in that it is formed by subjecting transistors (22, 23) included in the circuit to wiring patterning. 2. The device according to claim 1, wherein the bus driver (13
) is the output data (A
); and a control unit (25) that controls the transmission of
The control section (25) is formed by wiring patterning in the area of the basic cell (2). , a master slice characterized in that the drive transistors (22, 23) are formed by wiring patterning transistors included in unused input/output cells (2) in the area of the input/output cells (2). type semiconductor integrated circuit device.